The Datasheet Archive

SF Impression Pixel

Search Stock (3)

  You can filter table by choosing multiple options from dropdownShowing 3 results of 3
Part Manufacturer Supplier Stock Best Price Price Each Buy Part
DS1007S-2 Maxim Integrated Products Rochester Electronics 3,472 $12.29 $9.99
DS1007S-2 Maxim Integrated Products Chip One Exchange 1,507 - -
DS1007S-2+ Maxim Integrated Products Chip One Exchange 2,394 - -

No Results Found

Show More

DS1007S-2 datasheet (5)

Part Manufacturer Description Type PDF
DS1007S-2 Maxim Integrated Products Delay Line, Active, 16nSec Delay, 5V Supply Voltage, 16-SOIC Original PDF
DS1007S-2+ Maxim Integrated Products 7-in-1 Silicon Delay Line Original PDF
DS1007S-2_T&R Dallas Semiconductor 7-in-1 Silicon Delay Line Original PDF
DS1007S-2/T&R Maxim Integrated Products Delay Line, 7-1 Silicon Delay Line, Tape and Reel Original PDF
DS1007S-2+T&R Maxim Integrated Products 7-in-1 Silicon Delay Line Original PDF

DS1007S-2 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2007 - DS1007S-2

Abstract: 56-G4009-001B soic-16
Text: Analysis 0C to +70C RoHS/Lead-Free: No DS1007S-9 DS1007S-2+ DS1007S-14+ DS1007S-2+T&R , 0C to +70C RoHS/Lead-Free: No Materials Analysis DS1007S-2 DS1007S-3 DS1007S-5 DS1007S , delay IN1 1 16 IN3 7 independent buffered delays OUT1 2 15 OUT3 Delay tolerance ± 2 ns Four delays can be custom set between 3 ns IN4 IN2 3 14 IN3 IN1 1 16 and 10 ns OUT2 4 13 OUT4 OUT3 OUT1 15 2 Three delays , ± 2 ns at room temperature. The device is offered in both a 16-pin DIP and a 16-pin SOIC. Since the


Original
PDF DS1007 16-pin 300-mil) DS1007S 56-G4009-001B W16-2* DS1007S-2 56-G4009-001B soic-16
Not Available

Abstract: No abstract text available
Text: FEATURES • All-silicon time delay • 7 independent buffered delays • Delay tolerance ± 2 ns IN , €¢ Auto-insertable, low profile • Surface mount 16-pin SOIC C 1 C 2 IN2 E 3 OUT2 C 4 Vcc C 5 IN1 OUT1 IN5 C 6 OUT5 C IN6 C 7 e 16 15 14 13 12 H H H H IN3 OUT3 IN4 OUT4 2 , times can be set from 3 ns to 40 ns with an accuracy of ± 2 ns at room temperature. The device is , 6ns 9ns 13ns 18ns DS1007- 2 4 6 8 10 12 14 16 DS1007-3 3 3


OCR Scan
PDF DS1007 DS1007 16-PIN 74F04 DS1007.
1998 - DS1007

Abstract: DS1007S DS1007-7 DS1007-6 DS1007-5 DS1007-4 DS1007-3 DS1007-2 DS1007-1 37143
Text: delay · 7 independent buffered delays · Delay tolerance ± 2 ns · Four delays can be custom set between , and precise · Economical · Auto-insertable, low profile IN1 1 16 IN3 OUT1 2 15 , OUT7 OUT5 7 10 IN7 IN6 8 9 IN1 OUT1 1 16 2 15 IN3 OUT3 IN2 , times can be set from 3 ns to 40 ns with an accuracy of ± 2 ns at room temperature. The device is , OUT5 OUT6 OUT7 DS1007-1 3ns 4ns 5ns 6ns 9ns 13ns 18ns DS1007- 2 4


Original
PDF DS1007 DS1007 16-PIN 74F04 DS1007. DS1007S DS1007-7 DS1007-6 DS1007-5 DS1007-4 DS1007-3 DS1007-2 DS1007-1 37143
1995 - DS1007

Abstract: DS1007-1 DS1007-2 DS1007-3 DS1007-4 DS1007-5 DS1007-6 DS1007-7 DS1007S
Text: delay · 7 independent buffered delays · Delay tolerance ± 2 ns · Four delays can be custom set between , and precise · Economical · Auto-insertable, low profile IN1 1 16 IN3 OUT1 2 15 , OUT7 OUT5 7 10 IN7 IN6 8 9 IN1 OUT1 1 16 2 15 IN3 OUT3 IN2 , times can be set from 3 ns to 40 ns with an accuracy of ± 2 ns at room temperature. The device is , OUT5 OUT6 OUT7 DS1007-1 3ns 4ns 5ns 6ns 9ns 13ns 18ns DS1007- 2 4


Original
PDF DS1007 DS1007 16-PIN 74F04 DS1007. DS1007-1 DS1007-2 DS1007-3 DS1007-4 DS1007-5 DS1007-6 DS1007-7 DS1007S
74F04

Abstract: DS1007 DS1007-1 DS1007-2 DS1007S
Text: delays Delay tolerance ± 2 ns Four delays can be custom set between 3 ns and 10 ns Three delays can be , specifications available Quick turn prototypes PIN ASSIGNMENT IN1 Q 1 w 16 OUT1 Q 2 15 IN2 Q 3 14 OUT2 Q 4 , IN1 : 1 U16 J IN3 OUT1 : 2 15 J OUT3 IN2 : 3 14 J IN4 OUT2 : 4 13 J OUT4 Vcc : 5 12 : GND IN5 : 6 , 's specification. The delay times can be set from 3 ns to 40 ns with an accuracy of ± 2 ns at room temperature. The , 13ns 18ns DS1007- 2 4 6 8 10 12 14 16 DS 1007-3 3 3 3 3 10 10 10 DS 1007-4 4 4 4 4 12 12 12 DS


OCR Scan
PDF DS1007 16-pin PS1007 74F04 DS1007-1 DS1007-2 DS1007S
Not Available

Abstract: No abstract text available
Text: tolerance ± 2 ns · Four delays can be custom set between 3 ns and 10 ns · Three delays can be custom set , -in-1 Silicon Delay Line PIN ASSIGNMENT DS1007 [ [_ 1 2 3 4 16 15 14 OUT1 [ IN2 , from 3 ns to 40 ns with an accuracy of ± 2 ns at room temperature. The device is offered in both a 16 , OUT PART NUMBER DELAY TABLE (tPLH) Table 1 PART# DS1007-1 DS1007- 2 DS1007-3 DS1007-4 DS1007 , 7 can be custom set from 9 to 40ns. (Both leading and trailing edge accuracy.) 030194 2 /5 303


OCR Scan
PDF 16-pin DS1007 DS1007S 74F04 DS1007.
Not Available

Abstract: No abstract text available
Text: ASSIGNMENT • All-silicon time delay 1 16 ] IN3 OUT1 [ 2 15 ] OUT3 IN2 [ 3 14 ] IN4 IN1 [ • 7 independent buffered delays • Delay tolerance ± 2 ns â , , low profile IN1 OUT1 C C C 2 16 : 15 1 n 3 14 OUT2 C 4 V cc C , of ± 2 ns at room temperature. The device is offered in both a 16-pin DIP and a 16-pin SOIC. Since , intellectual property rights, please reler to Dallas Semiconductor data books. 2 b m i 3 G ÜGlbPi+H T25


OCR Scan
PDF DS1007 ds1907 DS1007 16-PIN 74F04 DS1007.
74F04

Abstract: DS1007 DS1007-1 DS1007-2 DS1007S
Text: delay • 7 independent buffered delays • Delay tolerance ± 2 ns • Four delays can be custom set , IN3 2 15 ] OUT3 3 14 ] IN4 IN1 C 1 16 H IN3 4 13 ] OUT4 OUT1 C 2 15 H OUT3 IN2 C 3 14 , 's specification. The delay times can be set from 3 ns to 40 ns with an accuracy of ± 2 ns at room temperature. The , DS1007-1 3ns 4ns 5ns 6ns 9ns 13ns 18ns DS1007- 2 4 6 8 10 12 14 16 DS 1007-3 3 3 3 3 10 10 10 DS 1007-4 , .) 021798 2 /5 r This Material Copyrighted By Its Respective Manufacturer DS1007 TIMING DIAGRAM: SILICON


OCR Scan
PDF DS1007 16-pin 74F04 DS1007 DS1007-1 DS1007-2 DS1007S
Not Available

Abstract: No abstract text available
Text: [ • Delay tolerance ± 2 ns IN2 £ • Four delays can be custom set between 3 ns and 10 ns 2 3 OUT2 £ 4 ] ] 14 ] 13 ] 16 IN3 15 OUT3 Vcc C 5 • Three delays can be , IN1 H 1 OUT1 C 2 16 D IN3 15 J OUT3 IN2 C 3 14 OUT2 C 4 13 12 Vcc C 5 IN5 C , of ± 2 ns at room temperature. The device is offered in both a 16-pin DIP and a 16-pin SOIC. Since , . For special requests and rapid delivery, call (214) 450-5348. 2 b m i 3 0 001002G 2fl3 030194 1/5


OCR Scan
PDF DS1007 DS1007 16-PIN 74F04 DS1007.
1999 - 37143

Abstract: DS1007-6 DS1007-5 DS1007-4 DS1007-3 DS1007-2 DS1007-1 DS1007 DS1007S DS1007-8
Text: delay IN1 1 16 IN3 7 independent buffered delays OUT1 2 15 OUT3 Delay tolerance ± 2 ns Four , OUT3 OUT1 15 2 Three delays can be custom set between 9 ns 14 3 IN4 IN2 VCC GND 5 12 and , of ± 2 ns at room temperature. The device is offered in both a 16-pin DIP and a 16-pin SOIC. Since , DS1007-1 3ns 4ns 5ns 6ns 9ns 13ns 18ns DS1007- 2 4 6 8 10 12 14 16 DS1007-3 3 3 3 3 , through Out 7 can be set from 9 to 40 ns (both leading and trailing edge accuracy). 2 of 6 DS1007


Original
PDF DS1007 16-pin DS1007 300-mil) DS1007S 74F04 37143 DS1007-6 DS1007-5 DS1007-4 DS1007-3 DS1007-2 DS1007-1 DS1007-8
Not Available

Abstract: No abstract text available
Text: delays OUT 1 E 2 DS1007 7-in-1 Silicon Delay Line PIN ASSIGNMENT I - IN1 |_ 1 w 16 -1 J IN3 15 E| OUT3 14 ] ] IN4 IN1 C OUT 1 C IN2 E 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 IN3 OUT3 IN4 OUT4 GND OUT 7 IN7 OUT6 · Delay tolerance ± 2 ns · Four delays can be custom set between 3 , 's specification. T he delay times can be set from 3 ns to 40 ns with an accuracy of ± 2 ns at room temperature. T , important information regarding patents and other intellectual property rights please refer to 0 2 2 6 9


OCR Scan
PDF DS1007 16-pin 74F04 DS1007.
DS1237S

Abstract: DS1625 DS1621 DS1259 DS1215 DS1212 DS1211 DS1000M DS1000 DS1640
Text: [ 1 ^ 16 ] vcci vbat[ 2 15 ] vcci Bf[ 3 14 ] nc nc[ 4 13 ] vcco bat[ 5 12 ] vcco rst[ 6 11 ] pf , - attached battery (Vbat) ¡s greaterthan 2 volts. If the battery level should decrease to below 2 volts, the , on RST to high level for 50ns minimum while primary power is valid (see Figure 2 ). When primary power , VççQj 021798 2 /5 This Material Copyrighted By Its Respective Manufacturer DS1259 RESET TIMING Figure 2 +5V Veci Vcco r-r- -JT- rr -zTJ1- TYPICAL APPLICATION Figure 3 021798 3/5 This Material


OCR Scan
PDF DS1259 DS1212 16-pin 2bl413G 0G1442Q DS1237S DS1625 DS1621 DS1259 DS1215 DS1211 DS1000M DS1000 DS1640
Not Available

Abstract: No abstract text available
Text: · All-silicon time delay · 7 independent buffered delays · Delay tolerance ± 2 ns · Four delays can , available · Quick turn prototypes PIN ASSIGNMENT [1 OUT 1 C 2 IN2 [ 3 IN1 OUT2 V cc 15 C 4 , IN7 9 H OUT6 2 IN2 C 3 OUT2 C 4 V cc C 5 IN5 C 6 OUT5 C 7 IN6 C 8 DS1007 16-PIN DIP , custom er's specification. The delay times can be set from 3 ns to 40 ns with an accuracy of ± 2 ns at , PART NUMBER DELAY TABLE (tPLH) Table 1 PART# DS1007-1 DS1007- 2 DS1007-3 D S 1007-4 DS1007-5 DS 1007-6


OCR Scan
PDF DS1007 16-pin 74F04 DS1007.
2BL4

Abstract: DS2011D DS1000M DS1621 DS1234S DS1234 DS1215 DS1211 DS1000 DS1640
Text: mount package PIN ASSIGNMENT vcco[^ 1 14 ] VCCI NC[ 2 13 ] VBAT VCCO m 1 16 m VCCI CËÏ E 3 12 ] A3 NC m 2 15 m VBAT NC ai 3 14 m NC WEI [_ 4 11 ] A2 CËÏ m 4 13 m A3 CEO £ 5 10 , recognition sequence across four address lines (see Tables 1 and 2 ). Prior to entering the pattern recognition , 021798 2 /7 This Material Copyrighted By Its Respective Manufacturer DS1234 ADDRESS INPUT PATTERN Table 1 CYCLE NUMBER Address Inputs 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A3 1 0 1 0 0


OCR Scan
PDF DS1234 16-pin 2bl413G 0G1442Q 2BL4 DS2011D DS1000M DS1621 DS1234S DS1234 DS1215 DS1211 DS1000 DS1640
use of zenner diode in 3 pin regulator circuits

Abstract: DS1640 DS1231S DS1231 DS1215 DS1211 DS1000M DS1000 opto isolator IC DS2011D
Text: Figure 2 ). The comparator monitoring the input pin produces the NMI signal (Pin 7) when the input threshold voltage (Vjp) falls to a level as determined by Mode (Pin 2 ). When the Mode pin is connected to , when the mode pin is connected to Vcc- 022698 2 /9 This Material Copyrighted By Its Respective Manufacturer DS1231/S POWER MONITOR BLOCK DIAGRAM Figure 1 POWER-UP RESET Figure 2 IN Vcc MODE NMÌ TOL , «IL -10 +10 HA 2 Output Current @2.4V !oh 1.0 2.0 mA 5 Output Current @0.4V «OL 2.0 3.0 mA


OCR Scan
PDF DS1231/S 16-pin DS1231 2bl413G 0G1442Q use of zenner diode in 3 pin regulator circuits DS1640 DS1231S DS1215 DS1211 DS1000M DS1000 opto isolator IC DS2011D
DS1640

Abstract: No abstract text available
Text: 50K£2 759Q 200 KHz 12 2Q DS16 6 6 -1 0 0 1 00K£2 2 4 3 ÌÌ 1 .5 19 K ÎÎ 100 KHz 1 6 -P IN S , ­ tiom eter advances 2 % of resistance for every 1% of defaults to the 10% position on power up. The , #74=18% ± 2 % of total resistance. increment. The state of the U/D pin can be changed while CS is , counter value is stored when CS is returned high. 022698 2 /7 r DS1666, DS1666S BLOCK DIAGRAM Figure 2 MODE SELECTION Figure 3 cs INC U/D MODE L H WIPER UP L L WIPER


OCR Scan
PDF DS1666, DS1666S Poi73 001442Q DS1360S DS1380S DS1609S DS1610S DS1640
DS1640

Abstract: No abstract text available
Text: controlled by a 16-cycle pattern recognition sequence across four ad ­ dress lines (see Tables 1 and 2 ). , 021798 2 /7 r DS1234 ADDRESS INPUT PATTERN Table 1 CYCLE NUM BER Address Inputs 0 1 2 , 1 1 CONTROL SELECT Table 2 W EI Battery Control Operation 11 12 13 14 15 , AX UNITS NOTES !cci 5 mA 2 !c c o 80 mA 3 @ V c c o = ^ ccl " 0 2 , BAT -°- 2 6 !b a t 0.1 HA 7 !c c o i 100 HA 5 = ^ BAT " ° - 3^ r


OCR Scan
PDF DS1234 14-Pin 1234S 16-Pin 001442Q DS1360S DS1380S DS1609S DS1610S DS1640
DS1209

Abstract: Zener diode 0740 DS1640
Text: RSTarekeptactiveforaminimumof150mstoallowthe power suppiy to stabilize (see Figure 2 ). The comparator monitoring the input pin produces the NMI signal (Pin 7) when the input threshold voltage (Vjp) falls to a level as determined by Mode (Pin 2 ). , the DS1231 can be interfaced to the AC power line when the mode pin is connected to Vcc- 022698 2 /9 , Figure 1 POWER-UP RESET Figure 2 IN Vcc MODE NMÌ TOL RST GND RST MICROPROCESSOR (-5% Vcc THRESHOLD , Output Voltage @ -500 nA VOH VCC-0.5V Vcc-0.1V V 1, 6 Input Leakage «IL -10 +10 HA 2 Output Current


OCR Scan
PDF DS1231/S 16-pin DS1231 2bl413G 0G1442Q DS1209 Zener diode 0740 DS1640
1999 - transistor C143

Abstract: C144 transistor c225 diode smd transistor C144 Transistor c233 c143 transistor Transistor c226 transistor c223 transistor C147 TRANSISTOR c231
Text: Bill Of Materials Item Quantity 1 2 1 127 Aug. 10,1999 17:04:24 Part 3V Coincell (socket) 0.1uF , ,D5,D6,D8,D9,D10, D11,D12,D13,D14,D15 D4 JP1 JP2 4 5 6 7 8 9 10 1 4 1 2 1 4 41 6.8uF/16V 47pF , Quantity 18 19 20 21 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 1 2 4 6 1 1 2 1 1 1 2 1 1 7 1 1 1 2 1 1 7 7 1 1 1 1 2 12 Aug. 10,1999 17:04:24 Part PCB Footprint Part Spec AMP , 0.025' SQ. POST TH-1X3 1x6HEADER 0.025' SQ. POST TH-1X6 Stacked Dual PS/ 2 Jack DIMM Socket RJ-45 Jack TH


Original
PDF ElanSC520 000MHz 768kHz 333MHz 318MHz ECSMA-25 ECSMA-24 ECPSM29T-32 transistor C143 C144 transistor c225 diode smd transistor C144 Transistor c233 c143 transistor Transistor c226 transistor c223 transistor C147 TRANSISTOR c231
ds1236s

Abstract: battery 038 DS1640
Text: back up 16 RAMs · Optional 16-pin SOIC surface mount package PIN ASSIGNM ENT NC[ vbat 1 2 3 4 5 , (V qqo) at V b a t O- 2 volts at 15 mA. On power-up, as the Vqci supply rises above the bat tery, the , re gardless of the level of V qci- attached battery ( V b a t ) ¡s greaterthan 2 volts. If the bat tery level should decrease to below 2 volts, the BF sig nal is driven low, indicating a low battery , primary power is valid (see Figure 2 ). When primary power is removed after pulsing RST, the V cco output


OCR Scan
PDF DS1259 DS1212 16-pin 001442Q ds1236s battery 038 DS1640
ds1666-010

Abstract: DS-1000 DS1221S DS2107AS ds1010s DS1267 ordering DS1867 ordering information DS1228S DS1640
Text: NC C 1 14 □ NC 2 13 □ Vcc 3 12 □ vB 4 11 □ Vw 5 10 □ VH 6 9 □ Vl 7 8 □ NC 14-PIN DIP , precise amplification of low volume signals. The upper half of the potentiometer advances 2 % of resistance , typical Resistance at tap #74=18% ± 2 % of total resistance. PIN DESCRIPTIONS VH Vl Vw Up/Down (U/D) The , when CS is returned high. 022698 2 /7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 DS1666, DS1666S BLOCK DIAGRAM Figure 2 vL Vw MODE SELECTION Figure 3 CS INC U/D MODE L H WIPER UP L


OCR Scan
PDF DS1666, DS1666S 14-pin 16-pin DS1666-10 DS1666-50 DS1666-100100KÂ DS1666 ds1666-010 DS-1000 DS1221S DS2107AS ds1010s DS1267 ordering DS1867 ordering information DS1228S DS1640
DS2013D

Abstract: DS-1000 ely 0325 DS1640
Text: an orderly shutdown modeE ] vcc ] ] ] NMÏ RST RST 2 · Prevents processor from destroying m , surface mount package DS1231 8-Pin DIP (300 MIL) See Mech. Drawings Section NC Q I IN NC 16 2 3 4 5 6 7 , of 150 ms to allow the power supply to stabilize (see Figure 2 ). The com parator monitoring the input , determ ined by Mode (Pin 2 ). When the M ode pin is connected to V qq , detection o c curs at V jp -. In , ) is achieved and V qq is within nominal limits. In both 022698 2 /9 r DS1231/S POWER


OCR Scan
PDF DS1231/S 1231/S 16-pin DS1231 24-PIN 28-PIN 001442Q DS2013D DS-1000 ely 0325 DS1640
ebl41

Abstract: DS1228S DS1867 ordering information DS1669 Digital Pot IC DS1640
Text: C L1-3 C W3 W4 L4-6 W6 1 2 3 4 5 6 7 8 9 10 ^ 20 19 18 17 16 15 14 13 12 11 o o , °C to +85° C D S 1806 2 0 -P IN DIP (300 MIL) D S 1806S 2 0 -P IN S O IC (300 MIL) D S 1 80 6E 2 0 , specified over the industrial tem perature range. Packages for the device include 2 0 -le a d DIPs, SOICs , first data entered into the shift reg ister, followed by that of potentiom eter- 2 and so forth. Each w , ber the rem aining positions of the potentiom eter wipers. Figure 2 provides the for mat for a w ip e


OCR Scan
PDF DS1806 1806S 001442Q -20-PIN 14-PIN DS1801 DS1803 DS1807 20-PIN DS1033E ebl41 DS1228S DS1867 ordering information DS1669 Digital Pot IC DS1640
DS1666

Abstract: DALLAS SOIC PRODUCT CHANGE DS1211S DS1667-50 DS1667-100 DS1667-10 DS1667 DS1211 DS1000 DS2011D DS1640
Text: stacked such that NINV0 C 1 20 INV0 C 2 19 VB C 3 18 W1 C 4 17 H1 C 5 16 L1 c 6 15 RST c 7 , STACK MULTIPLEXER OP AMP SECTION NINVO 022698 2 /11 This Material Copyrighted By Its , (Figure 2 ). Data can be entered into the 17 bit shift register only when the RST input is at a high level , Its Respective Manufacturer DS1667 WRITING DATA Figure 2 CASCADING MULTIPLE DEVICES Figure 3 , Negative Supply Voltage vB -5.5 GND V 1 Resistor Inputs L, H, W VB - 0.5 Vcc + 0.5 V 2 DC ELECTRICAL


OCR Scan
PDF DS1667 256-position 20-pin 2bl413G 0G1442Q DS1666 DALLAS SOIC PRODUCT CHANGE DS1211S DS1667-50 DS1667-100 DS1667-10 DS1667 DS1211 DS1000 DS2011D DS1640
ic DS2430

Abstract: ds1205v DS1640
Text: 7.62 0.015 0.38 0.120 3.04 0.090 2.23 0.320 8.13 0.008 0.20 0.015 0.38 060794 2 /23 335 M E C H A N IC A L D R A W IN G S 2 4 - TO 40-PIN DIP (600 MIL) .1- i - i i- i i- i. Includes , DS1033Z DS1035Z DS1040Z DS1218S DS1830 DS2430 DS2502 200 Mil Includes: DS1232LPS- 2 DS1620S DS1651S , measured to the cen ter of radius. 2 . All dimensions are shown in inches. PKG DIM A B C D e F G H I J K L , 0.028 0.043 0.185 0.190 0.012 NOTE: 1. Dimensions L3 and L4 are measured to the center of radius. 2


OCR Scan
PDF 28-PIN DS1000 DS1000M DS1003 DS1003M DS1004M DS1005 DS1005M DS1007 DS1010 ic DS2430 ds1205v DS1640
Supplyframe Tracking Pixel