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Maxim Integrated Products
DS1005S-100 - Bulk (Alt: DS1005S-100) DS1005S-100 ECAD Model
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000
Avnet Americas DS1005S-100 0 1 Weeks 91 - - $3.85 $3.52 $3.52 More Info
Rochester Electronics DS1005S-100 7,299 1 $3.71 $3.71 $3.56 $3.41 $3.41 More Info
Maxim Integrated Products
DS1005S-100+ Active Tapped Delay Line 5 TAP 1-IN 20ns ABS 100ns MAX 16-Pin SOIC W - Bulk (Alt: DS1005S-100+) DS1005S-100+ ECAD Model
Distributors Part Package Stock Lead Time Min Order Qty 1 10 100 1,000 10,000
Avnet Americas DS1005S-100+ 0 1 Weeks 91 - - $3.85 $3.52 $3.52 More Info
Rochester Electronics DS1005S-100+ 1,175 1 $3.71 $3.71 $3.56 $3.41 $3.41 More Info

DS1005S-100 datasheet (4)

Part ECAD Model Manufacturer Description Type PDF
DS1005S-100 DS1005S-100 ECAD Model Maxim Integrated Products Delay Line, Active Tapped, 5 Tap, 100nSec Delay, 5V Supply Voltage, 16-SOIC Original PDF
DS1005S-100+ DS1005S-100+ ECAD Model Maxim Integrated Products 5-Tap Silicon Delay Line Original PDF
DS1005S-100/T&R DS1005S-100/T&R ECAD Model Maxim Integrated Products Delay Line, 5-Tap Silicon Delay Line, Tape and Reel Original PDF
DS1005S-100+T&R DS1005S-100+T&R ECAD Model Maxim Integrated Products 5-Tap Silicon Delay Line Original PDF

DS1005S-100 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
74LS

Abstract: delay line 400ns DS1005 DS1005-100 DS1005-125 DS1005-150 DS1005-75 DS1005M DS1005S
Text: . TAP 1 TAP2 TAP3 TAP4 TAP5 DS1005-75* 15ns 30ns 45ns 60ns 75ns DS1005- 100 20ns 40ns 60ns 80ns 100ns , 0.040 0.060 M 0.370 0.420 N 0.160 0.180 3 Equal Spaces At . 100 TOA 45 T-47-13 Silicon Delay Line


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PDF 2bl413D T-47-13 DS1005 14-Pin DS1005M DS1005S 16-Pin 5bl4130 74LS delay line 400ns DS1005-100 DS1005-125 DS1005-150 DS1005-75
Not Available

Abstract: No abstract text available
Text: -75* 15ns 30ns 45ns 60ns 75ns DS1005- 100 20ns 40ns 60ns 80ns 100ns DS1005 , 0.420 N 0.160 0.180 - H - ► 3 Equal Spaces At . 100 TNA L “ t N


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PDF T-47-13 DS1005 14-Pin DS1005M DS1005S 16-Pin DS1005S
2002 - DS1005-60

Abstract: 74LS DS1005M DS1005-75 DS1005-175 DS1005-150 DS1005-125 DS1005-100 DS1005 DS1005S
Text: reliability over hybrid technology is achieved by the combination of a 100 % silicon delay line and industry , ) Table 1 PART NO. TAP 1 DS1005-60 12 ns DS1005-75 15 ns DS1005- 100 20 ns DS1005-125 25 ns , TAP 2 24 ns 30 ns 40 ns 50 ns 60 ns 70 ns 80 ns 100 ns TAP 3 36 ns 45 ns 60 ns 75 ns 90 ns 105 ns 120 ns 150 ns 2 of 6 TAP 4 48 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns 200 ns TAP 5 60 ns 75 ns 100 ns 125 ns 150 ns 175 ns 200 ns 250 ns DS1005 ABSOLUTE


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PDF DS1005 14-pin 16-pin 74F04 DS1005-60 74LS DS1005M DS1005-75 DS1005-175 DS1005-150 DS1005-125 DS1005-100 DS1005 DS1005S
Not Available

Abstract: No abstract text available
Text: combination of a 100 % silicon delay line and industry standard DIP and SOIC S b l M l B Ü 0 0 1 D 0 1 5 , 100 ns DS1005- 100 20 ns 40 ns 60 ns 80 ns DS1005-125 25 ns 50 ns 75 ns 100 ns 125 ns DS1005-150 30 ns 60 ns 90 ns 120 ns 150 ns DS1005-175 35 ns , DS1005-250 50 ns 100 ns 150 ns 200 ns 250 ns Custom delays available 2t.mi30 DGlOQlb , Time 100 tp u Period ms ns 4 (twi) TA = 25°C) CAPACITANCE PARAMETER Input


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PDF DS1005 74F04 DS1005.
1998 - 74LS

Abstract: DS1005 DS1005-100 DS1005-125 DS1005-60 DS1005-75 DS1005M DS1005S
Text: combination of a 100 % silicon delay line and industry standard DIP and SOIC packaging. In order to maintain , DS1005- 100 20 ns 40 ns 60 ns 80 ns 100 ns DS1005-125 25 ns 50 ns 75 ns 100 , DS1005-250 50 ns 100 ns 150 ns 200 ns 250 ns Custom delays available 021798 2/5 , 1 ns 3,4,5,6 Table 1 TYP MAX ns 3,4,5,6 100 Period 4 (tWI) SYMBOL


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PDF DS1005 14-pin 16-pin DS1005S DS1005. 74LS DS1005 DS1005-100 DS1005-125 DS1005-60 DS1005-75 DS1005M
74LS

Abstract: DS1005 DS1005-100 DS1005-125 DS1005-60 DS1005-75 DS1005M DS1005S
Text: over hybridtechnology is achieved bythecombi-nation of a 100 % silicon delay line and industry standard , ns DS1005-75 15 ns 30 ns 45 ns 60 ns 75 ns DS1005- 100 20 ns 40 ns 60 ns 80 ns 100 ns DS1005-125 25 ns 50 ns 75 ns 100 ns 125 ns DS1005-150 30 ns 60 ns 90 ns 120 ns 150 ns DS 1005-175 35 ns 70 ns 105 ns 140 ns 175 ns DS 1005-200 40 ns 80 ns 120 ns 160 ns 200 ns DS 1005-250 50 ns 100 ns 150 ns 200 , ns 3,4,5,6 Input to Tap Delay (trailing edge) tpHL Table 1 ns 3,4,5,6 Power-up Time tpu 100 ms


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PDF DS1005 14-pin 16-pin DS1005 74F04 74LS DS1005-100 DS1005-125 DS1005-60 DS1005-75 DS1005M DS1005S
Not Available

Abstract: No abstract text available
Text: technology is achieved by the combination of a 100 % silicon delay line and industry standard DIP and SOIC , -75 DS1005- 100 DS1005-125 DS1005-150 DS1005-175 DS1005-200 DS1005-250 Custom delays available t p L H , 60 ns 70 ns 80 ns 100 ns TAP 3 36 ns 45 ns 60 ns 75 ns 90 ns 105 ns 120 ns 150 ns TAP 4 48 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns 200 ns TAP 5 60 ns 75 ns 100 ns 125 ns 150 ns 175 ns 200 , ) Power-up Time tPLH Table 1 Table 1 100 4 (twi) ns ns ms ns 3,4,5,6 3,4,5,6 tpHL tpu Period


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PDF DS1005 14-pin 16-pin DS1005 74F04 DS1005.
74LS

Abstract: DS1005 DS1005-60 DS1005G DS1005H DS1005K DS1005M DS1005S
Text: over hybrid technology is achieved by the combination of a 100 % silicon delay line and industry , -60 12 ns 24 ns 36 ns 48 ns 60 ns DS1005-75 15 ns 30 ns 45 ns 60 ns 75 ns DS1005- 100 20 ns 40 ns 60 ns 80 ns 100 ns DS1005-125 25 ns 50 ns 75 ns 100 ns 125 ns DS1005-150 30 ns 60 ns 90 ns 120 ns 150 ns , ns 100 ns 150 ns 200 ns 250 ns Custom delays available ■2t.mi30 001001b flS2 ■_ 030194 2/5 , ) tpHL Table 1 ns 3,4,5,6 Power-up Time tpu 100 ms Period 4 (twi) ns 7 CAPACITANCE TA = 25Â


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PDF DS1005 14-pin 16-pin DS1005 74F04 2bmi30 2bl413G 74LS DS1005-60 DS1005G DS1005H DS1005K DS1005M DS1005S
Not Available

Abstract: No abstract text available
Text: performance and superior re liability over hybrid technology is achieved by the com bi nation of a 100 , . D S 1005-60 DS1005-75 DS1005- 100 DS1005-125 DS1005-150 DS1005-175 DS 1005-200 DS1005-250 Custom , ns 60 ns 70 ns 80 ns 100 ns TAP 3 36 ns 45 ns 60 ns 75 ns 90 ns 105 ns 120 ns 150 ns TAP 4 48 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns 200 ns TAP 5 60 ns 75 ns 100 ns 125 ns 150 ns 175 ns , 'PHL (PU Period 4 (twi) Table 1 100 ns ms ns 3,4,5,6 7 CAPACITANCE PARAMETER Input


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PDF DS1005 14-pin 16-pin 74F04 DS1005.
Not Available

Abstract: No abstract text available
Text: superior re­ liability over hybrid technology is achieved by the combi­ nation of a 100 % silicon delay , DS1005- 100 20 ns 40 ns 60 ns 80 ns 100 ns DS1005-125 25 ns 50 ns 75 ns 100 , DS1005-250 50 ns 100 ns 150 ns 200 ns 250 ns Custom delays available 022697 2/5 â , ) tpHL Table 1 Power-up Time 100 tpu Period ms ns 4 (twi) CAPACITANCE 7 TA =


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PDF DS1005 14-pin 16-pin DS1005 74F04 DS1005. 2bl4130
Not Available

Abstract: No abstract text available
Text: hybrid technology is achieved by the com bi nation of a 100 % silicon delay line and industry standard DIP , DELAY TABLE (tPHL, tPLH) Table 1 PART NO. DS1005-60 DS1005-75 DS1005- 100 DS1005-125 DS1005-150 DS1005 , TAP 2 24 ns 30 ns 40 ns 50 ns 60 ns 70 ns 80 ns 100 ns TAP 3 36 ns 45 ns 60 ns 75 ns 90 ns 105 ns 120 ns 150 ns TAP 4 48 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns 200 ns TAP 5 60 ns 75 ns 100 , tpu Period Table 1 100 ns ms ns 3,4,5,6 4 (twi) 7 CAPACITANCE PARAMETER Input


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PDF DS1005 14-pin 16-pin 74F04 S1005.
74F04

Abstract: 74LS DS1005 DS1005-150 DS1005-60 DS1005-75 DS1005M DS1005S
Text: performance and superior reliability over hybrid technology is achieved by the combination of a 100 % silicon , 60 ns 80 ns 100 ns DS 1005-125 25 ns 50 ns 75 ns 100 ns 125 ns DS1005-150 30 ns 60 ns 90 ns 120 ns , 1005-250 50 ns 100 ns 150 ns 200 ns 250 ns Custom delays available 2 of 6 DS1005 ABSOLUTE MAXIMUM , Delay (trailing edge) tpHL Table 1 ns 3,4,5,6 Power-up Time tpu 100 ms Period 4(twi) ns 7


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PDF DS1005 14-pin 16-pin 74F04 74LS DS1005 DS1005-150 DS1005-60 DS1005-75 DS1005M DS1005S
Not Available

Abstract: No abstract text available
Text: combination of a 100 % silicon delay line and industry standard DIP and SOIC packaging. In order to , DS1005- 100 20 ns 40 ns 60 ns 80ns 100 ns DS1005-125 25ns 50 ns 75ns 100ns , Tap Delay (trailing edge) tpHL Table 1 ns 3,4,5,6 Power-up Time 100 l PU


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PDF DS1005 74F04 DS1005.
DS1237S

Abstract: DS1625 DS1621 DS1259 DS1215 DS1212 DS1211 DS1000M DS1000 DS1640
Text: DALLAS DS1259 semiconductor Battery Manager Chip FEATURES • Facilitates uninterruptible power • Uses battery only when primary Vqc ¡s not available • Low forward voltage drop • Powerfail signal interrupts processororwrite protects memory • Consumes less than 100 nA of battery , Battery Leakage 'bat 100 nA 8 Pin 5 Battery Output Current 'batout 100 HA CAPACITANCE (TA = 25 , 100 US 9 POWER-DOWN/POWER-UP CONDITION NOTES: 1. All voltages are referenced to ground. 2. Load


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PDF DS1259 DS1212 16-pin 2bl413G 0G1442Q DS1237S DS1625 DS1621 DS1259 DS1215 DS1211 DS1000M DS1000 DS1640
Not Available

Abstract: No abstract text available
Text: technology is achieved by the combination of a 100 % silicon delay line and industry standard DIP and SOIC , 45ns 60ns 75ns DS1005- 100 20ns 40ns 60ns 80ns 100ns DS1005-125, 25ns , ) ns 3, 4,5,6 100 l PU Period 7 ms ns 4 (twl) CAPACITANCE (t. =25°C


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PDF DS1005 DS1005M DS100SH DS100514-Pla 74F04.
1995 - 6V-0-6V

Abstract: precision waveform generator DS1005M DS1005-75 DS1005-60 DS1005-125 DS1005-100 DS1005 74LS hy 214
Text: combination of a 100 % silicon delay line and industry standard DIP and SOIC packaging. In order to maintain , 75 ns DS1005- 100 20 ns 40 ns 60 ns 80 ns 100 ns DS1005-125 25 ns 50 ns 75 ns 100 ns 125 ns DS1005-150 30 ns 60 ns 90 ns 120 ns 150 ns DS1005 , 200 ns DS1005-250 50 ns 100 ns 150 ns 200 ns 250 ns Custom delays available , ns 7 Table 1 ns 3,4,5,6 Table 1 TYP MAX ns 3,4,5,6 100 Period 4


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PDF DS1005 14-pin 16-pin DS1005S DS1005. 6V-0-6V precision waveform generator DS1005M DS1005-75 DS1005-60 DS1005-125 DS1005-100 DS1005 74LS hy 214
ds1666-010

Abstract: DS-1000 DS1221S DS2107AS ds1010s DS1267 ordering DS1867 ordering information DS1228S DS1640
Text: 122Q DS1666-50 50K£2 DS1666-100100K£2 243ÌÌ 152 Q 1.1 MHz 759Q. 200 KHz 1.519KÎÎ 100 KHz , 100 ns INC High to U/D Change t|D 100 ns U/D to INC Setup tDI 1 US INC Low Period t|L 500 ns INC High Period tlH 1 US INC Inactive to CS Inactive tic 500 ns CS Deselect Time tcPH 100 , and not 100 % tested. 3. Typical values are for tA = 25°C and nominal supply voltages. 4. Wiper output , +85°C 10K£i DS1666-050 14L DIP -40°C TO +85°C 50K£i DS1666- 100 14L DIP -40°C TO +85°C 100KÂ


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PDF DS1666, DS1666S 14-pin 16-pin DS1666-10 DS1666-50 DS1666-100100KÂ DS1666 ds1666-010 DS-1000 DS1221S DS2107AS ds1010s DS1267 ordering DS1867 ordering information DS1228S DS1640
use of zenner diode in 3 pin regulator circuits

Abstract: DS1640 DS1231S DS1231 DS1215 DS1211 DS1000M DS1000 opto isolator IC DS2011D
Text: ZENNER VOLTAGE EXAMPLE: CTR = 0.2 IC = 30 nA IF = 150nA VOLTAGE SENSE POINT = 105 AND VZ = 100 VOLTS THEN 105 = 100 + x R1 R1 = 33K NOTE: RST requires a pull-up resister. AC VOLTAGE MONITOR WITH , NMi Delay t|pd 1.1 US Vcc Slew Rate 4.75-4.25V tF 300 US VCc Detect to RST and RST Irpd 100


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PDF DS1231/S 16-pin DS1231 2bl413G 0G1442Q use of zenner diode in 3 pin regulator circuits DS1640 DS1231S DS1215 DS1211 DS1000M DS1000 opto isolator IC DS2011D
2BL4

Abstract: DS2011D DS1000M DS1621 DS1234S DS1234 DS1215 DS1211 DS1000 DS1640
Text: DS1234 DALLAS SEMICONDUCTOR DS1234 Conditional Nonvolatile Controller Chip FEATURES • Converts CMOS static RAMs into nonvolatile memories • Software-controlled write inhibit • Software-controlled battery disconnect extends battery life • Unconditionally write protects when Vqc ¡s 0LJt of tolerance • Consumes less than 100 nA of battery current • Powerfail signal can be usedto interrupt , Backup Current @ Vcco = Vbat-0.3V 'ccoi 100 HA 5 021798 4/7 This Material Copyrighted By Its


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PDF DS1234 16-pin 2bl413G 0G1442Q 2BL4 DS2011D DS1000M DS1621 DS1234S DS1234 DS1215 DS1211 DS1000 DS1640
2007 - Not Available

Abstract: No abstract text available
Text: combination of a 100 % silicon delay line and industry standard DIP and SOIC packaging. In order to maintain , DS1005- 100 20 ns DS1005-125 25 ns DS1005-150 30 ns DS1005-175 35 ns DS1005-200 40 ns DS1005-250 50 ns Custom delays available TAP 2 24 ns 30 ns 40 ns 50 ns 60 ns 70 ns 80 ns 100 ns TAP 3 36 ns 45 ns 60 ns 75 ns 90 ns 105 ns 120 ns 150 ns TAP 4 48 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns 200 ns TAP 5 60 ns 75 ns 100 ns 125 ns 150 ns 175 ns 200 ns 250 ns 2 of 6 DS1005 ABSOLUTE MAXIMUM RATINGS


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PDF DS1005 14-pin 16-pin 56-G2008-001C DS1004Z-3 DS1004Z-4 DS1004Z-5 DS1004Z-5+ DS1004Z-3+ DS1004Z-4+
ds1236s

Abstract: battery 038 DS1640
Text: s e m ic o n d u c to r DALLAS DS1259 Battery Manager Chip FEATURES · Facilitates uninterruptible power · Uses battery only when primary Vqc ¡s n°t available · Low forward voltage drop · Powerfail signal interrupts processororwrite protects memory · Consumes less than 100 nA of battery current · Low , 10 250 mA mA mA V 2.6 MAX 15 100 100 V UNITS mA nA HA 4,6 7 NOTES 5 8 1,2 1,2 3 NOTES VBATF SYMBOL , SYMBOL tF MIN 300 1 0 TYP (0°C to 70°C; VCC = 4.0 to 5.5V) MAX UNITS US US US 100 US 9 NOTES POW


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PDF DS1259 DS1212 16-pin 001442Q ds1236s battery 038 DS1640
DS1640

Abstract: No abstract text available
Text: 50K£2 759Q 200 KHz 12 2Q DS16 6 6 -1 0 0 1 00K£2 2 4 3 ÌÌ 1 .5 19 K ÎÎ 100 KHz 1 6 -P IN S , tei 100 ns IN C High to U/D Change t|D 100 ns U/D to IN C Setup I di 1 , Inactive tic 500 ns tcPH 100 NOTES ns CS Deselect Time AC TIMING Figure 4 , 100 % tested. 3. Typical values are for tA = 25°C and nominal supply voltages. 4. W iper output open , 16L SO IC (300 MIL) -4 0 °C TO +85°C 50K£i D S1666S - 100 16L SO IC (300 MIL) -4 0


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PDF DS1666, DS1666S Poi73 001442Q DS1360S DS1380S DS1609S DS1610S DS1640
DS1209

Abstract: Zener diode 0740 DS1640
Text: VZ = ZENNER VOLTAGE EXAMPLE: CTR = 0.2 IC = 30 nA IF = 150nA VOLTAGE SENSE POINT = 105 AND VZ = 100 VOLTS THEN 105 = 100 + x R1 R1 = 33K NOTE: RST requires a pull—up resister. AC VOLTAGE MONITOR WITH , Rate 4.75-4.25V tF 300 US VCc Detect to RST and RST Irpd 100 ns VCc Detect to NMÌ t|pu 200 US


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PDF DS1231/S 16-pin DS1231 2bl413G 0G1442Q DS1209 Zener diode 0740 DS1640
DS1640

Abstract: No abstract text available
Text: DALLAS SEMICONDUCTOR DS1234 Conditional Nonvolatile C ontroller Chip FEATURES PIN ASSIGNMENT • Converts CMOS static mem ories RAMs into nonvolatile • Software-controlled write inhibit • Software-controlled battery life battery disconnect extends • U nconditionally write protects when V qc ¡s 0LJt of tolerance • Consum es less than 100 nA of battery current , BAT -°-2 6 !b a t 0.1 HA 7 !c c o i 100 HA 5 = ^ BAT " ° - 3^ r


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PDF DS1234 14-Pin 1234S 16-Pin 001442Q DS1360S DS1380S DS1609S DS1610S DS1640
ebl41

Abstract: DS1228S DS1867 ordering information DS1669 Digital Pot IC DS1640
Text: resistance: DS18 0 6 -0 1 0 ; 1 MHz; DS18 0 6 -0 5 0 ; 200 KHz, DS18 0 6 -1 0 0 ; 100 KHz. 5. See Figure 4. 6 , DS18 0 6 -0 1 0 DS18 0 6 -0 5 0 DS18 0 6 -1 0 0 D S1806E -010 D S1806E -050 D S1806E - 100 D S1806S -010 D S1806S -050 D S1806S - 100 PACKAGE 20L DIP 20L DIP 20L DIP 2 0 L T S S O P (173 MIL) 2 0 L T S S O


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PDF DS1806 1806S 001442Q -20-PIN 14-PIN DS1801 DS1803 DS1807 20-PIN DS1033E ebl41 DS1228S DS1867 ordering information DS1669 Digital Pot IC DS1640
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