The Datasheet Archive

DS1004Z-4+T datasheet (4)

Part ECAD Model Manufacturer Description Type PDF
DS1004Z-4+T DS1004Z-4+T ECAD Model Maxim Integrated Products 5-Tap High-Speed Silicon Delay Line. Lead-free Original PDF
DS1004Z-4_T&R DS1004Z-4_T&R ECAD Model Dallas Semiconductor 5-Tap High-Speed Silicon Delay Line Original PDF
DS1004Z-4/T&R DS1004Z-4/T&R ECAD Model Maxim Integrated Products Delay Line, Active Tapped, 5 Tap, 21nSec Delay, 5V Supply Voltage, 8-SOIC, Tape And Reel Original PDF
DS1004Z-4/T&R/503 DS1004Z-4/T&R/503 ECAD Model Maxim Integrated Products 5-Tap High-Speed Silicon Delay Line Original PDF

DS1004Z-4+T Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
DS1004

Abstract: DS1004Z-3 DS1004Z-2 DS1004Z DS1004M-5 DS1004M-4 DS1004M-3 DS1004M-2 DS1004M DS1004Z-4
Text: TAP 4 TAP 5 INPUT - t >" A A A A A DELAY—*-DELAY —•-DELAY —•-DELAY —•—DELAY -' 2 of , Q 1 w 8 ] Vcc TAP 2 Q 2 7 ]] TAP 1 TAP 4 Q 3 6 ]] TAP 3 GND Q 4 5 ]] TAP 5 DS1004M 8-Pin DIP (300-mil) See Mech. Drawings Section IN Q 1 8 ] Vcc TAP 2 Q 2 7 ]] TAP 1 TAP 4 Q 3 6 ]] TAP 3 GND Q 4 5 ]] TAP 5 DS1004Z 8-Pin SOIC (150-mil) See Mech. Drawings Section PIN DESCRIPTION TAP 1-5 , -tap all silicon delay line which can provide 2, 3, 4 , or 5 ns tap-to-tap delays within a standard part


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PDF DS1004 DS1004M 300-mil) DS1004Z DS1004Z-3 DS1004Z-2 DS1004M-5 DS1004M-4 DS1004M-3 DS1004M-2 DS1004Z-4
2007 - Not Available

Abstract: No abstract text available
Text: within one business day. 4 . Part number suffixes: T or T&R = tape and reel; + = RoHS/lead-free; # = RoHS , phase, IR and wave solderable Available in Tape and Reel PIN ASSIGNMENT IN TAP 2 TAP 4 GND 1 2 3 4 8 , 4 GND 1 2 3 4 8 7 6 5 VCC TAP 1 TAP 3 TAP 5 DS1004Z 8-Pin SOIC (150-mil) See Mech. Drawings , DESCRIPTION The DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4 , or 5 ns tap-to-tap delays , delay of 5 ns. Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4 , or 5 ns. See Table 1


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PDF DS1004 DS1004M 300-mil) DS1004Z 150-mil) 56-G2008-001C DS1004Z-3 DS1004Z-4 DS1004Z-5 DS1004Z-5+
2007 - Not Available

Abstract: No abstract text available
Text: parts, usually within one business day. 4 . Part number suffixes: T or T&R = tape and reel; + = RoHS , range available IN NC NC TAP 2 NC TAP 4 GND PIN ASSIGNMENT 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC NC TAP 1 NC TAP 3 NC TAP 5 IN NC NC TAP 2 NC TAP 4 NC GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC NC , -Pin SOIC (300-mil) See Mech. Drawings Section 8 7 6 5 VCC TAP 1 TAP 3 TAP 5 IN TAP 2 TAP 4 GND 1 2 3 4 DS1005M 8-Pin DIP (300-mil) See Mech. Drawings Section PIN DESCRIPTION TAP 1-TAP 5 VCC GND


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PDF DS1005 14-pin 16-pin 56-G2008-001C DS1004Z-3 DS1004Z-4 DS1004Z-5 DS1004Z-5+ DS1004Z-3+ DS1004Z-4+
Not Available

Abstract: No abstract text available
Text: Silicon Delay Line PIN ASSIGNMENT IN L 1 2 3 4 8 Vcc · Five equally delayed clock phases per input , -pin SOIC · Vapor phase, IR and wave solderable · Available in Tape and Reel TAP 2 C TAP 4 C GND C 7 , TAP 4 C 3 GND C 4 8 H v cc 7 TAP 1 6 TAP 3 5 TAP 5 DS1004Z 8-PIN SOIC (150 MIL) See , , 3, 4 , or 5 ns tap-to-tap delays within a stan dard part family. The device is Dallas Semiconductor , , 3, 4 , or 5 ns. See Table 1 for details. Tolerance over temperature and voltage is ±1.5 ns. Nominal


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PDF DS1004 DS1004M
Not Available

Abstract: No abstract text available
Text: ±1 ns 1 TA P2Ë • Five equally delayed clock phases per input 4 5 H TAP 5 DS1004M 8 , of ±1.5 ns over temperature and voltage IN TAP 2 TAP 4 GND • Leading and trailing edge precision preserves the input symmetry • CMOS design with TTL compatibility t C : C 8 3 Vcc 7 , Input DESCRIPTION The DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4 , or 5 ns , delayed by 2 ,3 , 4 , or 5 ns. See Table 1 for details. Tolerance over temperature and voltage is Â


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PDF S1004 DS1004 DS1004M 0Dlb23fi
DS1004

Abstract: DS1004Z-3 DS1004Z-2 DS1004Z DS1004M-5 DS1004M-4 DS1004M-3 DS1004M-2 DS1004M DS1004Z-4
Text: ) See Mech. Drawings Section IN C TAP 2 C TAP 4 C GND L 1 8 2 7 3 6 4_5 n Vcc 3 TAP 1 3 TAP 3 3 , delay line which can provide 2, 3, 4 , or 5 ns tap-to-tap delays within a standard part family. The device , (taps 2 through 5) are precisely delayed by 2,3, 4 , or 5 ns. See Table 1 for details. Tolerance over , ± 1.5 ns ±1.5 ns 3 ns ±0.75 ns ±0.75 ns DS1004M- 4 5 ± 1.5 ns ±1.5 ns 4 ns ±1.0 ns ±0.75 ns , ±0.75 ns DS1004Z-3 5± 1.5 ns ±1.5 ns 3 ns +0.75 ns ±0.75 ns DS1004Z- 4 5 ± 1.5 ns ±1.5 ns 4 ns Â


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PDF DS1004 DS1004M DS1004Z 2fal4130 DS1004 DS1004Z-3 DS1004Z-2 DS1004M-5 DS1004M-4 DS1004M-3 DS1004M-2 DS1004Z-4
2000 - DS1004

Abstract: DS1004Z-3 DS1004Z-2 DS1004Z DS1004M-5 DS1004M-4 DS1004M-3 DS1004M-2 DS1004M DS1004Z-4
Text: 8 VCC TAP 2 2 7 TAP 1 TAP 4 3 6 TAP 3 GND 4 5 TAP 5 , TAP 4 3 6 TAP 3 GND 4 5 TAP 5 DS1004Z 8-Pin SOIC (150-mil) See Mech. Drawings , DESCRIPTION The DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4 , or 5 ns tap-to-tap delays , input-to-tap 1 delay of 5 ns. Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4 , or 5 ns , ±1.75 ns DS1004M-2 DS1004M-3 DS1004M- 4 DS1004M-5 DS1004Z-2 DS1004Z-3 DS1004Z- 4 DS1004Z


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PDF DS1004 DS1004M 300-mil) DS1004 DS1004Z-3 DS1004Z-2 DS1004Z DS1004M-5 DS1004M-4 DS1004M-3 DS1004M-2 DS1004Z-4
1999 - DS1004Z-2

Abstract: DS1004M-5 DS1004M-4 DS1004M-3 DS1004M-2 DS1004M DS1004 DS1004Z-4 DS1004Z-3 DS1004Z
Text: and Reel IN 1 8 VCC TAP 2 2 7 TAP 1 TAP 4 3 6 TAP 3 GND 4 , 2 7 TAP 1 TAP 4 3 6 TAP 3 GND 4 5 TAP 5 DS1004Z 8-Pin SOIC (150 , 2, 3, 4 , or 5 ns tap-to-tap delays within a standard part family. The device is Dallas , precisely delayed by 2, 3, 4 , or 5 ns. See Table 1 for details. Tolerance over temperature and voltage is , DS1004M-2 DS1004M-3 DS1004M- 4 DS1004M-5 DS1004Z-2 DS1004Z-3 DS1004Z- 4 DS1004Z-5 TAP-TO-TAP


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PDF DS1004 DS1004M 300-mil) DS1004Z-2 DS1004M-5 DS1004M-4 DS1004M-3 DS1004M-2 DS1004 DS1004Z-4 DS1004Z-3 DS1004Z
2002 - DS1004

Abstract: No abstract text available
Text: phase, IR and wave solderable Available in Tape and Reel PIN ASSIGNMENT IN TAP 2 TAP 4 GND 1 2 3 4 8 , 4 GND 1 2 3 4 8 7 6 5 VCC TAP 1 TAP 3 TAP 5 DS1004Z 8-Pin SOIC (150-mil) See Mech. Drawings , DESCRIPTION The DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4 , or 5 ns tap-to-tap delays , delay of 5 ns. Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4 , or 5 ns. See Table 1 , -2 DS1004M-3 DS1004M- 4 DS1004M-5 DS1004Z-2 DS1004Z-3 DS1004Z- 4 DS1004Z-5 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5


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PDF DS1004 DS1004M 300-mil) DS1004Z 150-mil)
Not Available

Abstract: No abstract text available
Text: Delay Line PIN ASSIGNMENT IN C 1 2 3 4 8 D Vcc 7 H TAP 1 6 U TAP 3 5 H TAP 5 · Five equally , TAP 4 L GND C DS1004M 8-PIN DIP (300 MIL) See Mech Drawings Section IN C 1 TAP 2 C 2 TAP 4 C 3 GND C 4 8 ^ V CC 7 3 TAP 1 6 D TAP 3 5 D TAP 5 DS1004Z 8-PIN SOIC (150 MIL) See , Input DESCRIPTION The DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4 , or 5 ns , inputto-tap 1 delay of 5 ns. Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4 , or 5 ns. See


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PDF DS1004 DS1004M
1995 - 74F04

Abstract: DS1004 DS1004M DS1004Z
Text: 7 TAP 1 · Precise tap­to­tap delay tolerances of TAP 4 3 6 TAP 3 GND 4 5 , 4 GND · Leading and trailing edge precision preserves the input symmetry · CMOS design with TTL compatibility 1 2 3 4 8 7 6 5 VCC TAP 1 TAP 3 TAP 5 DS1004Z 8-PIN SOIC , ­tap all silicon delay line which can provide 2, 3, 4 , or 5 ns tap­to­tap delays within a standard part , . Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4 , or 5 ns. See Table 1 for details


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PDF DS1004 DS1004M DS1004Z 74F04 DS1004
DS1004

Abstract: DS1004Z-4 DS1004Z-3 DS1004Z-2 DS1004Z DS1004M-5 DS1004M-4 DS1004M-3 DS1004M-2 DS1004M
Text: and wave solderable • Available in Tape and Reel PIN ASSIGNMENT IN C TAP 2 C TAP 4 E GND C H , 4 C GND C 3 VCC □ TAP 1 3 TAP 3 H TAP 5 DS1004Z 8-PIN SOIC (150 MIL) See Mech. Drawings Section , DESCRIPTION The DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4 , or 5 ns tap-to-tap delays , - to-tap1 delay of5ns. Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4 , or 5 ns. See , ns ±0.75 ns ±0.75 ns DS1004M- 4 5± 1.5 ns ±1.5 ns 4 ns ±1.0 ns ±0.75 ns DS1004M-5 5± 1.5 ns Â


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PDF DS1004 DS1004M DS1004 DS1004Z-4 DS1004Z-3 DS1004Z-2 DS1004Z DS1004M-5 DS1004M-4 DS1004M-3 DS1004M-2
1998 - 74F04

Abstract: DS1004 DS1004M DS1004Z
Text: 7 TAP 1 · Precise tap­to­tap delay tolerances of TAP 4 3 6 TAP 3 GND 4 5 , 4 GND · Leading and trailing edge precision preserves the input symmetry · CMOS design with TTL compatibility 1 2 3 4 8 7 6 5 VCC TAP 1 TAP 3 TAP 5 DS1004Z 8-PIN SOIC , ­tap all silicon delay line which can provide 2, 3, 4 , or 5 ns tap­to­tap delays within a standard part , . Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4 , or 5 ns. See Table 1 for details


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PDF DS1004 DS1004M DS1004Z 74F04 DS1004
Not Available

Abstract: No abstract text available
Text: IN 1 8 VCC TAP 2 2 7 TAP 1 TAP 4 3 6 TAP 3 GND 4 5 TAP 5 , TAP 4 3 6 TAP 3 GND 4 5 TAP 5 DS1004Z 8-Pin SOIC (150-mil) See Mech. Drawings , DESCRIPTION The DS1004 is a 5-tap all silicon delay line which can provide 2, 3, 4 , or 5 ns tap-to-tap delays , input-to-tap 1 delay of 5 ns. Subsequent taps (taps 2 through 5) are precisely delayed by 2, 3, 4 , or 5 ns , ±1.5 ns ±1.75 ns ±1.75 ns DS1004M-2 DS1004M-3 DS1004M- 4 DS1004M-5 DS1004Z-2 DS1004Z-3 DS1004Z- 4


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PDF DS1004 DS1004M 300-mil)
DS1004Z-004

Abstract: No abstract text available
Text: Delay Line PIN ASSIGNMENT IN C DS1004 1 2 3 4 8 H Vcc 7 H TAP 1 6 H TAP 3 5 U TAP 5 · , Reel TAP 2 [ I TAP 4 C GND C DS1004M 8-PIN DIP (300 MIL) See Mech. Drawing Pg. 480 8 ^ V CC IN C 1 7 TAP 1 TAP 2 C 2 TAP 4 C 3 6 D TAP 3 GND C 4_5 H TAP 5 3 DS1004Z 8-PIN SOIC (150 MIL , provide 2,3, 4 , or 5 ns tap-to-tap delays within a stan dard part family. The device is Dallas , precisely delayed by 2,3, 4 , or 5 ns. See Table 1 for details. Tolerance over temperature and voltage is ±1.5


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PDF DS1004 DS1004M DS1004Z-004
2002 - DS1425L-F5

Abstract: ds1480s F5 sot223 DS1868 DS75U ds1642-150 DS1669SN-10 DS1640 DS1251W-120 ds1386-8-150
Text: DS1004Z-003 DS1004Z-3/T&R DS1004Z-004 DS1004Z- 4 /T&R DS1004Z-005 DS1004Z-5/T&R DS1005-xxx DS1005M-xxx , DS1040Z-D70 DS1044-xxx DS1044R-xxx DS1044R-xxx/T&R DS1045-2 DS1045-3 DS1045- 4 DS1045-5 DS1045S-2 DS1045S-3 DS1045S- 4 DS1045S- 4 /T&R DS1045S-5 DS1050M-1 DS1050M-10 DS1050M-5 DS1050Z-1 DS1050Z-10 DS1050Z-5 DS1065T , ns xxx = 5 to 25 ns xxx = 5 to 25 ns 2 ns Steps 3 ns Steps 4 ns Steps 5 ns Steps 2 ns Steps 3 ns Steps 4 ns Steps 4 ns Steps 5 ns Steps 1.000KHz 10.000KHz 5.000KHz 1.000KHz 10.000KHz 5.000KHz 50.000MHz


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PDF DS0621 DS1000 14-Pin 16-Pin DS1425L-F5 ds1480s F5 sot223 DS1868 DS75U ds1642-150 DS1669SN-10 DS1640 DS1251W-120 ds1386-8-150
1999 - DS-1100

Abstract: DS1220Y-150 equivalent DS1267S-100 DS1267S-010 DS1221SN DS5002FP-16 DS1217 DS1213 DS1021S-25 DS-149
Text: and industrial temperature ranges PIN ASSIGNMENT IN TAP 2 TAP 4 GND 1 2 3 4 8 7 6 5 VCC TAP 1 TAP , series delay lines have five equally spaced taps providing delays from 4 ns to 300 ns. These devices are , -25 -30 -35 -40 -45 -50 -60 -75 -100 -125 -150 -175 -200 -250 -300 TAP 1 4 5 6 7 8 9 10 12 15 20 25 30 , 24 27 30 36 45 60 75 90 105 120 150 180 TAP 4 16 20 24 28 32 36 40 48 60 80 100 120 140 160 200 240 , . VOH= 4 VCC=Min. VOL=0.5 12 TEST CONDITION (-40°C to +85°C; VCC = 5.0V ± 5%) MIN 4.75 2.2 -0.5 -1.0


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PDF DS1100 DS1000 DS1100M DS1100Z DS1100U DS1100 18-Channel 18-line DS-1100 DS1220Y-150 equivalent DS1267S-100 DS1267S-010 DS1221SN DS5002FP-16 DS1217 DS1213 DS1021S-25 DS-149
2007 - DS-1100

Abstract: ds1480 ds1386-32-120 ds1225y DS1640 DS1669 replacement DS1307Z DS1270Y-70IND DS1251W-120 ds1775r1 u
Text: IN3 GND 1 2 3 4 8 7 6 5 VCC OUT1 OUT2 OUT3 DS1135M 8-Pin DIP IN1 IN2 IN3 GND 1 2 3 4 8 7 6 5 VCC OUT1 OUT2 OUT3 DS1135Z 8-Pin SOIC (150-mil) IN1 IN2 IN3 GND 1 2 3 4 8 7 6 5 VCC OUT1 OUT2 OUT3 , are being produced at the output. CAPACITANCE PARAMETER Input Capacitance SYMBOL CIN MIN 4 of 6 , -3/T&R DS1004Z-004 DS1004Z- 4 /T&R DS1004Z-005 DS1004Z-5/T&R DS1005-xxx DS1005M-xxx DS1005S-xxx DS1005S-xxx , DS1044R-xxx DS1044R-xxx/T&R DS1045-2 DS1045-3 DS1045- 4 DS1045-5 DS1045S-2 DS1045S-3 DS1045S- 4 DS1045S- 4 /T&R


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PDF DS1135 150-mil) 118-mil) DS1135L) DS1013 DS1035 DS1135M DS1135Z DS1135LU-8 DS1135LU-12/T DS-1100 ds1480 ds1386-32-120 ds1225y DS1640 DS1669 replacement DS1307Z DS1270Y-70IND DS1251W-120 ds1775r1 u
2002 - DS-1100

Abstract: DS1501 ds1307 pic DS1425L-F5 ds1236s-5 DS80C320 PIC SOT23-5 VTP DS1640 ds1480 256K x 8 SRAM dip
Text: to +85°C Perfect for PIC microprocessor applications PIN ASSIGNMENT VCC VBAT NC VOUT 1 2 3 4 8 7 6 5 RST(*RST) NMI IN GND 8-Pin DIP (300mil) VCC VBAT NC VOUT 1 2 3 4 8 7 6 5 RST(*RST) NMI IN GND , : NON-MASKABLE INTERRUPT Figure 4 4 of 9 DS1836A/B/C/D OUTPUT VALID CONDITIONS The DS1836 can maintain , V V V V V mA V V V pF NOTES 1 2 3 3 4 5 6 7 1, 8 1, 9 1 1 1 1 1, 10 1, 10 11 1, 10 1, 10 1 8 of 9 , VBAT < 2.7V. 4 ) Measured with outputs open and both VCC and VBAT < 5.5V. 5) Measured with outputs open


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PDF DS1836/A/B/C/D 350ms DS9092K DS9092R DS9093A DS9092RG DS9093A DS9093AB DS-1100 DS1501 ds1307 pic DS1425L-F5 ds1236s-5 DS80C320 PIC SOT23-5 VTP DS1640 ds1480 256K x 8 SRAM dip
2007 - F5 sot223

Abstract: DS1225AB-85 DS1307Z T DS1270W DS1267SN-100 DS1267N DS1236-5 ds1233z DS1225Y DS1217
Text: on Website 2 4 3 TOP VIEW SOT-223 PACKAGE See Mech. Drawings Section on Website PIN DESCRIPTION PIN 1 PIN 2 PIN 3 PIN 4 GROUND RESET VCC GROUND (SOT-223 ONLY) DESCRIPTION The DS1233 , 2 2 of 5 DS1233 PUSHBUTTON RESET Figure 3 POWER UP Figure 4 POWER DOWN Figure 5 3 , ground. 4 of 5 DS1233 ECONORESET SELECTION GUIDE VCC TRIP POINT MIN DS1233-15 DS1233-10 DS1233 , -3/T&R DS1004Z-004 DS1004Z- 4 /T&R DS1004Z-005 DS1004Z-5/T&R DS1005-xxx DS1005M-xxx DS1005S-xxx DS1005S-xxx


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PDF DS1233 350ms OT-223 DS1233-15 DS1233-5/T DS1233-15 DS1233-5+ DS1233-5 2000/Reel F5 sot223 DS1225AB-85 DS1307Z T DS1270W DS1267SN-100 DS1267N DS1236-5 ds1233z DS1225Y DS1217
2002 - DS1425L-F5

Abstract: TSOC 6 socket F5 sot223 DS-1100 DS1267SN-100 DS1314DS DS1640 DS1023S-25 DS1238S5 DS1667S-010
Text: on Website 2 4 3 TOP VIEW SOT-223 PACKAGE See Mech. Drawings Section on Website PIN DESCRIPTION PIN 1 PIN 2 PIN 3 PIN 4 GROUND RESET VCC GROUND (SOT-223 ONLY) DESCRIPTION The DS1233 , 2 2 of 5 DS1233 PUSHBUTTON RESET Figure 3 POWER UP Figure 4 POWER DOWN Figure 5 3 , ground. 4 of 5 DS1233 ECONORESET SELECTION GUIDE VCC TRIP POINT MIN DS1233-15 DS1233-10 DS1233 , -3/T&R DS1004Z-004 DS1004Z- 4 /T&R DS1004Z-005 DS1004Z-5/T&R DS1005-xxx DS1005M-xxx DS1005S-xxx DS1005S-xxx


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PDF DS1233 350ms OT-223 DS9092K DS9092R DS9093A DS9092RG DS1425L-F5 TSOC 6 socket F5 sot223 DS-1100 DS1267SN-100 DS1314DS DS1640 DS1023S-25 DS1238S5 DS1667S-010
2002 - F5 sot223

Abstract: DS18S20Z TSOC 6 socket ds1480 DS1321 DS1640 DS1667S-010 DS2404S-001 DS2404S001 dallas ds1213c
Text: on Website 2 4 3 TOP VIEW SOT-223 PACKAGE See Mech. Drawings Section on Website PIN DESCRIPTION PIN 1 PIN 2 PIN 3 PIN 4 GROUND RESET VCC GROUND (SOT-223 ONLY) DESCRIPTION The DS1233A , 2 2 of 5 DS1233A PUSHBUTTON RESET Figure 3 POWER-UP Figure 4 POWER-DOWN Figure 5 , referenced to ground. 2) With a 100pF to 0.01mF capacitor connected from RST to ground. 4 of 5 DS1233A , -003 DS1004M-004 DS1004M-005 DS1004Z-002 DS10004Z-2/T&R DS1004Z-003 DS1004Z-3/T&R DS1004Z-004 DS1004Z- 4 /T&R


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PDF DS1233A 350ms OT-223 DS9092K DS9092R DS9093A DS9092RG F5 sot223 DS18S20Z TSOC 6 socket ds1480 DS1321 DS1640 DS1667S-010 DS2404S-001 DS2404S001 dallas ds1213c
ds1480

Abstract: DS1480S DS1425L-F5 DS1867E-010 DS1225Y-200 F5 sot223 DS1775 DS18120-10 DB9 DS1033 DS1267S-100
Text: 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 DS1004M-2 DS1004M-3 DS1004M- 4 DS1004M-5 DS1004Z-2 DS10004Z-2/T&R DS1004Z-3 DS1004Z-3/T&R DS1004Z- 4 DS1004Z- 4 /T&R DS1004Z , DS1045-3 DS1045- 4 DS1045-5 DS1045S-3 DS1045S- 4 DS1045S- 4 /T&R DS1045S-5 3 ns Steps 4 ns Steps 5 ns Steps 3 ns Steps 4 ns Steps 4ns Steps 5 ns Steps DS1050M 8-pin DIP 8-pin DIP 8-pin DIP , Density 4 Megabit Density 512K Bit Density 8 Pin DIP 300mil 8 Pin SO 150mil 0C to +70C 0C to


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PDF DS0621-SDK 14-Pin 16-Pin DS1000-xxx DS1000M-xxx DS1000S-xxx DS1000S-xxx/T DS1000Z-xxx DS1000Z-xxx/T ds1480 DS1480S DS1425L-F5 DS1867E-010 DS1225Y-200 F5 sot223 DS1775 DS18120-10 DB9 DS1033 DS1267S-100
ic DS2430

Abstract: ds1205v DS1640
Text: DS1632S DS1640S DS1653S DS1666S DS1667 DS1867 DS1868 DS2404S-C01 t i jLJ U U L J f t J U U - 4 1 1 , H A N IC A L D R A W IN G S 2 4 - TO 40-PIN DIP (600 MIL) .1- i - i i- i i- i. Includes: DS1212 DS1609 DS2009 DS2010 DS2011 DS2012 DS2013 e T U l K^ l PKG DIM A IN . MM B IN . MM C IN . , 0.145 3.68 0.110 2.79 0.675 17.15 0.012 0.30 0.022 0.56 4 - i 40-PIN MIN 2.050 52.07 0.530 13.46 , .030 .76 8° 060794 4 /23 337 M E C H A N IC A L D R A W IN G S 16-, 20-, AND 24-PIN SOIC


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PDF 28-PIN DS1000 DS1000M DS1003 DS1003M DS1004M DS1005 DS1005M DS1007 DS1010 ic DS2430 ds1205v DS1640
cen 496

Abstract: DS1868 DS1000H DS1205V DS1640
Text: -PIN MIN 0.740 18.80 0.240 6.10 0.120 3.05 0.300 7.62 0.015 0.38 0.120 3.0 4 0.090 2.29 0.320 8.13 0.008 , 9.40 0.012 0.30 0.022 0.56 060794 2/23 481 M E C H A N IC A L D R A W IN G S 2 4 - TO 40-PIN DIP (600 MIL) Includes: DS1212 DS1609 DS2009 DS2010 DS2011 DS2012 DS2013 jL E T C L PKG DIM , ° 0.318 8.07 0.010 0.25 0.020 0.51 .030 .76 8° 060794 4 /23 483 M E C H A N IC A L D R A W IN G S , DS1267S DS1336S DS1609S DS1632S DS1640S DS1653S DS1666S DS1667 DS1867 DS1868 DS2404S-C01 T B H D


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PDF 28-PIN DS1000 DS1000M DS1003 DS1003M DS1004M DS1005 DS1005M DS1007 DS1010 cen 496 DS1868 DS1000H DS1205V DS1640
Supplyframe Tracking Pixel