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DS1000-100 datasheet (1)

Part Manufacturer Description Type PDF
DS1000-100 Dallas Semiconductor 5-Tap Silicon Delay Line Original PDF

DS1000-100 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
DS1000-25

Abstract: 2U27 DS1000 DS1000-250 DS1000Z DS1000S DS1000M DS1000K DS1000H DS1000-100
Text: ns 48 ns 60 ns DS1000-75 15 ns 30 ns 45 ns 60 ns 75 ns DS1000-100 20 ns 40 ns 60 ns 80 ns 100 ns DS1000-125 25 ns 50 ns 75 ns 100 ns 125 ns DS1000-150 30 ns 60 ns 90 ns 120 ns 150 ns DS1000-175 35 ns 70 ns 105 ns 140 ns 175 ns DS1000-200 40 ns 80 ns 120 ns 160 ns 200 ns DS1000-250 50 ns 100 ns 150 , technology is achieved by the combination of a 100 % silicon delay line and industry standard DIP and SOIC , 450 ns DS1000-500 100 ns 200 ns 300 ns 400 ns 500 ns Custom delays available. _ Ebl4130 0Q0111A 343


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PDF DS1000 74F04 2bl413D DS1000-25 2U27 DS1000 DS1000-250 DS1000Z DS1000S DS1000M DS1000K DS1000H DS1000-100
Not Available

Abstract: No abstract text available
Text: 75 ns DS1000-100 20 ns 40 ns 60 ns 80 ns 100 ns DS1000-125 25 ns 50 ns 75 ns 100 ns 125 ns DS1000-150 30 ns 60 ns 90 ns 120 ns 150 ns DS1000 , over hybrid technology is achieved by the combination of a 100 % silicon delay line and industry , 200 ns 200 ns 250 ns DS1000-250 50 ns 100 ns 150 ns DS1000-350 70 ns 140 ns , 1000-500 100 ns 200 ns 300 ns 400 ns 500 ns Custom delays available. _ 2 b l 4 1 3


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PDF DS1000 DS1000S 16-PIN DS1000 14-PIN DS1000G DS1000K 2bl4130
DS1000-350

Abstract: DS1000H DS1000-50 DS1000
Text: -45 DS1000-50 DS1000-60 DS1000-75 DS1000-100 DS1000-125 DS1000-150 DS1000-175 DS1000-200 DS1000-250 DS1000 , achieved by the combination of a 100 % silicon delay line and industry standard DIP and SOIC packaging. In , 20 ns 25 ns 30 ns 35 ns 40 ns 50 ns 70 ns 90 ns 100 ns ( tP H L > îr l h ) Table 1 TAP 3 12 ns , 300 ns TAP 4 16 ns 20 ns 24 ns 28 ns 32 ns 36 ns 40 ns 48 ns 60 ns 80 ns 100 ns 120 ns 140 ns 160 ns 200 ns 280 ns 360 ns 400 ns TAP 5 20 ns 25 ns 30 ns 35 ns 40 ns 45 ns 50 ns 60 ns 75 ns 100 ns 125 ns


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PDF DS1000 74F04 DS1000-350 DS1000H DS1000-50 DS1000
Not Available

Abstract: No abstract text available
Text: DS1000-100 20 ns 40 ns 60 ns 80 ns 100 ns DS1000-125 25 ns 50 ns 75 ns 100 , over hybrid technology is achieved by the combination of a 100 % silicon delay line and industry , 150 ns 200 ns 250 ns PART NO. D S1000-250 50 ns 100 ns DS1000-350 70 ns 140 , S1000-500 100 ns 200 ns 300 ns 400 ns 500 ns Custom delays available. ’ Consult , tpu SYM BO L MIN N O TES 7 ns 3 ,4 , 5, 6, 9 ns 4(tw i) u n ft s ns 100


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PDF DS1000 DS1000S 16-PIN 74F04 500ns r-500)
DS1000S-25

Abstract: DS1000H DS1000S-125 DS1000M-100 DS1000S-50 ds1000s-60 DS1000S75 DS1000S100 DS1000M125 DS1000K-100
Text: -75 75 14-PIN DIP DS1100M-75 75 8-PIN DIP Functional DS1000-100 100 14-PIN DIP DS1100M- 100 100 8-PIN DIP Functional DS1000-100 IND 100 14-PIN DIP DS1100M- 100 * 100 8-PIN DIP Functional , -75 75 8-PIN DIP DIRECT DS1000M- 100 100 8-PIN DIP DS1100M- 100 100 8-PIN DIP DIRECT DS1000M- 100 IND 100 8-PIN DIP DS1100M- 100 * 100 8-PIN DIP DIRECT DS1000M-125 125 8-PIN DIP DS1100M , -PIN SOIC DIRECT DS1000Z-75 75 8-PIN SOIC DS1100Z-75 75 8-PIN SOIC DIRECT DS1000Z- 100 100 8-PIN SOIC


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PDF A002701 DS1000 DS1100 DS1000. DS1100 DS1000S-25 DS1000H DS1000S-125 DS1000M-100 DS1000S-50 ds1000s-60 DS1000S75 DS1000S100 DS1000M125 DS1000K-100
1999 - 74F04

Abstract: 74LS DS1000 DS1000-IND DS1000M DS1000Z
Text: over hybrid technology is achieved by the combination of a 100 % silicon delay line and industry , - Nom -20 -25 -30 -35 -40 -45 -50 -60 -75 - 100 -125 -150 -175 -200 -250 -500 4 5 6 7 8 9 10 12 15 20 25 30 35 40 50 100 TAP 1 TOLERANCE Init Temp 2 1 2 1 2 , 10 12 14 16 18 20 24 30 40 50 60 70 80 100 200 TAP 2 TOLERANCE Init Temp 2 1 2 , 60 80 100 120 140 160 200 400 Nom 20 25 30 35 40 45 50 60 75 100 125 150 175


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PDF DS1000 DS1000-IND) DS1000M 300-mil) 74F04 74LS DS1000 DS1000-IND DS1000Z
Not Available

Abstract: No abstract text available
Text: over hybrid technology is achieved by the combination of a 100 % silicon delay line and industry , - 100 20 2 1 40 2 1.2 60 3 1.8 80 4 2.4 100 5 3 -1 25 25 2 1 50 2.5 1.5 75 3.8 2.3 100 5 3 125 6.3 3.8 -1 5 0 , 50 2.5 1.5 100 5 3 150 7.5 4.5 200 10 6 250 12.5 7.5 -5 0 0 100 5 3 200 10 6 300 15 9 400 20 12 500 25 15


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PDF DS1000 DS1000-IND) DS1000M DS1000 74F04
1998 - 74F04

Abstract: 74LS DS1000 DS1000M DS1000Z
Text: combination of a 100 % silicon delay line and industry standard DIP and SOIC packaging. In order to maintain , 2 1 ­50 10 2 ­60 12 ­75 15 ­ 100 TAP 5 TOLERANCE Nom Init , 75 3.8 2.3 40 2 1.2 60 3 1.8 80 4 2.4 100 5 3 1 50 2.5 1.5 1 60 3 1.8 75 3.8 2.3 100 5 3 125 6.3 3.8 90 , 3.2 140 7 4.2 175 8.8 5.3 40 2 1.2 80 50 2.5 1.5 100 4


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PDF DS1000 DS1000 14-PIN 74F04 74F04 74LS DS1000M DS1000Z
Not Available

Abstract: No abstract text available
Text: reliability over hybrid technology is achieved by the com bination of a 100 % silicon delay line and industry , 50 60 70 80 100 200 2 2 2 2 2 2 2 2 2 2 2 .5 3 3,5 4 5 10 TAP 3 TOLERANCE Nom Init 12 15 18 21 24 , 1.2 15 1.8 2.4 3 3.6 4 .2 4 .8 6 12 TAP 5 TOLERANCE Init 20 25 30 35 40 45 50 60 75 100 125 150 , 25 30 35 40 50 100 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 .5 5 Temp Temp 1 1 1 1 1 1 1 1 1 1.2 1.5 1.8 , 60 80 100 120 140 160 200 400 2.1 2.4 3 6 NOTES: 1. Initial tolerances are i with respect to


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PDF S1000 DS1000 S1000-IN DS1000 14-PIN 74F04
74F04

Abstract: 74LS D012 DS1000 DS1000-IND DS1000M DS1000Z
Text: technology is achieved by the combination of a 100 % silicon delay line and industry standard DIP and SOIC , 1 30 2 1 45 2.3 1.4 60 3 1.8 75 3.8 2.3 - 100 20 2 1 40 2 1.2 60 3 1.8 80 4 2.4 100 5 3 -125 25 2 1 50 2.5 1.5 75 3.8 2.3 100 5 3 125 6.3 3.8 -150 30 2 60 3 1.8 90 4.5 2.7 120 6 3.6 150 7.5 4.5 -175 , 10 6 -250 50 2.5 1.5 100 5 3 150 7.5 4.5 200 10 6 250 12.5 7.5 -500 100 5 3 200 10 6 300 15 9 400 , Tap Delay (trailing edge) tpHL Table 1 ns 1,2,3, 4, 5, 10 Power-up Time tpu 100 ms Input Period


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PDF DS1000 DS1000-IND) DS1000 14-PIN DS1000M DS1000Z 2bl4130 74F04 74LS D012 DS1000-IND
74F04

Abstract: 74LS DS1000 DS1000-IND DS1000M DS1000Z
Text: combination of a 100 % silicon delay line and industry standard DIP and SOIC packaging. In orderto maintain , 1.5 60 3 1.8 -75 15 2 1 30 2 1 45 2.3 1.4 60 3 1.8 75 3.8 2.3 - 100 20 2 1 40 2 1.2 60 3 1.8 80 4 2.4 100 5 3 -125 25 2 1 50 2.5 1.5 75 3.8 2.3 100 5 3 125 6.3 3.8 -150 30 2 1 60 3 1.8 90 4.5 2.7 120 6 , 120 6 3.6 160 8 4.8 200 10 6 -250 50 2.5 1.5 100 5 3 150 7.5 4.5 200 10 6 250 12.5 7.5 -500 100 5 3 , Power-up Time tpu 100 ms Input Period Period 4 (twi) ns 8 CAPACITANCE (TA=25°C PARAMETER


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PDF DS1000 DS1000-IND) DS1000 14-PIN DS1000M DS1000Z 74F04 74LS DS1000-IND
1995 - 74ls series

Abstract: DS1000Z "Delay Lines" TTL 74LS 00 TTL pin 74LS 00 74F04 74LS DS1000 DS1000M
Text: combination of a 100 % silicon delay line and industry standard DIP and SOIC packaging. In order to maintain , 2 1 ­50 10 2 ­60 12 ­75 15 ­ 100 TAP 5 TOLERANCE Nom Init , 75 3.8 2.3 40 2 1.2 60 3 1.8 80 4 2.4 100 5 3 1 50 2.5 1.5 1 60 3 1.8 75 3.8 2.3 100 5 3 125 6.3 3.8 90 , 3.2 140 7 4.2 175 8.8 5.3 40 2 1.2 80 50 2.5 1.5 100 4


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PDF DS1000 DS1000 14-PIN 74F04 74ls series DS1000Z "Delay Lines" TTL 74LS 00 TTL pin 74LS 00 74F04 74LS DS1000M
DS-1100

Abstract: EN61010-1 EN61010-2-031 PEAK VOLTAGE ACQUIRE
Text: , , . DS-1000 (80/ 100 /150/250 ) 1 , - 100 (DS-1100), . - 150 (DS-1150), . - 250 (DS-1250), . - 200 / (MS/s) ; - 100 / (MS/s) ; - 25 / (GS/s) ( ). - 10 . - 400 . - . , (1/10/ 100 /1000). . 1 1:1 . 10 , 10. 100 , 100 . 1000 , 1000. 4 , -1100 DS-1150 0 ­ 80 0 ­ 100 0 ­ 150 (40 (40 (40 2/) 2/) 2/) 1 ± 1,5%; 16 8 . DS


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PDF DS-1000 RS-232C DS-1100 EN61010-1 EN61010-2-031 PEAK VOLTAGE ACQUIRE
DS1000

Abstract: 74F04 74LS DS1000-IND DS1000M DS1000Z
Text: over hybrid technology is achieved by the combination of a 100 % silicon delay line and industry , - Nom -20 -25 -30 -35 -40 -45 -50 -60 -75 - 100 -125 -150 -175 -200 -250 -500 4 5 6 7 8 9 10 12 15 20 25 30 35 40 50 100 TAP 1 TOLERANCE Init Temp 2 1 2 1 2 , 10 12 14 16 18 20 24 30 40 50 60 70 80 100 200 TAP 2 TOLERANCE Init Temp 2 1 2 , TEST CONDITION IOH Nom 20 25 30 35 40 45 50 60 75 100 125 150 175 200 250 500


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PDF DS1000 DS1000-IND) DS1000M 300-mil) 74F04 DS1000 74LS DS1000-IND DS1000Z
Not Available

Abstract: No abstract text available
Text: reliability over hybrid technology is achieved by the combination of a 100 % silicon delay line and industry , 2 1 45 2.3 1.4 60 3 1.8 75 3.8 2.3 - 100 20 2 1 40 2 1.2 60 3 1.8 80 4 2.4 100 5 3 -125 25 2 1 50 2.5 1.5 75 3.8 2.3 100 5 3 125 6.3 3.8 -150 30 2 1 60 3 1.8 , 2.4 120 6 3.6 160 8 4.8 200 10 6 -250 50 2.5 1.5 100 5


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PDF S1000 DS1000 DS1000 14-PIN 2bl4130 74F04 Q01bS2Q
HEDS1000

Abstract: HEDS-1000
Text: achieved by the combination of a 100 % silicon delay line and industry standard DIP and SOIC packaging. In , 1 TOLERANCE PART# DS1000- 20 -2 5 -3 0 -3 5 -4 0 - 45 -5 0 -6 0 -7 5 - 100 -125 -150 -175 -200 -250 -500 Nom Init 4 5 6 7 8 g 10 12 15 20 25 30 35 40 50 100 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2.5 5 Temp 1 1 1 1 1 1 1 1 1 1 1 1 1.1 1.2 1.5 3 8 10 12 14 16 18 20 24 30 40 50 60 70 80 100 200 Norn Init 2 2 2 2 2 2 , 1 1 1 1 1 1 1.1 1.4 1.8 2.3 2.7 3.2 3.6 4.5 9 16 20 24 28 32 36 40 48 60 80 100 120 140 160 200 400


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PDF DS1000 14-PIN DS1000 74F04 HEDS1000 HEDS-1000
q4ng

Abstract: 8pin hybrid board
Text: technology is achieved by the com bination of a 100 % silicon delay line and industry standard DIP and SOIC


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PDF DS1000 DS1000 14-PIN q4ng 8pin hybrid board
74F04

Abstract: 74LS DS1000 DS1000-IND DS1000M DS1000Z PS1000
Text: hybrid technology is achieved by the combination of a 100 % silicon delay line and industry standard DIP , 2.4 1.5 60 3 1.8 -75 15 2 1 30 2 1 45 2.3 1.4 60 3 1.8 75 3.8 2.3 - 100 20 2 1 40 2 1.2 60 3 1.8 80 4 2.4 100 5 3 -125 25 2 1 50 2.5 1.5 75 3.8 2.3 100 5 3 125 6.3 3.8 -150 30 2 1 60 3 1.8 90 4.5 2.7 , 2.4 120 6 3.6 160 8 4.8 200 10 6 -250 50 2.5 1.5 100 5 3 150 7.5 4.5 200 10 6 250 12.5 7.5 -500 100 , , 10 Power-up Time tpu 100 ms Input Period Period 4 (twi) ns 8 2 of 5 DSIOOO CAPACITANCE (Ta


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PDF DS1000 DS1000-IND) DS1000 14-Pin 300-mil) DS1000M PS1000 74F04 74LS DS1000-IND DS1000Z PS1000
2002 - DS21X5Y

Abstract: DS1000-100 DS2151 DS2152 DS2153 DS2154 DS2155
Text: Application Note 307 DS2151, DS2152, DS2153, DS2154, DS21X5Y, and DS2155 Three-Channel Drop and Insert www.maxim-ic.com NOTES: 1) A "looped-timed" application is shown. 2) This application assumes the dropped channels occupy the same timeslots as the inserted channels. 3) The idle registers in the DS2152, DS2154, DS21X5Y, and DS2155 can be used to fill unused (if any) channels. 4) The used channels do not need to be contiguous nor do they need to be only one channel wide. 5) The DS1000-100


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PDF DS2151, DS2152, DS2153, DS2154, DS21X5Y, DS2155 DS2155 DS21X5Y DS1000-100 DS2151 DS2152 DS2153 DS2154
Not Available

Abstract: No abstract text available
Text: . Low cost and superior reliability over hybrid technology is achieved by the com bination of a 100 , -4 0 - 45 -5 0 -6 0 -7 5 - 100 -125 -150 -175 -200 -250 -500 Nom Init 4 5 6 7 8 g 10 12 15 20 25 30 35 40 50 100 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2.5 5 T&V 2 2 2 2 2 2 2 2 2 2 2 2.4 2.8 3.2 4 8 8 10 12 14 16 18 20 24 30 40 50 60 70 80 100 200 Nom Init 2 2 2 2 2 2 2 2 2 2 2.5 3 3.5 4 5 10 T&V 2 2 2 2 2 2 2 , 24 16 20 24 28 32 36 40 48 60 80 100 120 140 160 200 400 TAP 3 TOLERANCE Norn Init 2 2 2 2 2 2 2 2.4


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PDF DS1000-1ND DS1000-1 14-PIN DS1000 74F04
2002 - dallas date code ds1230

Abstract: 25091 e8 sot223 24446
Text: POINT QTY FAIL 100 11 0 RELIABILITY MONITOR STRESS: TEMP CYCLE CONDITIONS: -55C TO 125C LOT NO , 300 300 300 1000 300 300 300 300 1000 300 77 77 77 100 100 77 77 77 77 77 77 77 77 77 15 0 0 0 0 0 0 0 , 77 100 77 77 77 77 77 77 77 77 77 11 15 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 Low Profile Module Low , ) PACKAGE SOT223 SOT223 TO226 (PR35) READ POINT QTY FAIL 100 100 100 100 100 100 77 72 72 77 70 56 0 0 , 959 274 959 274 274 959 274 959 274 959 274 959 274 959 274 959 77 77 77 77 77 77 77 100 100 77 70 70


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PDF DS1621 DS1869 DK815282AAB DJ824247ABA DM846764AA DS2502 DS87C520 DN901118AAB DK935356AAB dallas date code ds1230 25091 e8 sot223 24446
DS2155

Abstract: DS1000-100 DS21352 DS21354 DS2151 DS2152 DS2153 DS2154 DS21X5Y
Text: contiguous nor do they need to be only one channel wide. 5. The DS1000-100 delay line is used to adjust the


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PDF DS2152, DS2154, DS2151, DS2153, DS21X5Y, DS2155 DS2155 DS1000-100 DS21352 DS21354 DS2151 DS2152 DS2153 DS2154 DS21X5Y
2002 - dallas date code ds1230

Abstract: dallas date code dallas ds1230 code 25807
Text: 100 500 100 500 11 11 11 11 0 0 0 0 RELIABILITY MONITOR STRESS: TEMP CYCLE CONDITIONS: -55C TO , 1000 300 300 300 1000 300 300 1000 300 77 77 100 100 100 100 100 100 100 77 76 77 77 77 77 77 77 77 15 , 288 960 288 960 288 960 288 288 960 288 960 288 960 288 288 288 960 288 960 192 384 192 77 77 100 100 100 100 100 77 76 77 77 77 77 77 77 77 77 77 77 11 11 11 0 0 0 0 0 0 0 1 1 0 1 0 0 0 20 0 0 0 0 0 0 0 , %R.H.,5.5V LOT NO. PACKAGE READ POINT QTY FAIL 100 73 3 MONITOR DATE ASSEMBLY DATE PRODUCT REV JOB NO


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PDF DS5002 DS87C520 DM925587AAF DN901118AAB DK935356AAB J-STD-020 DM929359AB DS1232 DS1233 dallas date code ds1230 dallas date code dallas ds1230 code 25807
1997 - DS1000-100

Abstract: DS2151 DS2153
Text: DS2141A/43/51/53 Application Note PCM Interface, Three Channel Drop & Insert July 18, 1994 DS2141A/43/51/53 RSYNC Channel 1 TSYNC Bursty Clock Receive Data Transmit Data RSER RNEG RPOS RCLK TCLK TPOS TNEG RCHCLK A RCHBLK Decoder TCHBLK B C D TCHCLK A Mux TSER B C D IN Channel 2 Bursty Clock Receive Data Transmit Data Channel 3 Bursty Clock Receive Data Transmit Data TAP5 DS1000-100 (100ns delay) Notes: 1. a "looped-timed"


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PDF DS2141A/43/51/53 DS2141A/43/51/53 DS1000-100 100ns DS2151 DS2153 DS1000-100
2002 - Not Available

Abstract: No abstract text available
Text: No file text available


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PDF DM941226AA DM941230AG DS2502 DM941230AG DM941226AA
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