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2002 - 405d5

Abstract: DS083-2
Text: 0 R Virtex-II ProTM Platform FPGAs: Functional Description 0 0 DS083-2 (v1.0) January 31 , without notice. DS083-2 (v1.0) January 31, 2002 Advance Product Specification www.xilinx.com , by the received data and reference clock applied. 10 www.xilinx.com 1-800-255-7778 DS083-2 , TX Termination Supply TX Figure 2 : Rocket I/O Block Diagram DS083-2 (v1.0) January 31, 2002 , adjust the differential output level between 400 mV and 800 mV in four increments of 100 mV. DS083-2 (v1


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PDF DS083-2 PPC405 405d5 DS083-2
2004 - XC2VP30

Abstract: XC2VP100 XC2VP70
Text: Parameter Guidelines DCM Timing Parameters Module 2 : Functional Description DS083-2 (v4.1) November 17 , Description Product Specification DS083-2 (v4.1) November 17, 2004 Virtex-II Pro(1) Array Functional , without notice. DS083-2 (v4.1) November 17, 2004 Product Specification www.xilinx.com 1-800-255-7778 , _34_050704 Figure 3: RocketIO X Transmit Termination Figure 2 : CML Output Configuration DS083-2 (v4 , PMA Attribute Load Figure 4: RocketIO X Transceiver Block Diagram DS083-2 (v4.1) November 17


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PDF DS083 DS083-1 DS083-3 DS083-2 DS083-4 XC2VP30 XC2VP100 XC2VP70
2003 - IBM powerpc 405

Abstract: K2M11 XC2VP70 FF1704 pinout
Text: Guidelines DCM Timing Parameters Module 2 : Functional Description DS083-2 (v2.9) October 14, 2003 48 , ProTM Platform FPGAs: Functional Description 0 0 DS083-2 (v2.9) October 14, 2003 Advance Product , owners. All specifications are subject to change without notice. DS083-2 (v2.9) October 14, 2003 , www.xilinx.com 1-800-255-7778 DS083-2 (v2.9) October 14, 2003 Advance Product Specification R Virtex-II , code. If the K-character input is Low, the 8 bits are encoded DS083-2 (v2.9) October 14, 2003


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PDF DS083 DS083-1 DS083-3 FF1696) DS083-4 IBM powerpc 405 K2M11 XC2VP70 FF1704 pinout
2004 - 405D5

Abstract: dci -dc inverter XAPP290 basic block diagram of bit slice processors carry look ahead adder 405D4 transmitter circuit in GPR LVCMOS33 PPC405 repeater 10g passive
Text: 0 48 Virtex-II ProTM Platform FPGAs: Functional Description R DS083-2 (v3.1.1) March 9 , owners. All specifications are subject to change without notice. DS083-2 (v3.1.1) March 9, 2004 , GND 2.5V TX Termination Supply TX DS083-2_04_090402 Figure 2 : RocketIO Transceiver Block Diagram 2 www.xilinx.com 1-800-255-7778 DS083-2 (v3.1.1) March 9, 2004 Product Specification , bits are encoded DS083-2 (v3.1.1) March 9, 2004 Product Specification Serializer The


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PDF DS083-2 405D5 dci -dc inverter XAPP290 basic block diagram of bit slice processors carry look ahead adder 405D4 transmitter circuit in GPR LVCMOS33 PPC405 repeater 10g passive
2003 - Not Available

Abstract: No abstract text available
Text: „¢ Platform FPGAs: Functional Description R DS083-2 (v2.7) June 2 , 2003 0 0 Advance Product , owners. All specifications are subject to change without notice. DS083-2 (v2.7) June 2 , 2003 Advance , GND 2.5V TX Termination Supply TX DS083-2_04_090402 Figure 2 : RocketIO Transceiver Block Diagram 2 www.xilinx.com 1-800-255-7778 DS083-2 (v2.7) June 2 , 2003 Advance Product , bits are encoded DS083-2 (v2.7) June 2 , 2003 Advance Product Specification Serializer The


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PDF DS083-1 18-bit FF1148) FF1517) FF1696) DS083-4
2003 - vhdl code for uart communication

Abstract: XC2VP50
Text: Platform FPGAs: Functional Description 0 0 DS083-2 (v2.5.1) March 24, 2003 Advance Product , owners. All specifications are subject to change without notice. DS083-2 (v2.5.1) March 24, 2003 , www.xilinx.com 1-800-255-7778 DS083-2 (v2.5.1) March 24, 2003 Advance Product Specification R Virtex-II , code. If the K-character input is Low, the 8 bits are encoded DS083-2 (v2.5.1) March 24, 2003 , the input stream to ensure proper alignment of data being read through multiple transceivers DS083-2


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PDF DS083-1 18-bit FG676 XC2VP20, XC2VP30, XC2VP40. FF1517 vhdl code for uart communication XC2VP50
2004 - XC2VP40

Abstract: ultra fine pitch BGA XC2VP2-FG256 AF103 XC2VP70 FF1704 pinout XC2VP100 FF672 AJ33 AJ34 AJ35 AJ36 AJ37 AJ38 AJ39 AJ40 AJ41 AJ42 diode t25 4 L9 XC2VP50
Text: are available. Table 1 and Table 2 show the maximum number of user I/Os possible in wire-bond and , x 26 140 248 412 Maximum I/Os Table 2 : Flip-Chip Packages Information Package FF672 , RocketIO MGT Pins - - - - - - 144 180 - Differential I/O Pairs 2 FF1517 , transceiver (1.8V - 2.8V). GNDA# ( 2 ) Input Ground for the analog circuitry of the RocketIO , _1/VRN_1 C15 2 IO_L01N_ 2 /VRP_ 2 E14 2 IO_L01P_ 2 /VRN_ 2 E15 2 IO_L02N_ 2 E13


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PDF DS083-4 FG256 FG456 FG676 FF672 FF896 FF1152 FF1148 FF1517 FF1704 XC2VP40 ultra fine pitch BGA XC2VP2-FG256 AF103 XC2VP70 FF1704 pinout XC2VP100 AJ33 AJ34 AJ35 AJ36 AJ37 AJ38 AJ39 AJ40 AJ41 AJ42 diode t25 4 L9 XC2VP50
2002 - vhdl code for spi xilinx

Abstract: vhdl code for uart communication 16 BIT ALU design with verilog hdl code XC2VP30 XC2VPX70 XC2VP70
Text: and Virtex-II Pro X Platform FPGAs: Functional Description Product Specification DS083-2 (v4 , subject to change without notice. DS083-2 (v4.3) June 20, 2005 Product Specification www.xilinx.com , Driver DS083-2_66_052104 ug083_34_050704 Figure 3: RocketIO X Transmit Termination Figure 2 : CML Output Configuration DS083-2 (v4.3) June 20, 2005 Product Specification www.xilinx.com Module 2 , DS083-2 (v4.3) June 20, 2005 Product Specification www.xilinx.com Module 2 of 4 3 R


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PDF DS083 XC2VP30-FF1152 DS083-4 vhdl code for spi xilinx vhdl code for uart communication 16 BIT ALU design with verilog hdl code XC2VP30 XC2VPX70 XC2VP70
2004 - verilog hdl code for uart

Abstract: XC2VP70 FF1704 pinout XC2VP50
Text: Module 2 : Functional Description DS083-2 (v3.1.1) March 9, 2004 48 pages · · · · Functional Description , DS083-2 (v3.1.1) March 9, 2004 Product Specification Virtex-II Pro Array Functional Description , subject to change without notice. DS083-2 (v3.1.1) March 9, 2004 Product Specification , www.xilinx.com 1-800-255-7778 DS083-2 (v3.1.1) March 9, 2004 Product Specification R Virtex-II ProTM , code. If the K-character input is Low, the 8 bits are encoded DS083-2 (v3.1.1) March 9, 2004 Product


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PDF DS083 DS083-1 DS083-3 Des05/19/03 DS083-4 verilog hdl code for uart XC2VP70 FF1704 pinout XC2VP50
2002 - Not Available

Abstract: No abstract text available
Text: Description R DS083-2 (v2.3) November 20, 2002 0 0 Advance Product Specification Virtex-II , notice. DS083-2 (v2.3) November 20, 2002 Advance Product Specification www.xilinx.com , DS083-2_04_090402 Figure 2 : RocketIO Transceiver Block Diagram 2 www.xilinx.com 1-800-255-7778 DS083-2 (v2.3) November 20, 2002 Advance Product Specification R Virtex-II Pro™ Platform FPGAs , code. If the K-character input is Low, the 8 bits are encoded DS083-2 (v2.3) November 20, 2002


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PDF DS083-1 18-bit DS083-4
2002 - transistor bf 244

Abstract: TXBYPASS8B10B XC2VP50
Text: Platform FPGAs: Functional Description 0 0 DS083-2 (v2.4) December 3, 2002 Advance Product , owners. All specifications are subject to change without notice. DS083-2 (v2.4) December 3, 2002 , www.xilinx.com 1-800-255-7778 DS083-2 (v2.4) December 3, 2002 Advance Product Specification R Virtex-II , K-characters available in the 8B/10B code. If the K-character input is Low, the 8 bits are encoded DS083-2 , the input stream to ensure proper alignment of data being read through multiple transceivers DS083-2


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PDF DS083-1 18-bit DS083-4 transistor bf 244 TXBYPASS8B10B XC2VP50
2002 - XC2VP20

Abstract: XC2VP50 XC2VP100 XC2VP70
Text: Description 0 0 DS083-2 (v2.0) June 13, 2002 Advance Product Specification · FPGA fabric based on , specifications are subject to change without notice. DS083-2 (v2.0) June 13, 2002 Advance Product , Figure 2 : Rocket I/O Block Diagram 2 www.xilinx.com 1-800-255-7778 DS083-2 (v2.0) June 13, 2002 , code. If the K-character input is Low, the 8 bits are encoded DS083-2 (v2.0) June 13, 2002 Advance , " and "out-of-band" errors. A disparity error 4 www.xilinx.com 1-800-255-7778 DS083-2 (v2


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PDF DS083-1 18-bit DS083-4 XC2VP20 XC2VP50 XC2VP100 XC2VP70
2003 - Virtex-II Pro xc2vp70ff1517

Abstract: XC2VP20FF896 XC2VP100 XC2VP70
Text: to 3.0 ­0.5 to 3.0 ­65 to +150 +220 +125 ( 2 ) Units V V V V V V V V V V V V V °C °C °C VTS , time might affect device reliability. 2 . For 3.3V operation, TJ must be less than 100°C. © 2003 , Virtex-II Pro Electrical Characteristics R Table 2 : Recommended Operating Conditions Symbol VCCINT , V V V V V V VCCAUX(1) VCCO( 2 ) Commercial GND ­ 0.2 Industrial GND ­ 0.2 Commercial GND ­ , maximum voltage droop for VCCAUX is 10 mV/ms. 2 . Configuration data is retained even if VCCO drops to 0V


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PDF DS083-3 Virtex-II Pro xc2vp70ff1517 XC2VP20FF896 XC2VP100 XC2VP70
2002 - LVDCI25

Abstract: rocket battery 150 XC2VP20 XC2VP50
Text: ­0.5 to 3.45 ­0.5 to 3.45 ­0.5 to 3.45 ­0.5 ( 2 ) to 3.45 (4) ­0.5 (3) to 3.45 (5) ­0.5 to 3.45 ­0.5 to , Maximum Ratings conditions for extended periods of time might affect device reliability. 2 . For 3.3V I/O , Characteristics R Table 2 : Recommended Operating Conditions Symbol VCCINT Description Internal supply , ) VCCO( 2 ) VBATT(3) VCCAUXRX, VCCAUXTX Notes: 1. For LVDS operation, VCCAUX min is 2.37V and max is 2.63V. 2 . Configuration data is retained even if VCCO drops to 0V. 3. If battery is not used, do not


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PDF DS083-3 LVDCI25 rocket battery 150 XC2VP20 XC2VP50
2004 - Virtex-II Pro xc2vp70ff1517

Abstract: XC2VP100 xc2vp40ff1148 XC2VP70 XC2VP100FF1704 xilinx Xilinx XC2VP30-FF896 XAPP623 XAPP659 XC2VP30-FF896 speed XC2VP40
Text: soldering temperature ( 2 ) Maximum junction temperature ( 2 ) Notes: 1. Stresses beyond those listed , of time might affect device reliability. 2 . For soldering guidelines and thermal considerations, see , www.xilinx.com 1-800-255-7778 1 R Table 2 : Recommended Operating Conditions Symbol VCCINT VCCAUX(1) VCCO( 2 ,3) Description Internal supply voltage relative to GND, TJ = 0 °C to +85°C , droop for VCCAUX is 10 mV/ms. 2 . Configuration data is retained even if VCCO drops to 0V. 3. For 3.3V


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PDF DS083-3 CLK2X180. CLK2X180; CLK180; Virtex-II Pro xc2vp70ff1517 XC2VP100 xc2vp40ff1148 XC2VP70 XC2VP100FF1704 xilinx Xilinx XC2VP30-FF896 XAPP623 XAPP659 XC2VP30-FF896 speed XC2VP40
2002 - vhdl code for data memory

Abstract: daisy chain verilog vhdl code for sdram controller digital IIR Filter VHDL code serdes ip XC2VP7-FG456 XAPP290 FF672 FF1152 FF1148
Text: : RocketIO X Transmit Termination DS083-2_66_052104 Figure 2 : CML Output Configuration DS083-2 (v4. 2 , Description DS083-2 (v4. 2 ) March 1, 2005 Product Specification Virtex-II Pro(1) Array Functional , property of their respective owners. All specifications are subject to change without notice. DS083-2 , Diagram DS083-2 (v4. 2 ) March 1, 2005 Product Specification www.xilinx.com Module 2 of 4 3 R , . DS083-2 (v4. 2 ) March 1, 2005 Product Specification This clock is presented to the FPGA fabric at 1


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PDF DS083 DS083-4 vhdl code for data memory daisy chain verilog vhdl code for sdram controller digital IIR Filter VHDL code serdes ip XC2VP7-FG456 XAPP290 FF672 FF1152 FF1148
2003 - AW134

Abstract: FF1148 XC2VP30 tag a2 255 600 XAPP290 FG676 FG256 FF672 DS083 XC2VP70 FF1704 pinout
Text: : Pinout Information DS083-2 (v3.0) December 10, 2003 50 pages DS083-4 (v3.0) December 10, 2003 298 , Description R DS083-2 (v3.0) December 10, 2003 0 0 Product Specification Virtex-II Pro Array , notice. DS083-2 (v3.0) December 10, 2003 Product Specification www.xilinx.com 1-800-255-7778 1 , transceiver and its FPGA interface signals. www.xilinx.com 1-800-255-7778 DS083-2 (v3.0) December 10 , Figure 2 : RocketIO Transceiver Block Diagram DS083-2 (v3.0) December 10, 2003 Product Specification


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PDF DS083 DS083-1 DS083-3 Parameter2VP70 XC2VP100 DS083-4 AW134 FF1148 XC2VP30 tag a2 255 600 XAPP290 FG676 FG256 FF672 XC2VP70 FF1704 pinout
2003 - verilog coding using instantiations

Abstract: 405d4 XC2VP7-FF896 XAPP290 molex Connector FG676 FG256 FF672 FF1148 XC2VP70 FF1704 pinout
Text: : Pinout Information DS083-2 (v2.9) October 14, 2003 48 pages DS083-4 (v2.5.5) August 25, 2003 298 , Specification 0 48 Virtex-II ProTM Platform FPGAs: Functional Description R DS083-2 (v2 , owners. All specifications are subject to change without notice. DS083-2 (v2.9) October 14, 2003 , TX/RX GND 2.5V TX Termination Supply TX DS083-2_04_090402 Figure 2 : RocketIO Transceiver Block Diagram 2 www.xilinx.com 1-800-255-7778 DS083-2 (v2.9) October 14, 2003 Advance Product


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PDF DS083 DS083-1 DS083-3 DS083-4 verilog coding using instantiations 405d4 XC2VP7-FF896 XAPP290 molex Connector FG676 FG256 FF672 FF1148 XC2VP70 FF1704 pinout
2003 - Not Available

Abstract: No abstract text available
Text: Description Module 4: Pinout Information DS083-2 (v2.8) September 10, 2003 48 pages DS083-4 (v2 , „¢ Platform FPGAs: Functional Description R DS083-2 (v2.8) September 10, 2003 0 0 Advance , owners. All specifications are subject to change without notice. DS083-2 (v2.8) September 10, 2003 , TX/RX GND 2.5V TX Termination Supply TX DS083-2_04_090402 Figure 2 : RocketIO Transceiver Block Diagram 2 www.xilinx.com 1-800-255-7778 DS083-2 (v2.8) September 10, 2003 Advance


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PDF DS083 DS083-1 DS083-3 DS083-4
2003 - vhdl code for uart communication

Abstract: XC2VP50 XC2VP70 FF1704 pinout
Text: Platform FPGAs: Functional Description 0 0 DS083-2 (v2.7) June 2 , 2003 Advance Product Specification , owners. All specifications are subject to change without notice. DS083-2 (v2.7) June 2 , 2003 Advance , www.xilinx.com 1-800-255-7778 DS083-2 (v2.7) June 2 , 2003 Advance Product Specification R Virtex-II , code. If the K-character input is Low, the 8 bits are encoded DS083-2 (v2.7) June 2 , 2003 Advance , the input stream to ensure proper alignment of data being read through multiple transceivers DS083-2


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PDF DS083-1 18-bit DS083-4 vhdl code for uart communication XC2VP50 XC2VP70 FF1704 pinout
2002 - 16 BIT ALU design with verilog hdl code

Abstract: AH5N IBM powerpc 405 XC2VP20 AF124 FG256 function generator PPC405 IEEE1532 XC2VP50
Text: TX Termination Supply TX DS083-2_04_010202 Figure 2 : Rocket I/O Block Diagram DS083-2 (v1 , Virtex-II ProTM Platform FPGAs: Functional Description R DS083-2 (v1.0) January 31, 2002 0 0 , subject to change without notice. DS083-2 (v1.0) January 31, 2002 Advance Product Specification , interface signals. www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product , increments of 100 mV. www.xilinx.com 1-800-255-7778 DS083-2 (v1.0) January 31, 2002 Advance Product


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PDF DS083-1 18-bit DS083-4 16 BIT ALU design with verilog hdl code AH5N IBM powerpc 405 XC2VP20 AF124 FG256 function generator PPC405 IEEE1532 XC2VP50
2004 - ATM machine working circuit diagram

Abstract: gearbox 405 Virtex-II Pro xc2vp50ff1152 Virtex-II Pro xc2vp70ff1517 K162 Virtex-II D37 connector pcb 250v ACE 69 R 2.8 no pinout 4 "Digital Delay Lines"
Text: Description Module 4: Pinout Information DS083-2 (v4.0) June 30, 2004 59 pages DS083-4 (v4.0) June , Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description DS083-2 (v4.0) June 30, 2004 , to change without notice. DS083-2 (v4.0) June 30, 2004 Product Specification www.xilinx.com , Figure 2 : CML Output Configuration DS083-2 (v4.0) June 30, 2004 Product Specification , 4: RocketIO X Transceiver Block Diagram DS083-2 (v4.0) June 30, 2004 Product Specification


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PDF DS083 DS083-1 DS083-3 DS083-4 ATM machine working circuit diagram gearbox 405 Virtex-II Pro xc2vp50ff1152 Virtex-II Pro xc2vp70ff1517 K162 Virtex-II D37 connector pcb 250v ACE 69 R 2.8 no pinout 4 "Digital Delay Lines"
2002 - Not Available

Abstract: No abstract text available
Text: 0 Virtex-II Pro™ Platform FPGAs: Functional Description R DS083-2 (v2.0) June 13, 2002 , owners. All specifications are subject to change without notice. DS083-2 (v2.0) June 13, 2002 Advance , Termination Supply TX DS083-2_04_010202 Figure 2 : Rocket I/O Block Diagram 2 www.xilinx.com 1-800-255-7778 DS083-2 (v2.0) June 13, 2002 Advance Product Specification R Virtex-II Pro™ Platform , K-characters available in the 8B/10B code. If the K-character input is Low, the 8 bits are encoded DS083-2


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PDF DS083-2
2004 - Virtex-II Pro xc2vp50ff1152

Abstract: XC2VP50 250v ACE 69 IOL29 XC2VP30 4 BIT ALU design with verilog vhdl code XAPP290 FG256 FF672 FF1148
Text: : Pinout Information DS083-2 (v3.1) February 19, 2004 48 pages DS083-4 (v3.1) February 19, 2004 299 , : Functional Description R DS083-2 (v3.1) February 19, 2004 0 0 Product Specification , subject to change without notice. DS083-2 (v3.1) February 19, 2004 Product Specification , Termination Supply TX DS083-2_04_090402 Figure 2 : RocketIO Transceiver Block Diagram 2 www.xilinx.com 1-800-255-7778 DS083-2 (v3.1) February 19, 2004 Product Specification R Virtex-II


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PDF DS083 DS083-1 DS083-3 DS083-4 Virtex-II Pro xc2vp50ff1152 XC2VP50 250v ACE 69 IOL29 XC2VP30 4 BIT ALU design with verilog vhdl code XAPP290 FG256 FF672 FF1148
2003 - vhdl code for uart communication

Abstract: wireless encrypt XC2VP70 FF1704 pinout
Text: Guidelines DCM Timing Parameters Module 2 : Functional Description DS083-2 (v2.7.1) August 25, 2003 48 , ProTM Platform FPGAs: Functional Description 0 0 DS083-2 (v2.7.1) August 25, 2003 Advance Product , owners. All specifications are subject to change without notice. DS083-2 (v2.7.1) August 25, 2003 , www.xilinx.com 1-800-255-7778 DS083-2 (v2.7.1) August 25, 2003 Advance Product Specification R , code. If the K-character input is Low, the 8 bits are encoded DS083-2 (v2.7.1) August 25, 2003


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PDF DS083 DS083-1 DS083-3 FF1696) DS083-4 vhdl code for uart communication wireless encrypt XC2VP70 FF1704 pinout
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