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Top Results (4)

Part Manufacturer Description Datasheet Download Buy Part
STL025W6DQ (1589809-8) TE Connectivity (1589809-8) STL025W6DQ = Thru-Hole
STM037W61DQ (1589942-1) TE Connectivity (1589942-1) STM037W61DQ = Thru-Hole
SSM009W6DQ (1589812-2) TE Connectivity (1589812-2) SSM009W6DQ = Thru-Hole
STG015M6DQ (1589487-2) TE Connectivity (1589487-2) STG015M6DQ = THRU-HOLE

DQ15-DQ0 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2006 - DQ15-DQ0

Abstract: PD20
Text: organization. The BYTE# pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic '1', the device is in word configuration and DQ15-DQ0 are , , DQ15-DQ0 , and the second flash is connected to the high word lane, DQ23 to DQ16 (Figure 2.1). To address , device is configured as x16 or word mode, as in this design example, data I/O pins DQ15-DQ0 become , command, DQ15-DQ0 data bits are used to set appropriate word count (WC). Since maximum word count is 16


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PDF DQ15-DQ0 DQ15-DQ8 PD20
2000 - f16e

Abstract: No abstract text available
Text: Supply To provide 3.0 volts supply.(2.7 to 3.3 volts) GND Ground DQ15-DQ0 NC No , Buffer & Latches 256Kx16 X-Decoder Flash Bank1 256Kx16 A18-A0 Flash Bank2 DQ15-DQ0 , CE# TOE OE# TOHZ TOLZ VIH WE# TCHZ TCLZ HIGH-Z DQ15-DQ0 TOH DATA VALID , OE# TCEH CE# TCES DQ15-DQ0 AA SW0 55 SW1 A0 SW2 DATA WORD (ADDR/DATA , DQ15-DQ0 AA SW0 55 A0 SW1 DATA SW2 WORD (ADDR/DATA) 808T\808_ENG\F4-2_E Figure


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PDF LE28DW8102T 16141\168T\ xxxx-19/19 f16e
A23A0

Abstract: A23-A0 DQ15-DQ0 S29WS-N S29WS256N
Text: GDWD OLQHV DUH ELGLUHFWLRQDO ELGLUHFWLRQDO EXIIHUV DUH QHHGHG RQ WKH GDWD OLQHV DQ15-DQ0 DQ15-DQ0 , Using_S29WS-N_on_3V-Systems_AN_A0 July 5, 2005 A p p l i c a t i o n CPU Vcc 3.3 V DQ15-DQ0 N o t e Flash Vcc 1.8 V TI SN74AVCA164245 VCCA VCCB A B DIR OE# DQ15-DQ0 1.8 V OE# VCC


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PDF S29WS256N S29WS-N A23A0 A23-A0 DQ15-DQ0
2002 - LE28DW3215AT-80

Abstract: flash "simultaneous read write" 198 DQ15-DQ0 A20-A0
Text: A19-A0 A19-A15 A19-A10 DQ15-DQ0 CE# OE# WE# VDD VSS NC Pin Name Bank Select address Flash , Bank2 1024K x 16 A20-A0 CE# OE# WE# Flash Bank1 DQ15-DQ0 Control Logic I/O Buffers & , HIGH-Z DQ15-DQ0 DATA VALID TCHZ DATA VALID HIGH-Z Figure3: Read Cycle Timing Diagram , TWP WE# TAS TDS TWPH OE# TCEH CE# TCES DQ15-DQ0 AA SW0 55 SW1 A0 SW2 , # TWEH WE# TWES AA SW0 DQ15-DQ0 55 SW1 A0 SW2 DATA WORD (ADDR/DATA) Figure4


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PDF LE28DW3215AT-80 16Mbit 1024K 000Cycles 000Cycies 10years 15sec 500ms LE28DW3215AT-80 flash "simultaneous read write" 198 DQ15-DQ0 A20-A0
2012 - W764M32V1-XBX

Abstract: No abstract text available
Text: tCE tOH A25-A0 tDF CS# tDF tOE tOH OE# DQ15-DQ0 Back to Back Read Operation (tRC , tDF OE# DQ15-DQ0 FIGURE 4 – PAGE READ TIMING tACC A25-A4 A3-A0 tCE CS# tOE OE# tPACC DQ15-DQ0 NOTE: Word Configuration: Toggle A0, A1, A2, and A3. Microsemi Corporation , # tDS tDH DQ15-DQ0 FIGURE 8 – BACK TO BACK (CS#VIL) WRITE OPERATION TIMING DIAGRAM tWC A25-A0 tAS tAH tCS CS# OE# tWP tWPH WE# tDS tDH DQ15-DQ0 Microsemi Corporation reserves the


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PDF W764M32V1-XBX 64Mx32 W764M32V1-XBX 32-bit 16-bit 1024-byte prx32
2000 - bax 50

Abstract: No abstract text available
Text: or CE# is high. DQ15-DQ0 CE# Chip Enable To activate the Flash Bank w hen CE# is low. OE , -1 Flash Bank1 CE# OE# WE# WP# RY/BY# RESET# BYTE# DQ15-DQ0 Control Logic I/O Buffers & Data , CE# TOE OE# TOHZ TOLZ VIH WE# TCHZ TCLZ HIGH-Z DQ15-DQ0 TOH DATA VALID , 2AAA 5555 ADDR TDH TWP WE# TAS TDS TWPH OE# TCEH CE# TCES DQ15-DQ0 AA , OE# TWEH WE# TWES DQ15-DQ0 AA SW0 55 A0 SW1 DATA SW2 WORD (ADDR/DATA


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PDF 12Mbit 1536K LE28DW1621T-80T xxxx-19/20 xxxx-20/20 bax 50
2012 - Microsemi

Abstract: No abstract text available
Text: tCE tOH A25-A0 tDF CS# tDF tOE tOH OE# DQ15-DQ0 Back to Back Read Operation (tRC , tDF OE# DQ15-DQ0 FIGURE 4 – PAGE READ TIMING tACC A25-A4 A3-A0 tCE CS# tOE OE# tPACC DQ15-DQ0 NOTE: Word Configuration: Toggle A0, A1, A2, and A3. Microsemi Corporation , CS# OE# tWP tWPH WE# tDS tDH DQ15-DQ0 FIGURE 8 – BACK TO BACK (CS#VIL) WRITE OPERATION TIMING DIAGRAM tWC A25-A0 tAS tAH tCS CS# OE# tWP tWPH WE# tDS tDH DQ15-DQ0


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PDF W764M32V1-XBX 64Mx32 W764M32V1-XBX 32-bit 16-bit 1024-byte Microsemi
1997 - P8025

Abstract: MU9C8148 DRA110 MU9C1 BNA30 tms38053
Text: INSTRUCTION BUFFER 16 HOST PROCESSOR INTERFACE /E 5 16 LANCAM INTERFACE DQ15-DQ0 A4-A0


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PDF MU9C8148 MU9C1480 MU9C8148s P8025 MU9C8148 DRA110 MU9C1 BNA30 tms38053
2013 - Not Available

Abstract: No abstract text available
Text: tOE tOH OE# DQ15-DQ0 Back to Back Read Operation (tRC)Timing Diagram tRC tACC tOH , address change to initiate the second access. tOE tOH tDF OE# DQ15-DQ0 FIGURE 4 – PAGE READ TIMING tACC A25-A4 A3-A0 tCE CS# tOE OE# tPACC DQ15-DQ0 NOTE: Word Configuration , # tDS tDH DQ15-DQ0 FIGURE 8 – BACK TO BACK (CS#VIL) WRITE OPERATION TIMING DIAGRAM tWC A25-A0 tAS tAH tCS CS# OE# tWP tWPH WE# tDS tDH DQ15-DQ0 Microsemi Corporation reserves the


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PDF W764M32V1-XBX 64Mx32 W764M32V1-XBX 32-bit 16-bit 1024-byte
2000 - Not Available

Abstract: No abstract text available
Text: . DQ15-DQ0 OE# Output Enable To gate the data output buffers. WE# Write Enable To control , # WE# WP# RY/BY# RESET# BYTE# DQ15-DQ0 Control Logic I/O Buffers & Data Latches Figure2 , DQ15-DQ0 TOH DATA VALID HIGH-Z DATA VALID 28DW8163T\F3_E Exsample for Word Mode, in Byte Mode , CE# TCES DQ15-DQ0 AA SW0 55 SW1 A0 SW2 DATA WORD (ADDR/DATA) 28DW8163T\F4 , TWPH OE# TWEH WE# TWES DQ15-DQ0 AA SW0 55 A0 SW1 DATA SW2 WORD (ADDR


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PDF LE28DW8163T-80T xxxx-19/20 xxxx-20/20
2000 - F14E

Abstract: F12E Sakata F13E LE28BW168T 2596H
Text: cycle. The outputs are in tristate when OE# is high or CE# is high. DQ15-DQ0 CE# Chip Enable , 512Kx16 Flash Bank2 A19-A0 CE# OE# WE# DQ15-DQ0 Control Logic I/O Buffers & Data Latches , ADDRESS A19- A0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# TCHZ TCLZ HIGH-Z DQ15-DQ0 , # TAS TDS TWPH OE# TCEH CE# TCES DQ15-DQ0 AA SW0 55 SW1 A0 DATA SW2 , OE# TWEH WE# TWES DQ15-DQ0 AA SW0 55 A0 SW1 DATA SW2 WORD (ADDR/DATA


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PDF LE28BW168T 16141\168T\ xxxx-20/20 F14E F12E Sakata F13E LE28BW168T 2596H
2013 - Not Available

Abstract: No abstract text available
Text: tOE tOH OE# DQ15-DQ0 Back to Back Read Operation (tRC)Timing Diagram tRC tACC tOH , address change to initiate the second access. tOE tOH tDF OE# DQ15-DQ0 FIGURE 4 – PAGE READ TIMING tACC A25-A4 A3-A0 tCE CS# tOE OE# tPACC DQ15-DQ0 NOTE: Word Configuration , CS# OE# tWP tWPH WE# tDS tDH DQ15-DQ0 FIGURE 8 – BACK TO BACK (CS#VIL) WRITE OPERATION TIMING DIAGRAM tWC A25-A0 tAS tAH tCS CS# OE# tWP tWPH WE# tDS tDH DQ15-DQ0


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PDF W764M32V1-XBX 256MB 64Mx32 W764M32V1-XBX 32-bit 16-bit 1024-byte fo2013
IR5L

Abstract: PLCC-44 cr16 AR10-AR0 MX47 0804H ST27-ST16 MU9C1 44-PIN QS762470 QS761480
Text: pin assignments for the 44-pin PLCC are shown in Figures 2 and 3. Data/Command Bus DQ15-DQ0 The DQ15-DQ0 lines convey data, commands, and status to and from the QS761480/QS762470. The state of the WE , the information on the DQ15-DQ0 lines is interpreted as data or as a command or status. DQ0 is the , destination of the data input on the DQ15-DQ0 lines is the Instruction Register; in command read mode (CM is LOW, WE is HIGH), the default source of the data output on the DQ15-DQ0 lines is the Status Register


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PDF QS761480, QS762470 QS761480 QS761480 QS762470 64-bit 16-bit MU9C1480/A MU9C2480/A IR5L PLCC-44 cr16 AR10-AR0 MX47 0804H ST27-ST16 MU9C1 44-PIN
2003 - NORFLASH

Abstract: ic DPD HYE18P32160AC
Text: CellularRAM DQ15-DQ0 CS# WE# OE# UB# LB# (FBGA-54) CRE DQ15-DQ0 (FBGA-54) CRE A20-A0 , selected Control Register WE# UB#, LB# DQ15-DQ0 Don't Care Figure8 Control Register Write , # UB#, LB# WAIT# DQ15-DQ0 Don't Care Infineon Technologies Page 15 of 45 Version 1.8


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PDF HYE18P32160AC-9 FBGA-48 FBGA-56 48-ball 56-ball NORFLASH ic DPD HYE18P32160AC
2001 - LE28DW3212AT-80B

Abstract: sanyo sax
Text: 1024Kx16 A20-A0 CE# OE# WE# WP# RY/BY# RESET# BYTE# Flash Bank1 DQ15-DQ0 Control Logic I/O , ADDRESS A20- A0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# TCHZ TCLZ HIGH-Z DQ15-DQ0 , DQ15-DQ0 AA SW0 55 SW1 A0 SW2 DATA WORD (ADDR/DATA) 28DW3212\F4-1_E Exsample for , OE# TWEH WE# TWES DQ15-DQ0 AA SW0 55 A0 SW1 SW2 DATA WORD (ADDR/DATA , 5555 5555 2AAA 5555 TAH TAS CE# OE# TDS TWPH TWP TDH WE# DQ15-DQ0


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PDF 16Mbit 1024K 2048K LE28DW3212AT-80B 28DW8163T\F19 xxxx-19/19 LE28DW3212AT-80B sanyo sax
1997 - Tbb 38

Abstract: MU9C8248 intel 8248
Text: INTERFACE DQ15-DQ0 6 A5-A0 D15-D0 ALE, SRNW /CS /RS, /LDS /WS, /UDS /HBRDY /HBEN /HBDIR


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PDF MU9C8248 MU9C1480 Tbb 38 MU9C8248 intel 8248
2005 - EN71PL032A0

Abstract: H7 RF EN71PL064 SUNNY EN71PL064A0 A0-A21 S71GL032N40 SA77
Text: ) DQ15-DQ0 CE1#f DQ15-DQ0 CE1#f Chip Enable 1 (pSRAM) CE1#s CE1#ps Chip Enable 2 (pSRAM


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PDF 16-bit) EN71PL032A0 S71GL032N40 EN71PL032A0 S71Gftware EN71PL064A0: 001CH S71GL032N40: H7 RF EN71PL064 SUNNY EN71PL064A0 A0-A21 S71GL032N40 SA77
2005 - EN71PL064

Abstract: H7 RF SUNNY EN71PL064A0 A0-A21 EN71PL
Text: A0-A21 Data Inputs/Outputs (Common) Chip Enable 1 (Flash) DQ15-DQ0 CE1#f DQ15-DQ0 CE1#f


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PDF 16-bit) EN71PL064A0 S71PL064A0 EN71PL227E 200ns S71PL064A0 EN71PL064A0, EN71PL064A0: EN71PL064 H7 RF SUNNY EN71PL064A0 A0-A21 EN71PL
2006 - S29WS256P

Abstract: S29WS-P S73WS-P
Text: # A0-Amax DQ15-DQ0 RDY CLK AVD# CE# OE# RESET# ACC WP# WE# WS-P NOR Flash Memory DQ15-DQ0 D-VCC D-VCC Q 2 RAS# CAS# BA0 BA1 CKE WE# CE# A0-Amax VCC VCCQ S73WS-P , DQ15-DQ0 VSS VSSQ D-VSS D-VSSQ S73WS-P_00_A0 March 16, 2006 D a ta S h e e t ( A dv anc , between NOR Flash and DRAM DQ15-DQ0 = Data input/output, shared between NOR Flash and DRAM


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PDF S73WS-P S29WS256P S29WS-P
2004 - A19 SMD transistor

Abstract: HYE18P32160AC HYE18P32160AW-15
Text: /OE /UB /LB DQ15-DQ0 (FBGA-54) CRE A20-A0 Asynchronous I/F CLK=/ADV=Low and WAIT ignored in Asynchronous I/F Figure 1 DQ15-DQ0 (FBGA-54) CRE A20-A0 32Mb CellularRAM , Register Access CS W rite latched O P C O D E to selected Control Register WE UB, LB DQ15-DQ0 , Control Register Access ADV CS OE WE UB, LB W AIT DQ15-DQ0 Don't Care Figure 8 Control


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PDF HYE18P32160AW-12 HYE18P32160AW-15 A19 SMD transistor HYE18P32160AC HYE18P32160AW-15
2004 - smd diode SL V2

Abstract: HYE18P32160AC
Text: CellularRAM /CS /WE /OE /UB /LB DQ15-DQ0 (FBGA-54) CRE A20-A0 Asynchronous I/F CLK=/ADV=Low and WAIT ignored in Asynchronous I/F Figure 1 DQ15-DQ0 (FBGA-54) CRE A20-A0 32Mb , Register WE UB, LB DQ15-DQ0 Don't Care Figure 7 Control Register Write in NOR-Flash-Type , DQ15-DQ0 Don't Care Figure 8 Data Sheet Control Register Write in Synchronous Mode 20 V2


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PDF
2005 - SMD MARKING CODE A20

Abstract: ic DPD SCR FIR 3 D A22 SMD MARKING CODE A22 SMD CODE SCR IC CHIP smd transistor marking A11 SMD MARKING CODE A12 smd diode code WP infineon memory
Text: -54) Pinning: CLK ADV CS WE OE UB LB CRE 128Mb CellularRAM DQ15-DQ0 (FBGA-54) CS WE OE UB LB DQ15-DQ0 (FBGA-54) CRE WAIT A22-A0 A22-A0 Asynchronous I/F CLK=ADV=Low , selected control register is loaded via DQ15-DQ0 by performing this command. Please refer to the control , (BCR), x1B(DIDR) Select register ADV (note 1) (note 1) CS UB, LB OE WE CRE DQ15-DQ0 , Control Register Access ADV > tWC,min CS OE WE UB, LB WAIT DQ15-DQ0 (Notes) 1. A22 is for


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PDF HYE18P128160AF-9 HYE18P128160AF-12 HYE18P128160AF-15 0002H 0000B 0001B 0010B 0011B 00010B SMD MARKING CODE A20 ic DPD SCR FIR 3 D A22 SMD MARKING CODE A22 SMD CODE SCR IC CHIP smd transistor marking A11 SMD MARKING CODE A12 smd diode code WP infineon memory
2005 - Not Available

Abstract: No abstract text available
Text: /WE /OE /UB /LB CRE A20-A0 32Mb CellularRAM (FBGA-54) DQ15-DQ0 32Mb CellularRAM (FBGA-54) DQ15-DQ0 WAIT Asynchronous I/F CLK=/ADV=Low and WAIT ignored in Asynchronous I/F Sync. Burst I/F , Select Control Register 0(RCR), 1(BCR) Close Address Bus Latch CRE ADV CS WE UB, LB DQ15-DQ0 , A20-A0 A19 CRE ADV CS OE WE UB, LB W AIT DQ15-DQ0 Don't Care OPCODE Latch Control Register Address 0


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PDF HYE18P32160AF-15
2005 - SCR FIR 3 D

Abstract: SMD MARKING CODE A20 infineon memory smd diode code WP smd codes marking A21 smd code marking HD A22 SMD CODE SCR IC CHIP transistor marking A21 ic DPD
Text: state. FETCH CONTROL REGISTER The content of selected control register is loaded via DQ15-DQ0 by , (DIDR) Select register ADV (note 1) (note 1) CS UB, LB OE WE CRE DQ15-DQ0 OPCODE , Control Register Access ADV > tWC,min CS OE WE UB, LB WAIT DQ15-DQ0 (Notes) 1. A22 is for , (DIDR) B B B A19, A18 CRE ADV CS UB, LB OE WE DQ15-DQ0 opcode WAIT Don't Care


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PDF HYE18P64160AF-9 HYE18P64160AF-12 HYE18P64160AF-15 0002H 0000B 0001B 0010B 0011B 00010B SCR FIR 3 D SMD MARKING CODE A20 infineon memory smd diode code WP smd codes marking A21 smd code marking HD A22 SMD CODE SCR IC CHIP transistor marking A21 ic DPD
2004 - A21-A0

Abstract: tray matrix bga DQ15-DQ0
Text: No file text available


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PDF S70JL128H S29JL064H, 16-Bit) S70JL128HA0 A21-A0 tray matrix bga DQ15-DQ0
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