The Datasheet Archive

Top Results (4)

Part Manufacturer Description Datasheet Download Buy Part
SSM009W6DQ (1589812-2) TE Connectivity (1589812-2) SSM009W6DQ = Thru-Hole
STM037W61DQ (1589942-1) TE Connectivity (1589942-1) STM037W61DQ = Thru-Hole
STL025W6DQ (1589809-8) TE Connectivity (1589809-8) STL025W6DQ = Thru-Hole
STG015M6DQ (1589487-2) TE Connectivity (1589487-2) STG015M6DQ = THRU-HOLE
SF Impression Pixel

Search Stock (12)

  You can filter table by choosing multiple options from dropdownShowing 12 results of 12
Part Manufacturer Supplier Stock Best Price Price Each Buy Part
RDQ150110S05 XP Power element14 Asia-Pacific - $208.51 $166.80
RDQ150110S05 XP Power Newark element14 3 $175.00 $147.00
RDQ150110S05 XP Power Allied Electronics & Automation - $175.00 $147.00
RDQ150110S05 XP Power RS Components 2 £121.70 £102.48
RDQ150110S12 XP Power element14 Asia-Pacific - $205.25 $164.20
RDQ150110S12 XP Power Newark element14 1 $175.00 $147.00
RDQ150110S12 XP Power Allied Electronics & Automation - $175.00 $147.00
RDQ150110S12 XP Power RS Components 2 £121.70 £102.48
RDQ150110S24 XP Power RS Components 2 £121.70 £102.48
RDQ150110S24 XP Power Newark element14 3 $175.00 $147.00
RDQ150110S24 XP Power Allied Electronics & Automation - $175.00 $147.00
RDQ150110S24 XP Power element14 Asia-Pacific - $205.25 $164.20

No Results Found

DQ15-0 datasheet (2)

Part Manufacturer Description Type PDF
DQ15001-000 Others Shortform Semicon, Diode, and SCR Datasheets Scan PDF
DQ15002-000 Others Shortform Semicon, Diode, and SCR Datasheets Scan PDF

DQ15-0 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2001 - SST38VF166

Abstract: JEP-137 32h 327
Text: and 1s, i.e. toggling between 0 and 1. When the Write cycle is completed, the toggling will stop. The , ) prevention of write for the first sector, i.e., addresses A5 to A13 are " 0 " (0000H to 001FH). Once the OTP , consecutive attempts to read DQ6 will produce alternating 0s and 1s, i.e. toggling between 0 and 1. When the , T1. 0 327 Note: For the purposes of this table, write means to Word-Write; Block-, Sector-, or , Bank Sector Addresses DQ15-DQ 0 Data Input/output To select an E2 Bank Sector for erase To


Original
PDF SST38VF166 SST38VF16616Mb MO-142 S71065 SST38VF166 JEP-137 32h 327
2000 - JEP-137

Abstract: JESD68 SW4506 T3A-2 SST38VF166 JEP137 be3vil
Text: write for the first sector, i.e., addresses A5 to A13 are " 0 " (0000 to 001F hex). Once the OTP , the Flash bank internal Write cycle, any consecutive attempts to read DQ6 will produce alternating 0 's and 1's, i.e. toggling between 0 and 1. When the Write cycle is completed, the toggling will stop , the E2 bank internal Write cycle, any consecutive attempts to read DQ6 will produce alternating 0 's and 1's, i.e. toggling between 0 and 1. When the Write cycle is completed, the toggling will stop


Original
PDF SST38UF166 SST38VF166 SST38UF166: SST38VF166: 48-BALL JEP-137 JESD68 SW4506 T3A-2 SST38VF166 JEP137 be3vil
2002 - W49L102

Abstract: No abstract text available
Text: TOE #OE VIH TOHZ TOLZ #WE TCLZ T OH TCHZ High-Z High-Z DQ15-0 Data , TWP #WE TWPH TDS DQ15-0 Data Valid TDH #CE Controlled Command Write Cycle Timing Diagram TAS TAH Address A15- 0 TCPH TCP #CE TOES TOEH #OE #WE TDS DQ15-0 High Z , 5555 55 AA DQ15-0 5555 Address A0 Data-In #CE #OE T WPH TBP TWP , Diagram Six-word code for Boot Block Lockout Feature Enable Address A15- 0 DQ15-0 5555 2AAA


Original
PDF W49L102 W49L102 12-volt
2000 - W49F102

Abstract: No abstract text available
Text: CE TOE OE VIH TOHZ TOLZ WE TCLZ T OH TCHZ High-Z High-Z DQ15-0 Data , WE TWPH TDS DQ15-0 Data Valid TDH CE Controlled Command Write Cycle Timing Diagram TAS TAH Address A15- 0 TCPH TCP CE TOES TOEH OE WE TDS DQ15-0 High Z Data , AA DQ15-0 5555 55 Address A0 Data-In CE OE T WPH TBP TWP WE Word 1 , Boot Block Lockout Feature Enable Address A15- 0 DQ15-0 5555 2AAA XXAA XX55 5555


Original
PDF W49F102 W49F102 12-volt
1999 - W29F102

Abstract: No abstract text available
Text: VIH T OHZ TOLZ WE TCLZ TOH TCHZ High-Z High-Z DQ15-0 Data Valid Data Valid , TDS DQ15-0 Data Valid TDH CE Controlled Command Write Cycle Timing Diagram TAS TAH Address A15- 0 TCPH TCP CE TOES TOEH OE WE TDS DQ15-0 High Z Data Valid TDH - 15 , Program Cycle Timing Diagram Word Program Cycle Address A15- 0 2AAA 5555 55 AA DQ15-0 , Enable Address A15- 0 DQ15-0 5555 2AAA XXAA XX55 5555 5555 XX80 XXAA 2AAA


Original
PDF W29F102 W29F102 12-volt
W49L102

Abstract: A1A15
Text: Diagram T RC Address A15- 0 T CE TOE OE V T TOLZ WE TCLZ DQ15-0 TOH TCHZ , TCH TOES T OEH OE TWP WE TWPH TDS DQ15-0 Data Valid TDH CE Controlled , TDS DQ15-0 High Z Data Valid TDH - 15 - Publication Release Date: June 1999 Revision , Program Cycle Address A15- 0 2AAA 5555 55 AA DQ15-0 5555 Address A0 Data-In , Feature Enable Address A15- 0 DQ15-0 5555 2AAA XXAA XX55 5555 5555 XX80 XXAA


Original
PDF W49L102 W49L102 12-volt A1A15
W29F102Q-55

Abstract: W29F102 MM 5555
Text: Diagram TRC Address A15- 0 TCE CE TOE OE WE VIH TOHZ TOLZ TCLZ DQ15-0 , CE TCS TCH TOES T OEH OE TWP WE TWPH TDS DQ15-0 Data Valid TDH CE , OE WE TDS DQ15-0 High Z Data Valid TDH - 15 - Publication Release Date: April , Word Program Cycle Address A15- 0 2AAA 5555 55 AA DQ15-0 5555 Address A0 , DQ15-0 5555 2AAA XXAA XX55 5555 5555 XX80 XXAA 2AAA XX55 5555 XX40


Original
PDF W29F102 W29F102 12-volt W29F102Q-55 MM 5555
1998 - Not Available

Abstract: No abstract text available
Text: reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3*2 Typ 3.3 0 Max 3.6 0 VCC+0.3*1 0.8 Units V V V V *1 : VCC+1.3V at pulse width 15ns which is measured at VCC , (Recommended operating conditions unless otherwise noted.) Parameter Input Leakage Current (Any input 0 VIN VCC+0.3V, all other pins not under test= 0 Volt) Output Leakage Current (Data out is disabled, 0V VOUT


Original
PDF KM416V4000C, KM416V4100C 16bit 4Mx16 400mil
2002 - W49F201

Abstract: ortec 142 w49f201t
Text: High-Z DQ15-0 Data Valid Data Valid TAA #WE Controlled Command Write Cycle Timing Diagram , DQ15-0 Data Valid TDH - 16 - W49F201 Timing Waveforms, continued #CE Controlled , #WE TDS DQ15-0 High Z Data Valid TDH Program Cycle Timing Diagram Word Program Cycle Address A16- 0 2AAA 5555 XXAA DQ15-0 5555 XX55 XXA0 Address Data-In #CE , Feature Enable Address A16- 0 DQ15-0 5555 2AAA XX55 XXAA 5555 5555 XX80 XXAA


Original
PDF W49F201 W49F201 12-volt ortec 142 w49f201t
2002 - W49L201

Abstract: No abstract text available
Text: TCS TCH TOES TOEH #OE TWP #WE TWPH TDS DQ15-0 Data Valid TDH - 16 - , Address A16- 0 TCPH TCP #CE TOES TOEH #OE #WE TDS DQ15-0 High Z Data Valid TDH Program Cycle Timing Diagram Word Program Cycle Address A16- 0 2AAA 5555 XXAA DQ15-0 , Timing Diagram Six-word code for Boot Block Lockout Feature Enable Address A16- 0 DQ15-0 5555 , Diagram Six-word code for 3.3V-only software chip erase Address A16- 0 DQ15-0 5555 2AAA


Original
PDF W49L201 W49L201 12-volt
2002 - W49F102

Abstract: No abstract text available
Text: TOHZ TOLZ #WE TCLZ T OH TCHZ High-Z High-Z DQ15-0 Data Valid Data Valid TAA , DQ15-0 Data Valid TDH #CE Controlled Command Write Cycle Timing Diagram TAS TAH Address A15- 0 TCPH TCP #CE TOES TOEH #OE #WE TDS DQ15-0 High Z Data Valid TDH - , DQ15-0 5555 XX55 Address XXA0 Data-In #CE #OE T WPH TBP TWP #WE Word 1 , Boot Block Lockout Feature Enable Address A15- 0 DQ15-0 5555 2AAA XXAA XX55 5555


Original
PDF W49F102 W49F102 12-volt
2004 - Not Available

Abstract: No abstract text available
Text: LBS#2 X X X VIH X X X X UBS#2 X X X VIH X X X X VIL VIL VIH VIL VIL VIH X DQ15-0 HIGH-Z HIGH-Z , UBS#, LBS# TBYLZS DQ15-0 DATA VALID 1269 F03.1 TOHS TBHZS TOES TOHZS TBYES TBYHZS Note: AMSS , TOLZ TAA TOHZ TCHZ HIGH-Z DATA VALID 1269 F06. 0 DQ15-0 HIGH-Z FIGURE 6: FLASH READ , TBP ADDRESS A19- 0 555 TAH TWP WE# TAS OE# TCH BEF# TCS DQ15-0 XXAA XX55 XXA0 TDS TDH DATA WORD (ADDR , TCPH 2AA 555 ADDR WE# TCS DQ15-0 1269 F08. 0 FIGURE 8: FLASH BEF# CONTROLLED PROGRAM CYCLE


Original
PDF SST34HF162C SST34HF164C SST34HF162C16Mb 48-lbga-LBK-10x12-500mic-2 48-BALL S71269-01-000
W29C101Q

Abstract: w29c101q-70 W29C101Q70 W29C101
Text: Address A15- 0 TCE CE TOE OE T OHZ VIH WE TOH DQ15-0 T CHZ High-Z High-Z Data , CE TCS TCH TOES T OEH OE WE TWP T WPH TDS DQ15-0 Data Valid TDH , DS DQ15-0 High Z Data Valid T DH Internal Write Starts Page Write Cycle Timing Diagram TWC Address A15- 0 DQ15-0 CE OE T WPH TBLC TWP WE Word 0 Word 1 Word 2 , A15- 0 2AAA 5555 DQ15-0 AAAA TWC Byte/page load cycle starts Three-byte sequence


Original
PDF W29C101 W29C101 12-volt W29C101Q w29c101q-70 W29C101Q70
2005 - Not Available

Abstract: No abstract text available
Text: normal memory access transactions: CFM/CFMN clock pins, RQ11. 0 request pins, and DQ15. 0 /DQN15. 0 data , T22 T23 CFM CFMN RQ11. 0 ACT WR a0 a1 t DQ15. 0 RCD-W DQN15. 0 WR a2 tCC D(a1 , T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 CFM CFMN RQ11. 0 DQ15. 0 DQN15. 0 , Calibration 0 (CC0) Register . 38 Current Calibration 1 (CC1) Register . 38 Read Only Memory 0 (ROM0) Register . 38 Read Only Memory 1 (ROM1) Register


Original
PDF EDX5116ABSE EDX5116ABSE M01E0107 E0643E40
2005 - DQ15d

Abstract: EDX5116ADSE-3C-E x5116 E1033E40 EDX5116ADSE T21at 8x4Mx16
Text: used for normal memory access transactions: CFM/CFMN clock pins, RQ11. 0 request pins, and DQ15. 0 /DQN15. 0 data pins. The "N" appended to a signal name denotes the complementary signal of a , T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 CFM CFMN RQ11. 0 ACT WR a0 a1 tCC tCWD D(a1) D(a2) Transaction a: WR T0 T1 T2 T3 RQ11. 0 DQ15. 0 DQN15. 0 , tCYCLE PRE a3 tWRP Pr t DQ15. 0 RCD-W DQN15. 0 WR a2 a0 = {Ba,Ra} tCYCLE Q(a2


Original
PDF EDX5116ADSE EDX5116ADSE M01E0706 E1033E40 DQ15d EDX5116ADSE-3C-E x5116 E1033E40 T21at 8x4Mx16
2005 - EDX5116ACSE-3C-E

Abstract: EDX5116ACSE X5116
Text: transactions: CFM/CFMN clock pins, RQ11. 0 request pins, and DQ15. 0 /DQN15. 0 data pins. The "N" appended to , CFMN RQ11. 0 ACT WR a0 a1 t DQ15. 0 RCD-W DQN15. 0 WR a2 tCC D(a1) tCWD tCYCLE , T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 CFM CFMN RQ11. 0 DQ15. 0 DQN15. 0 ACT a0 RD a1 , Calibration 0 (CC0) Register . 38 Current Calibration 1 (CC1) Register . 38 Read Only Memory 0 (ROM0) Register . 38 Read Only Memory 1 (ROM1) Register


Original
PDF EDX5116ACSE EDX5116ACSE M01E0107 E0881E20 EDX5116ACSE-3C-E X5116
2008 - HYB18H512322BF

Abstract: qimonda hyb18h5
Text: March 2008 IDRD51- 0 -A1F1C­32C XDR DRAM 512-Mbit XDR DRAM RoHS compliant Data Sheet Rev. 1.0 Data Sheet IDRD51- 0 -A1F1C 512-Mbit XDR DRAM IDRD51- 0 -A1F1C­32C Revision History: 2008-03 , -N57X-JNTM 2 Data Sheet IDRD51- 0 -A1F1C 512-Mbit XDR DRAM Table of Contents 1 2 2.1 2.2 3 4 5 6 6.1 , . . . . . . 72 72 73 73 Rev. 1.0, 2008-03 08312007-N57X-JNTM 3 Data Sheet IDRD51- 0 , . 43 IO Configuration (IOCFG) Register . 44 Current Calibration 0


Original
PDF IDRD51-0-A1F1C 512-Mbit 08312007-N57X-JNTM HYB18H512322BF qimonda hyb18h5
1999 - Equivalent of sw2 354

Abstract: sw2 354 8080 microprocessor Architecture Diagram cmos power TCP 8108 oasis F-173
Text: Hardware Mode Software Mode A9 DQ15-0 Address AIN AIN X DOUT DIN X AIN AIN Sector , # DQ15-0 TOHS DATA VALID TBHZS HIGH-Z DATA VALID 354 ILL F02.3 FIGURE 2A: SRAM READ CYCLE , 6 DATA VALID DQ15-0 354 ILL F03.3 7 FIGURE 3A: SRAM WRITE CYCLE TIMING DIAGRAM , # TOE OE# VIH TOHZ TOLZ WE# HIGH-Z DQ15-0 TBHZ TOH TBLZ HIGH-Z DATA , # 5 TCS DQ15-0 AAAA SW0 5555 SW1 A0A0 SW2 DATA 6 WORD (ADDR/DATA) 354 ILL


Original
PDF SST32LH802 Sec498404 Equivalent of sw2 354 sw2 354 8080 microprocessor Architecture Diagram cmos power TCP 8108 oasis F-173
W29C102

Abstract: w29c102p-70
Text: OE T OHZ VIH WE TOH DQ15-0 T CHZ High-Z High-Z Data Valid Data Valid TAA WE , OEH OE WE TWP TWPH TDS DQ15-0 Data Valid TDH Internal write starts - 13 - , OE WE T DS DQ15-0 High Z Data Valid T DH Internal Write Starts Page Write Cycle Timing Diagram TWC Address A15- 0 DQ15-0 CE OE T WPH TBLC TWP WE Word 0 Word 1 , A15- 0 2AAA 5555 DQ15-0 AAAA TWC Byte/page load cycle starts Three-byte sequence


Original
PDF W29C102 W29C102 12-volt w29c102p-70
1999 - K4F641611C-TC

Abstract: K4F661611C-TC
Text: reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Symbol Min , 0 0 0 V Input High Voltage VIH 2.6 - VCC+1.0 *1 V Input Low Voltage , Current (Any input 0VINVCC+0.5V, all other pins not under test= 0 Volt) II(L) -5 5 uA , [DQ0 - DQ15] C DQ - 7 pF AC CHARACTERISTICS ( 0 °CTA70°C, See note 1,2) Test condition , 30 ns 3,10 CAS to output in Low-Z tCLZ 0 ns 3 Output buffer turn-off delay


Original
PDF K4F661611C, K4F641611C 16bit 4Mx16 K4F661611C-TC 400mil K4F641611C-TC
1999 - W49L102

Abstract: No abstract text available
Text: WE TCLZ DQ15-0 TOH TCHZ High-Z High-Z Data Valid Data Valid TAA - 14 - , TAH Address A15- 0 CE TCS TCH TOES T OEH OE TWP WE TWPH TDS DQ15-0 , TCPH TCP CE TOES TOEH OE WE TDS DQ15-0 High Z Data Valid TDH - 15 - , Program Cycle Timing Diagram Word Program Cycle Address A15- 0 2AAA 5555 55 AA DQ15-0 , for Boot Block Lockout Feature Enable Address A15- 0 DQ15-0 5555 2AAA XXAA XX55


Original
PDF W49L102 W49L102 12-volt
322CL

Abstract: No abstract text available
Text: VlH VlL tcRP - tR C D - tre tr .p tRP · tR H C P - - tPC ' tRSH - V ih - p 0 CÄ5 , - W a V ih ECS3 VlL - V ih VlL W V ih V il tD § * t 0 H - W '


OCR Scan
PDF
2008 - IDRD51-0-A1F1C

Abstract: No abstract text available
Text: October 2008 IDRD51- 0 -A1F1C­[32C/40C] XDR DRAM 512-Mbit XDR DRAM RoHS compliant Internet Data Sheet Rev. 1.10 Internet Data Sheet IDRD51- 0 -A1F1C 512-Mbit XDR DRAM IDRD51- 0 , : techdoc@qimonda.com qag_techdoc_A4, 4.20, 2008-01-25 10292008-600R-IXL7 2 Internet Data Sheet IDRD51- 0 , 10292008-600R-IXL7 3 Internet Data Sheet IDRD51- 0 -A1F1C 512-Mbit XDR DRAM 12.3 12.4 13 13.1 13.2 13.3 , 81 83 83 85 85 87 88 Rev. 1.10, 2008-10 10292008-600R-IXL7 4 Internet Data Sheet IDRD51- 0


Original
PDF IDRD51-0-A1F1C­ 32C/40C] 512-Mbit IDRD51-0-A1F1C 10292008-600R-IXL7
1998 - KM416C4000B

Abstract: KM416C4100B
Text: OPERATING CONDITIONS (Voltage referenced to Vss, T A= 0 to 70°C) Parameter Symbol Min Typ Max Units Supply Voltage VCC 4.5 5.0 5.5 V Ground VSS 0 0 0 V Input , 0VINVCC+0.5V, all other pins not under test= 0 Volt) II(L) -5 5 uA Output Leakage Current (Data , CHARACTERISTICS ( 0 °CTA70°C, See note 1,2) Test condition : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V , 30 ns 3,10 CAS to output in Low-Z tCLZ 0 ns 3 Output buffer turn-off delay


Original
PDF KM416C4000B, KM416C4100B 16bit 4Mx16 400mil KM416C4000B KM416C4100B
1999 - Not Available

Abstract: No abstract text available
Text: T OHZ TCLZ High-Z DQ15-0 TOH Data Valid TAA TCHZ High-Z Data Valid - 14 - W29F102 , TCS TOES OE WE TAH TCH TOEH TWP TWPH TDS DQ15-0 Data Valid TDH CE Controlled Command Write Cycle Timing Diagram TAS TAH Address A15- 0 TCPH TCP CE TOES OE WE TDS DQ15-0 High Z , 5555 Address DQ15-0 AA 55 A0 Data-In CE OE TWP WE Word 0 T WPH TBP Word 1 , 2AAA 5555 5555 2AAA 5555 DQ15-0 CE XXAA XX55 XX80 XXAA XX55 XX40 OE WE TWP


Original
PDF W29F102 12-volt
Supplyframe Tracking Pixel