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gw 348

Abstract: DQ0-DQ63 6943-4 CY82C694 cy82 6943-3
Text: able (OE) must be deasserted HIGH before presenting data to the DQ0-DQ63 inputs. Doing so will threestate the output drivers. As a safety precaution, DQ0-DQ63 are automatically three stated whenever a , global write is con ducted, the data presented to the DQ0-DQ63 is written into the corresponding , , the Output En able (OE) must be deasserted HIGH before presenting data to the DQ0-DQ63 inputs. Doing so will threestate the output drivers. As a safety precaution, DQ0-DQ63 are automatically three


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PDF CY82C694 128KB CY82C691/692/693) CY82C694 riCY82C694 CY82C694-XXX 128Lead gw 348 DQ0-DQ63 6943-4 cy82 6943-3
Not Available

Abstract: No abstract text available
Text: . PIN DESCRIPTIONS DQ0-DQ63 (Data Bus, Tri-state, Input/Output, TTL) The DQ0-DQ63 lines convey data to and from the P2800. W hen the /E line is HIGH the DQ0-DQ63 lines are held at high impedance. The , / E at the beginning of an Read Cycle causes the data on the DQ0-DQ63 lines to be registered. The source or destination of data on the DQ0-DQ63 lines is determined by the states of the CT0-CT11 lines. The width of the input/output transactions on the DQ0-DQ63 lines is configurable as 16 bits, 32 bits


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PDF DS4468-2 P2800 64BIT P2800 OC-12 622MBits
Not Available

Abstract: No abstract text available
Text: Match 1 System Full Fig.3 Vertically cascaded P2800 system PIN DESCRIPTIONS DQ0-DQ63 (Data Bus, Tri-state, Input/Output, TTL) The DQ0-DQ63 lines convey data to and from the P2800. When the /E line is HIGH the DQ0-DQ63 lines are held at high impedance. The state of the AWline determines whether the , causes the data on the DQ0-DQ63 lines to be registered. The source or destination of data on the DQ0-DQ63 lines is determined by the states of the CT0-CT11 lines. The width of the input/output


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PDF P2800 64BIT P2800 OC-12 622MBits 16-bit
2000 - DTM60137

Abstract: No abstract text available
Text: *SA2 Vdd Function A0-A11 BA0-BA1 DQ0-DQ63 *CB0-CB7 CLK0 CKE0 CS0-CS3 RAS CAS WE , (CS0-CS3) DQM (DQM0-DQM7) DQ ( DQ0-DQ63 ) Document 06056, Revision A, 4/21/00 Symbol CADD CIN CCKE


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PDF DTM60137 128MB-16M 168-Pin PC100 DTM60137 400mil 168-pin
2000 - 64MB-8M

Abstract: DTM60136 DQ0-DQ63
Text: *SA1 *SA2 Vdd Function A0-A11 BA0-BA1 DQ0-DQ63 * CB0-CB7 CLK0 CKE0 CS0-CS3 RAS CAS WE , (CS0, CS2) DQM (DQM0-DQM7) DQ ( DQ0-DQ63 ) Document 06055, Revision A, 4/21/00 Symbol CADD CIN


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PDF DTM60136 64MB-8M 168-Pin PC100 DTM60136 400mil 168-pin DQ0-DQ63
2000 - DTM60160

Abstract: No abstract text available
Text: DQ0-DQ63 CB0-CB7 CLK0 CKE0 CS0-CS3 RAS CAS WE DQM0-DQM7 Vdd Vss *Vref REGE SDA SCL SA0-SA2 , ( DQ0-DQ63 ) CB (CB0-CB7) Document 06068, Revision B, 11/14/00 Symbol CADD CIN CCKE CCLK CCS CDQM


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PDF DTM60160 256MB-32M 168-Pin PC100 100MHz( DTM60160 16Mx16 256Mb) Cycles/64ms)
Not Available

Abstract: No abstract text available
Text: CSO A0-A10, BAO A0-A10, BAO DQ0-DQ15 DQ0-DQ63 SCL SDA 'cc V SS Decoupling , S0B1UV6412-(67/84/100/125)T-S Pin Name A0-A10/AP A0-A8 BAO DQ0-DQ63 CLKO RAS* CAS* CKEO Pin No , Input Capacitance (CS0*) C|3 13 PF 1 Input/Output Capacitance ( DQ0-DQ63 ) C |/o 12


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PDF V6412- S0B1UV6412- 144-pin, MB811171622A- 1Mx16 200mV. DGlfl745 SOB1UV6412- 144-pin 001fl74b
1996 - CY2254ASC-2

Abstract: CY27C010 CY82C691 CY82C692 CY82C694 cy82
Text: /pipelined cache Burst presented to the DQ0-DQ63 SRAM (BSRAM) designed to support a zero wait state , systems utilizing ei DQ0-DQ63 inputs. Doing so will threestate the output drivers. ther a linear or interleaved burst sequence. The interleaved burst As a safety precaution, DQ0-DQ63 are automatically three , presented to the DQ0-DQ63 is written into the asynchronous output enable (OE) provide for easy bank , DQ0-DQ63 inputs. Doing so will threestate the output drivers. As a safety precaution, DQ0-DQ63 are


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PDF CY82C694 128KB 128pin 66MHz CY2254ASC-2 CY27C010 CY82C691 CY82C692 CY82C694 cy82
Not Available

Abstract: No abstract text available
Text: , 69-72, 74-76, 86-89, 91-94, 97-101,103-105, 136-137,139-142, 144, 149,151,153-156,158-160 DQ0-DQ63 Input/ Output Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs to the addressed DRAM location , cycles, DQ0-DQ63 act as outputs for the addressed DRAM location. 79-82,163-166 PD1-PD8 41-42 , CURRENT (Q is disabled: 0V s V out s 3.6V) for each package input DQ0-DQ63 , PDQ0-PDQ7 OUTPUT , Capacitance: CASO - CAS7 Cl4 9 PF 2 Input/Output Capacitance: DQ0-DQ63 , PDQ0-PDQ7 Cio 15


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PDF MT24LD 168-pin, 400mW 048-cycle 128ms 0G1175b A0/B0-A10, 00117S7
MT16C

Abstract: No abstract text available
Text: ,97-101, 103-105, 136-137, 139-142, 144, 149,151,153-156,158-160 DQ0-DQ63 Input/ Output 79-82 , 1 OOllbGb } N W ■D A MODULE E RM PIN NUMBERS Data I/O: For WRITE cycles, DQ0-DQ63 act , CAS select (x64 mode only). For READ access cycles, DQ0-DQ63 act as outputs for the addressed DRAM , DQ0-DQ63 loz -10 10 HA VOH 2.4 PARAMETER/CONDITION INPUT LEAKAGE CURRENT Any input , Capacitance: CASO - CAS7 Cl4 9 PF 2 Input/Output Capacitance: DQ0-DQ63 Cio 10 PF 2


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PDF MT16D 168-pin, 200mW 048-cycle MT10O MT16C
1996 - CMOS 16-Bit Priority Encoder

Abstract: P2800 DS4440 content addressable memory Wired mae p2800s
Text: address on the DQ bus, and can be read by the processor. DQ0-DQ63 (Data Bus, Tri-state, Input/Output, TTL) The DQ0-DQ63 lines convey data to and from the P2800. When the /E line is HIGH the DQ0-DQ63 , DQ0-DQ63 lines to be registered. The source or destination of data on the DQ0-DQ63 lines is determined by , HIGH the DQ0-DQ63 lines are forced to the high-impedance state, the device is disabled, and static , input selects the direction of data transfer on the DQ0-DQ63 lines during a cycle. It is used in


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PDF P2800 DS4468-1 64BIT P2800 OC-12 622MBits CMOS 16-Bit Priority Encoder DS4440 content addressable memory Wired mae p2800s
Not Available

Abstract: No abstract text available
Text: DQ48-DQ63 DQ32-DQ47 CB0-CB3 4M x 16 DRAM DQ0-DQ63 , C 0-C B 7 SERIAL PD EEPROM S C L , DQ0-DQ63 WEO*, WE2* RASO*, RAS2* SDA OEO*, OE2* CAS0*~CAS7* SA0-SA2 SCL Vcc Vsg NC Pin No , *) C I5 26 PF 1 Input/Output Capacitance ( DQ0-DQ63 , CB0 - CB7) C|/0 12 PF 1,2


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PDF 32MByte EDC4UV724 32-megabyte 168-pins, MB81V1 168-pin u111111111 111111tttttttti
W9V332647HA-333

Abstract: W9V332647HA 32X64 079R 32MX64 PC133-333 tt12ns
Text: Inputs DQ50 BA0, BA1 DQ0-DQ63 Data Inputs/Outputs 13 15 DQ4 DQ5 14 16 DQ36 DQ37 , ( DQ0-DQ63 ) I/O capacitance (SDA) CI1 43 pF CI2 CI3 CI4 CI5 CIO1 CIO2 20 43 10 8 10


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PDF W9V332647HA-333 32MX64 144-pin PC133 32MX8 400-mil TSOPII-54 PC133-333 133MHz W9V332647HA-333 W9V332647HA 32X64 079R tt12ns
wintec

Abstract: 079R PC-100
Text: DQ49 A0-A12 Address Inputs DQ50 BA0, BA1 DQ0-DQ63 Data Inputs/Outputs 13 15 DQ4 , capacitance (DQMB0-DQMB7) I/O capacitance ( DQ0-DQ63 ) I/O capacitance (SDA) CI1 23 pF CI2 CI3


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PDF W9R308647PA-222 144-pin PC100 400-mil TSOPII-54 PC-100 100MHz W9R308647PA-222 wintec 079R
2004 - Not Available

Abstract: No abstract text available
Text: DQ4 140 DQM8 DQ0-DQ63 Data Input/Output 3 VSS 49 CB2 95 DQ5 141 , /Output capacitance ( DQ0-DQ63 )(DQS) COUT 15 pF Data Input/Output Capacitance (CB0-CB7) COUT


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PDF WED3EG7218S-D3 128MB- 16Mx72 WED3DG7218S 128Mb 16Mx8 WED3DG7218S262D3 WED3DG7218S265D3
Not Available

Abstract: No abstract text available
Text: DQ0-DQ63 1 2 Clock Input Clock Enable Input RAS 144 Read/Write Enable CKE0, CKE1 143 , DQ0-DQ63 BDQ0-BDQ63 Document Part Number 61000-00968-105 August 2001 Page 5 SimpleTech


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PDF SL64G6D8M4G-B10xV 144-Pin PC100) SL64G6D8M4G-B10xV 54-pin 400-mil PC100/Intel A0-A10/AP, BDQ48-55
IC SDA 2001

Abstract: SL64U8S128M8G-A75AV
Text: A0-A10/AP, A11, A12 Address Inputs BA0, BA1 Select Bank DQ0-DQ63 Data In/Out WE Write , BDQ0-BDQ63 4 SDRAMS* 10 CLK3 10 DQ0-DQ63 CLK2 4 SDRAMS* * Note: Each Double-Die SDRAM is


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PDF SL64U8S128M8G-A75AV 168-Pin PC133) SL64U8S128M8G-A75AV PC133 cycles/64ms U0-U15 A0-A10/AP, BDQ24 IC SDA 2001
pin diagram for IC 7476

Abstract: INTERNAL DIAGRAM OF IC 7476
Text: clocked by RAS and CAS. Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs to the addressed DRAM location , cycles, DQ0-DQ63 act as outputs for the addressed DRAM location. Presence-Detect: These pins are read by , , 103-105, 136-137, 139-142, 144, 149,151,153-156,158-160 79-82, 163-166 A0-A9, BO DQ0-DQ63 Buffered , ,2 RASO,2 DQ0-DQ63 4.5 3.5 -0.5 -2 -16 -10 2.4 5.5 Vcc+0.5 0.8 2 16 10 V V V |xA I^A HA V , Capacitance: DQ0-DQ63 Cm Cl2 Cl3 Cl4 9 9 40 9 10 pF PF PF PF PF 2 2 2 2 2 Cio ELECTRICAL C


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PDF MT16D 168-pin, 600mW 024-cycle 128ms 168-Pi pin diagram for IC 7476 INTERNAL DIAGRAM OF IC 7476
tc 97101

Abstract: No abstract text available
Text: and clocked by RAS and CAS. Data I/O: For W RITE cycles, DQ0-DQ63 act as inputs to the addressed DRAM , access cycles, DQ0-DQ63 act as outputs for the addressed DRAM location. Presence-Detect: These pins are , , 103-105, 136-137, 139-142, 144, 149,151,153-156,158-160 79-82, 163-166 A0-A10, B0 DQ0-DQ63 Buffered , Voltage ( I o u t = 2mA) DQ0-DQ63 SYMBOL Vcc VlH VlL In Il2 lo z MIN 3.0 2.0 -1.0 -2 -16 -10 2.4 , : RASO, RAS2 Input Capacitance: CASO - CAS7 Input/Output Capacitance: DQ0-DQ63 SYMBOL Cn Cl2 Cl3 Cl4


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PDF MT16LD 168-pin, 048-cycle 128ms DE-24) T16LD MT16ID A0-A11 tc 97101
2001 - pc133 SDRAM DIMM

Abstract: DTM60177 DTM60178
Text: Function A0-A12 BA0-BA1 DQ0-DQ63 CB0-CB7 CLK0-CLK3 CKE0 CS0-CS3 RAS CAS WE DQM0-DQM7 Vdd Vss , (DQM0-DQM7) DQ ( DQ0-DQ63 ) CB (CB0-CB7) Symbol C ADD CIN CCKE CCLK CCS C DQM COUT1 COUT2


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PDF DTM60177, 512MB-64M 168-Pin PC100/PC133 DTM60177: DTM60178: PC100 PC133 PC100 100MHz pc133 SDRAM DIMM DTM60177 DTM60178
2004 - Not Available

Abstract: No abstract text available
Text: *ADVANCED PIN NAMES A0 ­ A11 BA0-BA1 DQ0-DQ63 DQS0-DQS7 CK0, CK1, CK2 CK0#, CK1#, CK2# CKE0 CS0# RAS , Capacitance (BA0-BA1) Data input/output capacitance ( DQ0-DQ63 )(DQS) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7


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PDF WED3EG6418S-D3 128MB- 16Mx64 WED3EG6418S262D3 WED3EG6418S265D3 WED3EG6418S202D3 133MHz/266Mbps 100MHz/200Mbps
Not Available

Abstract: No abstract text available
Text: DQ0-DQ63 O.OIjiF - Vss upling capacitors to all devices to change without notice.) Notes , DQ0-DQ63 CLK0-CLK3 RAS* CAS* CKEO DQMB0-DQMB7 Addresses Bank Select Address Data Inputs/Outputs Clock


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PDF SDC8UV6484- 64MByte V6484- 64-megabtye 168-pin, MB81164842A- 67/84/l 64MByte 125MHz)
079R

Abstract: PC-100 PC133-333 ZD064M26H
Text: 168 VCC V. PIN NAMES: SYMBO L DESCRIPTION A0-A11 Address Inputs BA0, BA1 DQ0-DQ63 , ) Input capacitance (DQMB0-DQMB7) I/O capacitance ( DQ0-DQ63 ) Input capacitance (SA0-SA2, SCL) I/O


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PDF W9D308647PA-333 8Mx64 168-pin PC133-333 8Mx16 400-mil TSOPII-54 133MHz 12-row, 11-column, 079R PC-100 ZD064M26H
079R

Abstract: 32mx8 sdram 070d 32X64 ZE256M58IA 32MX64 WINTEC INDUSTRIES wintec
Text: DESCRIPTION DQ49 A0-A12 Address Inputs DQ50 BA0, BA1 DQ0-DQ63 Data Inputs/Outputs 13 15 , capacitance (SCL) Input capacitance (DQMB0-DQMB7) I/O capacitance ( DQ0-DQ63 ) I/O capacitance (SDA) CI1


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PDF W9R332647HA-222 32MX64 144-pin PC100 32MX8 400-mil TSOPII-54 W9R332647HA-222 D9R332647HA-222 079R 32mx8 sdram 070d 32X64 ZE256M58IA WINTEC INDUSTRIES wintec
Not Available

Abstract: No abstract text available
Text: Function A0-A10/AP, A11 BA0, BA1 Address Inputs DQ0-DQ63 Data In/Out WE Write Enable , DQ0-DQ63 BDQ0-BDQ63 4 SDRAMS 10 CLK3 Document Part Number 61000-01229-102 June 2001 Page 5


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PDF SL64U8E16M4G-A10xV 128MB) PC100) PC100 cycles/64ms SL64U8E16M4G-A10xV BDQ53 BDQ54 BDQ55 BDQ24
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