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SSM009W6DQ (1589812-2) TE Connectivity (1589812-2) SSM009W6DQ = Thru-Hole
STL025W6DQ (1589809-8) TE Connectivity (1589809-8) STL025W6DQ = Thru-Hole
STM037W61DQ (1589942-1) TE Connectivity (1589942-1) STM037W61DQ = Thru-Hole
STG015M6DQ (1589487-2) TE Connectivity (1589487-2) STG015M6DQ = THRU-HOLE

DQ0-DQ15 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2006 - M65KG256AB

Abstract: A476
Text: . . . . . . . . . . . . . . . . . . . . 9 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) . . . . . . . . . , . M65KG256AB Figure 1. 1 Summary description Logic Diagram VDD VDDQ 13 16 A0-A12 DQ0-DQ15 2 , DQ0-DQ15 Data Inputs/Outputs K, K Clock Inputs KE Clock Enable Input E Chip Enable , , CAS, and W must be High, VIH. 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) The Data Inputs/Outputs output , except UDQM/LDQM, UDQS/LDQS and DQ0-DQ15 are referred to the cross point of K rising edge and K falling


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PDF M65KG256AB 256Mbit 133MHz 256Mbit 266Mbit/s 133MHz M65KG256AB A476
2006 - M65KG256AF

Abstract: No abstract text available
Text: Data Inputs/Outputs ( DQ0-DQ15 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 , M65KG256AF Figure 1. Summary description Logic Diagram VDD VDDQ 13 16 A0-A12 DQ0-DQ15 2 , DQ0-DQ15 Data Inputs/Outputs K, K Clock Inputs KE Clock Enable Input E Chip Enable , , CAS, and W must be High, VIH. 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) The Data Inputs/Outputs output , except UDQM/LDQM, UDQS/LDQS and DQ0-DQ15 are referred to the cross point of K rising edge and K falling


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PDF M65KG256AF 256Mbit 133MHz, 256Mbit 266Mbit/s 133MHz M65KG256AF
2006 - M65KG512AB

Abstract: No abstract text available
Text: . . . . . . . . . . . . . . . . . . . . 9 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) . . . . . . . . . , 16 A0-A12 DQ0-DQ15 2 BA0-BA1 E UDQS RAS LDQS CAS M65KG512AB K K KE W , Bank Select Inputs DQ0-DQ15 Data Inputs/Outputs K, K Clock Inputs KE Clock Enable , ( DQ0-DQ15 ) The Data Inputs/Outputs output the data stored at the selected address during a Read operation , , K and K, are the master clock inputs. All input signals except UDQM/LDQM, UDQS/LDQS and DQ0-DQ15


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PDF M65KG512AB 512Mbit 512Mbit 266Mbit/s 133MHz M65KG512AB
2007 - JESD97

Abstract: FBGA71 rl3410 M69AB048 E1-57 X 30 M69KB048BD
Text: Figure 1. Description Logic diagram VCC 21 16 A0-A20 DQ0-DQ15 W WAIT E1 E2 G , Inputs DQ0-DQ15 Data Inputs/Outputs E1 Chip Enable Input (Active Low) E2 Chip Enable , Address Valid A0-A20 Address Valid L E1 G High W WAIT DQ0-DQ15 Hi-Z Hi-Z , Hi-Z DQ0-DQ15 DIN1 DIN2 DINBL ai09409c 1. The above diagram is an example of , K A0-A20 Address Valid L E1 G Read Latency(CR RL bits) DQ0-DQ15 Hi Z DOUT1


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PDF M69KB048BD M69AB048BD FBGA71 JESD97 FBGA71 rl3410 M69AB048 E1-57 X 30 M69KB048BD
2007 - FBGA71

Abstract: VIH42 M69AB048 M69KB048BD
Text: UB LB K L M69AB048BD M69KB048BD 16 DQ0-DQ15 WAIT VSS AI11394 Table 1. Signal names , input Latch Enable input Wait output Core supply voltage Ground A0-A20 DQ0-DQ15 E1 E2 G W UB LB K L , Address Valid L E1 G High W Hi-Z WAIT Hi-Z DQ0-DQ15 Hi-Z Hi-Z DOUT1 DOUTBL , A0-A20 VALID VALID L E1 High G W Hi-Z Hi-Z WAIT DQ0-DQ15 DIN1 DIN2 DINBL , Latency(CR RL bits) DQ0-DQ15 Hi Z DOUT1 DOUT2 DOUTBL Hi Z Burst Length (CR BL bits) WAIT Hi Z AI08940d


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PDF M69KB048BD M69AB048BD FBGA71 VIH42 M69AB048
2006 - Not Available

Abstract: No abstract text available
Text: Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data Inputs/Outputs ( DQ0-DQ15 ) . , E RAS CAS K K KE W UDQM LDQM M65KG256AF UDQS LDQS 16 DQ0-DQ15 Summary description VSS VSSQ AI12484 Table 1. A0-A12 BA0-BA1 DQ0-DQ15 K, K KE E W RAS CAS UDQM LDQM UDQS LDQS VDD VDDQ VSS VSSQ , Data Inputs/Outputs ( DQ0-DQ15 ) The Data Inputs/Outputs output the data stored at the selected address , signals, K and K, are the master clock inputs. All input signals except UDQM/LDQM, UDQS/LDQS and DQ0-DQ15


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PDF M65KG256AF 256Mbit 133MHz, 256Mbit 266Mbit/s 133MHz M65KG256AF8W6T M65KG256AF
DQ0-DQ15

Abstract: 28F016SA E28F016SV-070 80 pin flash DQ16-DQ31
Text: OE WE A1-A20 OE CE0 CE0 DQ16-DQ31 DQ0-DQ15 WE2 WE0 CE1 WE A1-A20 OE , DQ0-DQ15 WE2 WE0 CE2 WE A1-A20 OE WE A1-A20 OE To all flash memory components , DQ16-DQ31 DQ0-DQ15 Document Part Number 61000-00924-101 August 1998 5. CE1 and 3/5 of all flash , DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16-DQ31 DQ0-DQ15 SL29160-70(T/G)A8SI 80-PIN FLASH


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PDF SL29160-70 V/12V 56-pin 80-pin E28F016SVry A1-A20 DQ16-DQ31 DQ0-DQ15 DQ0-DQ15 28F016SA E28F016SV-070 80 pin flash DQ16-DQ31
2007 - M65KG512AB

Abstract: No abstract text available
Text: . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) . . . . , DQ0-DQ15 2 BA0-BA1 E UDQS RAS LDQS CAS M65KG512AB K K KE W UDQM LDQM VSS , DQ0-DQ15 Data Inputs/Outputs K, K Clock Inputs KE Clock Enable Input E Chip Enable , , VIH. 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) The Data Inputs/Outputs output the data stored at the , /LDQM, UDQS/LDQS and DQ0-DQ15 are referred to the cross point of K rising edge and K falling edge


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PDF M65KG512AB 512Mbit 512Mbit M65KG512AB
2006 - Not Available

Abstract: No abstract text available
Text: Data Inputs/Outputs ( DQ0-DQ15 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip , VDD VDDQ 13 A0-A12 2 BA0-BA1 E RAS CAS K K KE W UDQM LDQM M65KG512AB UDQS LDQS 16 DQ0-DQ15 Summary description VSS VSSQ AI12443 Table 1. A0-A12 BA0-BA1 DQ0-DQ15 K, K KE E W RAS CAS UDQM LDQM UDQS , be High, VIH. 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) The Data Inputs/Outputs output the data , , UDQS/LDQS and DQ0-DQ15 are referred to the cross point of K rising edge and K falling edge. During read


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PDF M65KG512AB 512Mbit 512Mbit 332Mbit/s 133MHz 166MHz
2007 - Not Available

Abstract: No abstract text available
Text: . . . . . . . . . . . . . . . . . . . . . . 9 Data Inputs/Outputs ( DQ0-DQ15 ) . . . . . . . . . . . . , E RAS CAS K K KE W UDQM LDQM M65KG512AA UDQS LDQS 16 DQ0-DQ15 Description VSS VSSQ AI13128 Table 1. A0-A12 BA0-BA1 DQ0-DQ15 K, K KE E W RAS CAS UDQM LDQM UDQS LDQS VDD VDDQ VSS VSSQ Signal , ( DQ0-DQ15 ) The Data Inputs/Outputs output the data stored at the selected address during a Read operation , the master clock inputs. All input signals except UDQM/LDQM, UDQS/LDQS and DQ0-DQ15 are referred to


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PDF M65KG512AA 512Mbit 512Mbit M65KG512AA8W9 M65KG512AA
2007 - Not Available

Abstract: No abstract text available
Text: . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) . . . . , . Description Logic diagram VDD VDDQ 13 16 A0-A12 DQ0-DQ15 2 BA0-BA1 E UDQS RAS LDQS , A0-A12 Address Inputs BA0-BA1 Bank Select Inputs DQ0-DQ15 Data Inputs/Outputs K, K , Data Inputs/Outputs ( DQ0-DQ15 ) The Data Inputs/Outputs output the data stored at the selected address , signals, K and K, are the master clock inputs. All input signals except UDQM/LDQM, UDQS/LDQS and DQ0-DQ15


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PDF M65KG512AA 512Mbit 512Mbit
2006 - M65KA128AE

Abstract: No abstract text available
Text: Data Inputs/Outputs ( DQ0-DQ15 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 , . M65KA128AE Figure 1. Summary description Logic diagram VDD VDDQ 12 16 A0-A11 DQ0-DQ15 2 , names A0-A11 Address Inputs BA0-BA1 Bank Select Inputs DQ0-DQ15 Data Inputs/Outputs , rising edge of the clock signal, K. 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) The Data Inputs/Outputs , 2.0 4.5 pF A0-A11, BA0, BA1, KE, E, RAS, CAS, W, UDQM, LDQM 2.0 4.5 pF DQ0-DQ15


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PDF M65KA128AE 133MHz M65KA128AE
2006 - M65KA128AE

Abstract: No abstract text available
Text: Data Inputs/Outputs ( DQ0-DQ15 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 , A0-A11 DQ0-DQ15 2 BA0-BA1 E RAS UDQM M65KA128AE LDQM CAS K KE W VSS Table 1 , DQ0-DQ15 Data Inputs/Outputs K Clock Input KE Clock Enable Input E Chip Select Input , the rising edge of the clock signal, K. 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) The Data Inputs , 2.0 4.5 pF A0-A11, BA0, BA1, KE, E, RAS, CAS, W, UDQM, LDQM 2.0 4.5 pF DQ0-DQ15


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PDF M65KA128AE 128Mbit 128Mbit 133MHz M65KA128AE
2008 - Not Available

Abstract: No abstract text available
Text: ( DQ0-DQ15 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Select (E) . . . . . . . . . , UDQM 16 DQ0-DQ15 VSS VSSQ AI12170 Table 1. A0-A11 BA0-BA1 DQ0-DQ15 K KE E W RAS CAS UDQM , Data Inputs/Outputs ( DQ0-DQ15 ) The Data Inputs/Outputs output the data stored at the selected address , ) Parameter Signal Min. K Input Capacitance A0-A11, BA0, BA1, KE, E, RAS, CAS, W, UDQM, LDQM DQ0-DQ15 2.0 2.0 , Column a in Bank A, DAan= Data n written to Column a in Bank A. 28/53 DQ0-DQ15 Address LDQM


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PDF M65KA128AE 133MHz
MT46V16M16

Abstract: DQ0-DQ15 62-ball DDR333 ISDD128M4PBB MT46V32M8 MT46V64M4 PC2700 A0-A12
Text: DM DQS DQ0-DQ15 DQ0-DQ15 DQ0-DQ15 Email: BGAstack@irvine-sensors.com Internet


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PDF ISDD128M4PBB ISDD64M8PBC ISDD32M16PBD 512Mb 512Mbit 256Mb A0-A12 MT46V16M16 DQ0-DQ15 62-ball DDR333 ISDD128M4PBB MT46V32M8 MT46V64M4 PC2700 A0-A12
2005 - Not Available

Abstract: No abstract text available
Text: . . . 9 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) . . . . . . . . . . . . . . . . . . . . . . . . . . , Logic Diagram VDD VDDQ 12 16 A0-A11 DQ0-DQ15 2 BA0-BA1 E RAS M65KA128AL CAS K KE , BA0-BA1 Bank Select Inputs DQ0-DQ15 Data Inputs/Outputs K Clock Input KE Clock Enable , ( DQ0-DQ15 ) The Data Inputs/Outputs output the data stored at the selected address during a Read operation , High until the Precharge command is issued to make sure that DQ0-DQ15 remain high impedance. 4


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PDF M65KA128AL 128Mbit 128Mbit 104MHz
2007 - M65KA512AB

Abstract: No abstract text available
Text: . . . . . . . 9 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) . . . . . . . . . . . . . . . . . . . . . . , command. M65KA512AB Figure 1. Description Logic diagram VDD VDDQ 13 16 A0-A12 DQ0-DQ15 , Select Inputs Inputs DQ0-DQ15 Data Inputs/Outputs Input/Outputs K Clock Input Input , Data Inputs/Outputs ( DQ0-DQ15 ) The Data Inputs/Outputs output the data stored at the selected address , , W, UDQM, LDQM 2.0 4.5 pF DQ0-DQ15 3.5 6.0 pF CI1 Input capacitance CI2


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PDF M65KA512AB 512Mbit M65KA512AB
2006 - code diode KE

Abstract: M65KA256AL
Text: . . . . . . . . . . . . . . . . . . . . 9 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) . . . . . . . . . , description Logic Diagram VDD VDDQ 13 16 A0-A12 DQ0-DQ15 2 BA0-BA1 E RAS UDQM M65KA256AL , BA0-BA1 Bank Select Inputs DQ0-DQ15 Data Inputs/Outputs K Clock Input KE Clock Enable , inputs are latched on the rising edge of the clock signal, K. 2.3 Data Inputs/Outputs ( DQ0-DQ15 , DQ0-DQ15 4 5 pF CI1 Input Capacitance CI2 CIO Data I/O Capacitance 1. TJ = 25°C, f =


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PDF M65KA256AL 256Mbit 105MHz 256Mbit 105MHz code diode KE M65KA256AL
2006 - Not Available

Abstract: No abstract text available
Text: ( DQ0-DQ15 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Enable (E) . . . . . . . . . , M65KA512AB LDQM UDQM 16 DQ0-DQ15 VSS VSSQ AI12117 Table 1. A0-A12 BA0-BA1 DQ0-DQ15 K KE E W RAS , signal, K. 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) The Data Inputs/Outputs output the data stored at , K Input capacitance A0-A11, BA0, BA1, KE, E, RAS, CAS, W, UDQM, LDQM DQ0-DQ15 2.0 2.0 3.5 Max 4.5 , , DAan= Data n written to Column a in Bank A. 30/55 DQ0-DQ15 Address LDQM/ UDQM RAS CAS


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PDF M65KA512AB 512Mbit 133MHz 512Mbit 133MHz
1995 - M28F102

Abstract: PLCC44
Text: 16 A0-A15 W DQ0-DQ15 M28F102 E Table 1. Signal Names A0 - A15 DQ0 - DQ15 Data , DQ0-DQ15 (2) X 2 Write X xx90h 0000h 0020h 0001h 0050h X xx20h Read , DQ0-DQ15 (2) Write 1 A0-A15 Read Read Operation Setup Erase/ 2 Write X , tGHQZ tGLQX DQ0-DQ15 DATA OUT AI00630 Figure 6. Read Command Waveforms VPP tVPHEL , W tWLWH tGLQV tDVWH DQ0-DQ15 tWHDX COMMAND READ SET-UP DATA OUT READ AI00631


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PDF M28F102 PLCC44 TSOP40 PLCC44 M28F102
M65KA512AB

Abstract: No abstract text available
Text: 9 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . M65KA512AB Figure 1. 1 Summary description Logic Diagram VDD VDDQ 13 16 A0-A12 DQ0-DQ15 , Signal Names A0-A12 Address Inputs BA0-BA1 Bank Select Inputs DQ0-DQ15 Data Inputs , signal, K. 2.3 Data Inputs/Outputs ( DQ0-DQ15 ) The Data Inputs/Outputs output the data stored at , A0-A11, BA0, BA1, KE, E, RAS, CAS, W, UDQM, LDQM 2.0 4.5 pF DQ0-DQ15 3.5 6.0 pF


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PDF M65KA512AB 512Mbit 133MHz 512Mbit 133MHz M65KA512AB
2005 - Not Available

Abstract: No abstract text available
Text: . Logic Diagram VCC VCCQ 22 16 A0-A21 DQ0-DQ15 W WAIT E CR G M69KB096AA UB LB K L VSS VSSQ AI10584b Table 1. Signal Names Address Inputs DQ0-DQ15 Data , A0-A21 Address Valid ADV Latency Code 2 (3 clocks) E G W WAIT Hi Z DQ0-DQ15 Hi , Address Valid L E G W LB/UB WAIT Hi Z DQ0-DQ15 Hi Z DQ0 DQ1 DQ2 DQ3 , LB/UB WAIT Hi Z DQ0-DQ15 Hi Z DQ0 Additional WAIT states inserted to allow Refresh


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PDF M69KB096AA 80MHz 66MHz, 80MHz
2004 - tpd1221

Abstract: No abstract text available
Text: pitch) package. Figure 2. Logic Diagram Table 1. Signal Names A0-A18 DQ0-DQ15 Address Inputs Data , A0-A18 W E1 E2 G UB LB M68AW512D 16 DQ0-DQ15 E2 G W UB LB VCC VSS NC DU VSS AI04800b 4/21 , Disabled The Output Enable signal, G, provides high-speed tri-state control of DQ0-DQ15 , allowing fast read , . In this mode, LB and UB are Don't care and DQ0-DQ15 are high impedance. Read Mode When Chip Select , tGLQV G tGLQX DQ0-DQ15 tBLQV UB, LB tBLQX AI05981b tGHQZ VALID tBHQZ Note: Write Enable (W) =


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PDF M68AW512D TFBGA48 tpd1221
1998 - M28F102

Abstract: PLCC44
Text: Supply VCC M28F102 Write Enable VPP DQ0-DQ15 Chip Enable G 16 Data Inputs , Cycles Operation A0-A15 2nd Cycle DQ0-DQ15 (2) X 2 Write X xx90h 0020h , Signature 0000h Write Write Read Write 1 A0-A15 Read Read DQ0-DQ15 (2 , tAXQX E tELQV tEHQZ tELQX G tGLQV tGHQZ tGLQX DQ0-DQ15 DATA OUT AI00630 , tELQV tEHQZ G tGHWL tWHGL tGHQZ W tWLWH tGLQV tDVWH DQ0-DQ15 tWHDX COMMAND


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PDF M28F102 0020h 0050h M28F102 PLCC44
2004 - J-STD-020B

Abstract: M36W0R5020B0 M36W0R5020T0 m36w0r5
Text: . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Input/Output ( DQ0-DQ15 ). . . . . . . , DQ0-DQ15 Common Data Input/Output VDDF Flash Memory Power Supply VDDQ Common Flash and SRAM , VPPF VDDS VDDF 21 16 A0-A20 DQ0-DQ15 EF GF WPF WAITF E1S, E2S Chip Enable , E2S) and the Write Enable signal (WS). Data Input/Output ( DQ0-DQ15 ). The Data I/O output the data , WAITF LF KF RPF A0-A17 WPF DQ0-DQ15 VDDS E1S GS WS 4Mbit SRAM E2S UBS LBS


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PDF M36W0R5020T0 M36W0R5020B0 256Kb 8814h 8815h J-STD-020B M36W0R5020B0 M36W0R5020T0 m36w0r5
Supplyframe Tracking Pixel