The Datasheet Archive

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Part Manufacturer Description Datasheet Download Buy Part
5962-9054302MQA Intersil Corporation 4 CHANNEL(S), 8MHz, DMA CONTROLLER, CDIP40, CERDIP-40
CS82C37A Intersil Corporation 4 CHANNEL(S), 8MHz, DMA CONTROLLER, PQCC44
CP82C37A-5 Intersil Corporation 4 CHANNEL(S), 5MHz, DMA CONTROLLER, PDIP40, PLASTIC, DIP-40
CS82C37A-1296 Intersil Corporation 4 CHANNEL(S), 12.5MHz, DMA CONTROLLER, PQCC44, PLASTIC, MO-047AC, LCC-44
MD82C37A/B Intersil Corporation 4 CHANNEL(S), 8MHz, DMA CONTROLLER, CDIP40, CERAMIC, DIP-40
CS82C37AZ Intersil Corporation 4 CHANNEL(S), 8MHz, DMA CONTROLLER, PQCC44, ROHS COMPLIANT, MO-047AC, PLASTIC, LCC-44
SF Impression Pixel

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DMA66014 Unknown Bristol Electronics 5 - -
FDMA6676PZ ON Semiconductor Avnet - €0.41 €0.26
FDMA6676PZ ON Semiconductor Avnet - $0.28 $0.26
FDMA6676PZ ON Semiconductor Avnet - $0.43 $0.35
FDMA6676PZ ON Semiconductor Future Electronics - $0.27 $0.27
FDMA6676PZ ON Semiconductor element14 Asia-Pacific - $1.17 $0.52
FDMA6676PZ ON Semiconductor Farnell element14 - £0.80 £0.40

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DMA-66 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
ADSP210x

Abstract: LQFP100 16KX16 ADSP-210x 68-PGA 1kx16 ADSP-2186M
Text: ADSP2101 40 50 66 80 100 66 80 100 66 80 100 10 13 17 20 25 17 20 25 17 20 25 10 10 20 14 20 10 13 17 20 17 , ADSP2111 66 ADSP2111 80 ADSP2115 66 ADSP2115 80 ADSP2115 100 ADSP2115 66 ADSP2115 80 ADSP2115 100 ADSP2115 , ADSP2109 80 ADSP2109 55 ADSP2161 66 ADSP2162 40 ADSP2163 66 ADSP2163 100 ADSP2164 40 ADSP2165 66 ADSP2165 80 ADSP2166 66 LARGE ON CHIP MEMORY BS BS BST BST BS BST $114.06 $131.38 $16.25 $16.59 $19.07


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PDF ADSP210x ADSP2101 LQFP100 16KX16 ADSP-210x 68-PGA 1kx16 ADSP-2186M
1998 - 1kx16

Abstract: 2Kx16 8Kx16 16KX16 ADSP2105 ADSP2103 ADSP2111 ADSP2115 ADSP2171 ADSP2173
Text: 12.5 ADSP2101 66 16.67 ADSP2101 80 20 ADSP2101 100 25 ADSP2103 80 20 ADSP2104 80 20 , 66 16.67 ADSP2111 80 20 ADSP2115 80 20 ADSP2115 66 16.67 ADSP2115 100 25 ADSP2171 133 , 66 16.67 ADSP2162 40 10.24 ADSP2163 66 16.67 ADSP2163 100 25 ADSP2164 40 10.24 ADSP2165 66 16.67 ADSP2165 80 20 ADSP2166 66 16.67 LARGE ON CHIP MEMORY ADSP2181 115 28.8 ADSP2181 , 40 ADSP2187L 160 40 ADSP2187L 210 52 ADSP2189L 260 66 11/10/98 8:56 AM 100 80 60


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PDF ADSP2101 ADSP2103 ADSP2104 ADSP2104L ADSP2105 1kx16 2Kx16 8Kx16 16KX16 ADSP2105 ADSP2103 ADSP2111 ADSP2115 ADSP2171 ADSP2173
1999 - ISP2200A

Abstract: ISP2100A QLOGIC isp
Text: QLogic Corporation ISP2200A/33 and ISP2200A/ 66 Intelligent Fibre Channel Processors Data Sheet Features s Available in two speed grades (collectively referred to as ISP2200A): 66 -MHz, 64-bit PCI host bus interface (ISP2200A/ 66 ) 33-MHz, 64-bit PCI host bus interface (ISP2200A/33) s , ISP2100A/33. The ISP2200A/ 66 is pin compatible with the ISP2100A/ 66 . The ISP2200A is a fully autonomous , -BIT, 33- OR 66 -MHZ BUS 10 TRANSMIT DATA DMA CHANNEL PCI CONTROL COMMAND DMA CHANNEL


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PDF ISP2200A/33 ISP2200A/66 ISP2200A) 66-MHz, 64-bit ISP2200A/66) 33-MHz, ISP2200A/33) ISP2200A ISP2100A QLOGIC isp
1997 - BT-308

Abstract: ADSP21062 2111 ram BB128 2164 RAM 2101 ram 1kx16 AD14060
Text: ADSP ADSP 21CSP01 21CSP11 21CSP11L 200 200 200 50 66 60 20 15 15 25 25 30 4Kx24 24Kx24 24Kx24 4Kx16 16Kx16 16Kx16 40 50 66 80 100 40 55 80 40 52 66 80 80 66 100 133 104 80 10.24 12.5 16.67 20 25 10.24 13.84 20 10.24 13 16.67 20 20 , 2Kx24 2Kx24 2Kx24 80 55 80 55 66 40 66 100 20 13.84 20 13.84 16.67 10.24 16.67 25 , MODEL MIPS 2164 2165 2166 10.24 20 16.67 40 80 66 CYLCE CLK TIME IN nsec MHZ


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PDF 21CSP01 21CSP11 21CSP11L 4Kx24 24Kx24 4Kx16 16Kx16 ADSP21062 BT-308 ADSP21062 2111 ram BB128 2164 RAM 2101 ram 1kx16 AD14060
1998 - motorola DSP563XX architecture

Abstract: XC56303PV80 xc56307 XC56303PV66 G.711, G.723.1, G.726, G.728 XC56307GC100C DSP56002FC40 DSP56002FC66 XC56301PW80 SPAKXC56309PV80
Text: -bit data Peripherals 3.3v core 3.3v I/O 66 /80 MIPS 66 /80 MHz 24-bit program 24-bit data 56307 On-chip Memory 66 /80 MIPS 66 /80 MHz 24-bit program 24-bit data 56303 Voltage , -pin PQFP 5.0v core 5.0v I/O 66 MHz 64/512 2x256/2x256 Host,SSI,SCI,Timer OnCE and PLL , ,Timer OnCE and PLL DSP56002PV66 36 144-pin TQFP 5.0v core 5.0v I/O 66 MHz 64/512 , -Bit Fixed Point XC56301PW66 84 208-pin TQFP 3.3v core 3.3v I/O 66 MHz _/4096 _/4096


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PDF SG184/D DSP563xx 24-bit motorola DSP563XX architecture XC56303PV80 xc56307 XC56303PV66 G.711, G.723.1, G.726, G.728 XC56307GC100C DSP56002FC40 DSP56002FC66 XC56301PW80 SPAKXC56309PV80
2001 - ISP2100A

Abstract: ISP2200A ISP2200A/33
Text: Simplify ISP2200A/33 and ISP2200A/ 66 Data Sheet 1-Gb Fibre Channel to 66 -MHz PCI Controller , ISP2100A/33. The ISP2200A/ 66 is pin compatible with the ISP2100A/ 66 . The ISP2200A is a fully , ISP2200A): 66 -MHz, 64-bit PCI host bus interface (ISP2200A/ 66 ) 33-MHz, 64-bit PCI host bus interface , s s s s s s s s s s 33-MHz (ISP2200A/33) or 66 -MHz (ISP2200A/ 66 ), 64-bit, intelligent , . Packaging The ISP2200A/33 and the ISP2200A/ 66 are available in a 256-pin ball grid array (BGA) package


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PDF ISP2200A/33 ISP2200A/66 66-MHz ISP2200A ISP2100A/33. ISP2100A/66. ISP2100A
Not Available

Abstract: No abstract text available
Text: ation in this datasheet is subject to change 42 1714 01 1/ 66 - , .58 2/ 66 Table of Contents 16.5 System control registers , .64 3/ 66 ST18952 1 Introduction The S T 18952 chip includes the SGS-Thomson D950 16 , the D950Core datasheet (docum ent num ber 42-1709). 4/ 66 ST18952 2 Pin Description The , output. 5/ 66 ST18952 Table 2.4 Pin name PJTRQO-7 Table 2.5 Pin name EXTAL General


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PDF ST18952 66MIPS ST18952X66S D950Core
1997 - D950

Abstract: D952 ST18952 Ya13 SCR SN 102 YBs 70 YA11
Text: controller DMA controller 42 1714 01 1/ 66 Table of Contents 1 Introduction . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2/ 66 1 , . . . . . . . . . . . . . . . . . 64 3/ 66 ST18952 1 Introduction The ST18952 chip , details of the D950Core refer to the D950Core datasheet (document number 42-1709). 4/ 66 2 , (XWRE) or BSU EXWR output. 5/ 66 ST18952 Table 2.4 General purpose parallel port / Interrupt


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PDF ST18952 66MIPS D950 D952 ST18952 Ya13 SCR SN 102 YBs 70 YA11
VT82C598

Abstract: 82C596 ACPI CIRCUIT DIAGRAM RX5B VT82C693A VT82C596B SFF-8038i VIA Apollo Design Guide Rx58 "Hot Plug and Play"
Text: , 1999 Revision Initial release based on 82C596A Data Sheet revision 1.1 - Added UltraDMA- 66 to , Replaced IDE function 1 with registers from 686B to reflect UltraDMA- 66 Added / changed PMU function 3 , . 66 Power Management I/O-Space Registers , , ULTRADMA-33/ 66 MASTER MODE PCI-EIDE CONTROLLER, USB CONTROLLER, KEYBOARD CONTROLLER, AND RTC · Inter-operable with VIA and other Host-to-PCI Bridges - Combine with VT82C598 (Apollo MVP3) for a complete 66


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PDF QKDQFHG3RZHU0DQDJHPHQW60 543OXJDQG3OD\ RQWUROOHUDQG57& VT82C596B VT82C598 82C596 ACPI CIRCUIT DIAGRAM RX5B VT82C693A VT82C596B SFF-8038i VIA Apollo Design Guide Rx58 "Hot Plug and Play"
2004 - ISP1582

Abstract: ISP1582BS 3-pin IC 7806
Text: . 03 - 25 August 2004 2 of 66 ISP1582 Philips Semiconductors Hi-Speed USB peripheral , Preliminary data Version Rev. 03 - 25 August 2004 3 of 66 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x , WAKEUP VCC(I/O) Fig 1. Block diagram. ISP1582 Hi-Speed USB peripheral controller 4 of 66 , 750 13699 Preliminary data Rev. 03 - 25 August 2004 5 of 66 ISP1582 Philips , Preliminary data Rev. 03 - 25 August 2004 6 of 66 ISP1582 Philips Semiconductors Hi-Speed USB


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PDF ISP1582 ISP1582 ISP1582BS 3-pin IC 7806
server

Abstract: No abstract text available
Text: ) 67 acronyms 9 Address Recognition mode 66 Addressing mode 89 Append mode 44, 52 async interrupt setup , ) mode 98,104 fields, A and C 67 FIFO and timer operations 39 Flag Hunt mode 66 Flag mode 65-66 format character 66 frame 67 frame check sequence. See FCS frame format 67 FTP server 85 functional description 34 Chain mode 44 Channel Command and Status registers. See registers character format 66 CLK 174 CLK , mode 96 FCT (flow control transparency) mode 98,104 Flag Hunt mode 66 Flag mode 65-66 HDLC mode 89, 91


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PDF CL-CD2231 32-bit server
1999 - Not Available

Abstract: No abstract text available
Text: . 6-6 CPU to PCI Mailbox Interrupt Pending Register 12 . 6-6 PCI to CPU Mailbox Interrupt Pending Register 13 , Table 6.6 Table 6.7 Table 6.8 Table 6.9 Table 6.10 Table 6.11 Table 6.12 Table 6.13 Table 6.14 , ) .6-5 PCI Controller Interrupt Pending Register 11 Field Descriptions. 6-6


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PDF
2005 - ISP1582

Abstract: ISP1582BS toshiba laptop charging CIRCUIT diagram
Text: - 04 January 2005 2 of 66 ISP1582 Philips Semiconductors Hi-Speed USB peripheral , data Version Rev. 04 - 04 January 2005 3 of 66 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x , of 66 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. 13, 26, 29, 41 CS_N , 750 14033 Product data Rev. 04 - 04 January 2005 5 of 66 ISP1582 Philips , data Rev. 04 - 04 January 2005 6 of 66 ISP1582 Philips Semiconductors Hi-Speed USB


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PDF ISP1582 ISP1582 ISP1582BS toshiba laptop charging CIRCUIT diagram
EE-66

Abstract: ADSP-21065L VisualDSP PLIT
Text: Engineer To Engineer Note EE- 66 Notes on using Analog Devices' DSP, audio, & video components , functions with a total of 40 instructions. EE- 66 Page 2 Notes on using Analog Devices' DSP, audio, & , ; CALL .plt_FUNC_A; /* Call to PLIT entry */ DM(I3,M3) = R1; EE- 66 Page 3 Notes on using Analog , DMA transfer EE- 66 Page 4 Notes on using Analog Devices' DSP, audio, & video components from , _ov_runtimestartaddress_1; .EXTERN _ov_runtimestartaddress_2; These constants supply the overlay manager with: EE- 66


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PDF EE-66 32-bit f8-f12, f11-f14, f9-f14, EE-66 ADSP-21065L VisualDSP PLIT
NII51006-7

Abstract: No abstract text available
Text: drivers are provided in the HAL system library. See "Software Programming Model" on page 6­6 for details , page 6­6 "Software Programming Model" on page 6­6 The DMA controller is used to perform direct , DMA controller. Two ioctl() functions are defined for the receiver 6­6 Altera Corporation May , Handbook, Volume 5 Document Revision History Table 6­6 shows the revision history for this chapter. Table 6­6 . Document Revision History Date and Document Version May 2007 v7.1.0 Changes Made


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PDF NII51006-7
2010 - hdg104

Abstract: tft ipod touch 2 interface bluetooth with AVR 32-bit AVR UC3 datasheet AT32UC3C1512 AT32UC3C touch screen avr TFT LCD AVR AT32U AT32UC3B1512
Text: 3.6 1.62 - 3.6 1.62 - 3.6 1.62 - 3.6 1.62 - 3.6 1.62 - 3.6 1.63 - 3.6 66 66 66 66 66 66 66 66 66 66 66 66 66 66 66 66 66 66 60 60 60 60 60 60 60 60 66 66 66 66 66 66 66 66 66 66 66 66 48 48 48 50 50 50 50 50 Package (b) Clock Speed (MHz) 8


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PDF 32-bit hdg104 tft ipod touch 2 interface bluetooth with AVR 32-bit AVR UC3 datasheet AT32UC3C1512 AT32UC3C touch screen avr TFT LCD AVR AT32U AT32UC3B1512
2000 - 82801BA

Abstract: 82801AA intel ICH2 82371AB 82371EB 82801AA 82801AB ata controller 82801BA* manual
Text: . 47 Ultra DMA/ 66 (Ultra DMA mode 4) Configuration . 48 Ultra , Ultra DMA/ 66 and non-Ultra DMA/33 Configuration . 50 Mixed Ultra DMA/33 and , (Low-End, ATA- 66 ) 8086h 244Ah (Mobile, ATA-100) 244Bh (High-End, ATA-100) NOTES: In this , protocol corresponds to either the Ultra ATA/100, Ultra ATA/ 66 or Ultra ATA/33 specifications. The ICH2 , host and device to 100MB/s. The Ultra ATA/100 specification is an extension of Ultra ATA/ 66 and Ultra


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PDF 82801BA 82801AA 82801AB 82801BA 82801AA intel ICH2 82371AB 82371EB 82801AA 82801AB ata controller 82801BA* manual
SCSI Parallel Interfaces

Abstract: ultra3 scsi
Text: QLogic Corporation ISP10160A/33 and ISP10160A/ 66 Intelligent, Dual SCSI Processors Data Sheet Features Available in two versions (collectively referred to as ISP10160A ): The ISP10160A/ 66 supports a 66 -MHz, 64-bit PCI host bus interface with a 528 Mbytes/sec maximum PCI transfer rate. The ISP10160A/33 supports a 33-MHz, 64-bit PCI host bus interface with a 264 Mbytes/sec maximum PCI transfer rate , modules. PCI Interface The ISP10160A PCI interface supports the following: 3 3-MHz or 66 -MHz, 64


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PDF ISP10160A/33 ISP10160A/66 ISP10160A 66-MHz, 64-bit 33-MHz, T10/1302D SCSI Parallel Interfaces ultra3 scsi
2009 - AT32UC3C0128

Abstract: AT32UC3C2512 AT32UC3C AT32UC3C1512 AT32UC3C2128 AT32UC3C2256 ATEVK1103 TQFP100 footprint AT32UC3C264 tft ipod touch 2
Text: 66 66 66 66 66 66 66 66 66 66 66 66 60 60 60 60 60 60 60 60 66 66 66 66 66 66 66 66 66 66 66 66 40 40 40 50 50 50 Package (b) Clock Speed (MHz) Y Y Y


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PDF com/avr32 AVR32 32-bit 32-pin 8-/16-bit AT32UC3C0128 AT32UC3C2512 AT32UC3C AT32UC3C1512 AT32UC3C2128 AT32UC3C2256 ATEVK1103 TQFP100 footprint AT32UC3C264 tft ipod touch 2
2000 - TTC-B-01

Abstract: DSP-21020 ADSP-21020 Radiation Tolerant DSP EA30 EA31 EA21 TSC21020F SCC22900 EA20
Text: Krad, Latch Up immunity better than 100 MeV. 1 ( 66 ) Preliminary DPC Flexible IO port , Interface JTAG Functional block diagram of the T7904E 2 ( 66 ) Rev. B / 06 , -July-2000 3 ( 66 ) Preliminary DPC DSP Processor Core Architecture : DRAM implementation This , Memory (DRAM implementation) DSP Processor Core Architecture : DRAM implementation 4 ( 66 ) Rev , -bit data bus device must be connected on DMD(23-8). Rev. B / 06-July-2000 5 ( 66 ) Preliminary


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PDF T7904E TSC21020F ADSP-21020, 06-July-2000 T7904E- MQFPF256 M/883 S/883 TTC-B-01 DSP-21020 ADSP-21020 Radiation Tolerant DSP EA30 EA31 EA21 SCC22900 EA20
2001 - 82801BA

Abstract: 82801BA* manual INF-8070i 82801CA 2441h 82801AB 82801AA 82371EB 8038I ata controller
Text: ) Configuration . 49 Example #2: Ultra ATA/ 66 (Ultra DMA mode 4) Configuration , . 51 Example #4: Mixed Ultra ATA/ 66 and non-Ultra ATA/33 Configuration . 52 , (Low-End, ATA/ 66 ) 244Ah (Mobile, ATA/100) 244Bh (High-End, ATA/100) 8086h 82801CA (ICH3) ATA Controller 01h 2481h (Low-End, ATA/ 66 ) 248Ah (Mobile, ATA/100) 248Bh (High-End, ATA/100) 8086h , corresponds to either the Ultra ATA/100, Ultra ATA/ 66 or Ultra ATA/33 specifications. The ICH3 is new to


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PDF 82801CA 82801BA 82801AA 82801AB 82801CA, 82801BA, 82801AA, 82801AB 82801BA 82801BA* manual INF-8070i 82801CA 2441h 82801AA 82371EB 8038I ata controller
MCF5307

Abstract: 4k sram mbus free mbus master interfacing sram and dram m-bus
Text: ­ 3.3V pads / 5V tolerant ­ Offered at 22.5/90, 30/90, 45/90 MHz @ 0 to 70C ­ Offered at 16.5/ 66 , 22/ 66 , 33/ 66 MHz @ 0 to 70C, -40 to 85C ­ Samples NOW MCF5307 Intro Motorola ColdFire , MIPs at 66 MHz core clock frequency ­ Offered at 45/90 MHz, 30/90 MHz, 22.5/90 MHz at standard temperature ­ Offered at 33/ 66 MHz, 22/ 66 MHz, 16.5/ 66 MHz at standard and extended temperature ­ Fully


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PDF MCF5307 MCF5307 16-Bit 32-bit 90MHz 4k sram mbus free mbus master interfacing sram and dram m-bus
2000 - PC usb ball mouse CIRCUIT diagram

Abstract: fw82443bx application of 8259 microcontroller SLC90E66 intel fw82443bx 440BX SLC90E66-UF CLK48 82371AB microprocessors interface 8237
Text: SLC90E66 Victory66 Enhanced PCI South Bridge With 66 MHz IDE Controller FEATURES !" Enhanced , 82371AB PIIX4E South Bridge - High Performance OHCI USB Host Controller - Ultra ATA/ 66 IDE Controller , for Pentium II and Pentium Microprocessors - VictoryBX- 66 Chipset with Intel FW82443BX (440BX) North Bridge ® III !" Integrated Ultra ATA/ 66 IDE Controller - Supports "Ultra ATA/ 66 , a multi-function PCI device implementing a PCI-to-ISA bridge function, a PCI Ultra ATA/ 66 IDE


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PDF SLC90E66 Victory66 82371AB ATA/66 VictoryBX-66 FW82443BX 440BX) ATA/66" 66MbI PC usb ball mouse CIRCUIT diagram fw82443bx application of 8259 microcontroller SLC90E66 intel fw82443bx 440BX SLC90E66-UF CLK48 82371AB microprocessors interface 8237
stk1625

Abstract: No abstract text available
Text: receiver A and B buffers 44-45 fixed operations 66 options 67 register definitions 20 register descriptions , fixed operations 66 framing error 66 options 66 transmission of abort 66 transmitter A and B buffers 42


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PDF CL-CD2431 32-bit stk1625
Not Available

Abstract: No abstract text available
Text: . 66 4.3.1 Bisync Transmit Processing. 66 4.3.2 Bisync Receive Processing. 66 TABLE OF CONTENTS DATA BOOK v6.0 Jurte 1995 CL-CD2400/CD2401 M ulti-Protocol Com m , Registers. 115 6.5.3 Modem Interrupt Registers. 118 6.6


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PDF CL-CD2400/CD2401 100-Pin
Supplyframe Tracking Pixel