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DIVIDE-E3-UT Lattice Semiconductor Corporation IP CORE DIVIDER ECP3
DIVIDE-PM-UT Lattice Semiconductor Corporation IP CORE DIVIDER ECP2M
DIVIDE-X2-U Lattice Semiconductor Corporation IP MODULE DIVIDER
DIVIDE-PM-U Lattice Semiconductor Corporation IP CORE DIVIDER ECP2M
DIVIDE-P2-UT Lattice Semiconductor Corporation IP CORE DIVIDER ECP2
DIVIDE-P2-U Lattice Semiconductor Corporation IP CORE DIVIDER ECP2

DIVIDE-BY-17 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
mmic a08

Abstract: transistor t06 t06 TRANSISTOR B584B B585B UPC1678B UPC1668B A08 mmic mmic prescaler divide by 64 uPC1675
Text: 3.3 11 5 5 3.8 4.5 (mA) TYP 20 43 17 19 77 49 43 77 17 19 49 19 43 17 19 77 49 20 43 26 25 22 12 , 33 32 29 15 15 15 5.7 5.7 19 10 10 7 8 Gain (dB) MIN 16 17 10 19 22 21 17 22 10 19 21 18 17 10 18 22 21 16 17 13 21 30 11 18 26 8.5 16 9.5 9 16 9 16 Rim (dB) MAX 20 21 14 24 26 25 21 26 14 24 25 , Mount Mini Mold Surface Mount Mini Mold 15.5 14.5 14 21 14 21 13 13 17 12 11 13 14 11.5 Zo = 50 , 2.5 2.5 2.5 1.0 2.5 2.8 2.8 1.7 Icc (mA) MIN MAX 40 60 24 34 37 7.5 18 15 25 12 18 19 34 40 60 24


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2013 - Not Available

Abstract: No abstract text available
Text: kHz Offset 2 2 Min. Typ. 600 600 10 15 -10 -340 -9 -350 200 280 12 / 14 17 / 16 -151 -150 , , 11, 14, 17 , 21, 24 GND 3, 4 CKN, CKP Differential (CKP-CKN) or single ended (CKP) clock


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PDF HMC791LC4B HMC791LC4B 660mW 600mV 16mm2
2010 - Not Available

Abstract: No abstract text available
Text: @ 28 GHz Input, 20% - 80% 17 / 16 ps Additive Random Jitter [1] CK/2 SSB Phase Noise , these pins connected to RF/DC ground externally. 2, 5, 8, 11, 14, 17 , 21, 24 GND Signal and


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PDF HMC791LC4B HMC791LC4B 660mW 600mV
DIVIDE-BY-17

Abstract: No abstract text available
Text: R A PULSE I 8(16) «- DIVIDE-BY-17 (33) MODE ESTABLISHED Fig. 3b Setting divide-by-17 (33) mode Fig. 3 Timing diagrams m 37bf i S22 CD2SÔ05 23T ■1 SP8782B & B , GEC PLESSEY DS3653-1-2 SP8782A & B 1GHz 16/ 17 , -5-32/33 MULTI-MODULUS DIVIDER The S P 8782 is a m u lti-m o d ulu s d ivid e r w hich d ivid e s by 16/ 17 w hen th e R atio S elect input is , Control input s e le cts th e low e r division ratio (16 or 32) and th e higher ratio ( 17 o r 33) w hen


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PDF DS3653-1-2 SP8782A 8782B DIVIDE-BY-17 SP8782B 37bflS22 DIVIDE-BY-17
2012 - Not Available

Abstract: No abstract text available
Text: -10 -340 -9 -350 200 280 12 / 14 17 / 16 -151 -150 Max. Units mV mV dB dB mV mV mV mV fs fs ps , , 17 , 21, 24 GND 3, 4 CKN, CKP Differential (CKP-CKN) or single ended (CKP) clock inputs


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PDF HMC791LC4B HMC791LC4B 660mW 600mV 16mm2
bcd switch

Abstract: PROGRAMMABLE DIVIDE BY 4059 4000B series cmos gate hct4059 decade counter digits 16 "BCD Switch" divide-by-10 74HCT 74HC 100X6
Text: LE latch enable (active HIGH) 3. 4, 5, 6, 22,21,20, 19, Jl to J16 18, 17 , 16, 15, programmable , INPUTS USED BCD MAX. BINARY MAX. H H H H 2 1 J1 8 7 J2J3J4 15 999 17 331 timer mode H L H H 4 3 JiJ2 4 3 , H H L 10 9 J1J2J3J4 1 0 - 9 999 16 659 L H H H 2 1 Jl 8 7 J2J3J4 15 999 17 331 divide-by-n mode L L , . max. min. max. min. max. »PHI./ tPLH propagation delay CP to Q 58 21 17 200 40 34 250 50 43 300 , ; note 1 *max maximum clock pulse frequency 4.2 21 25 12 36 43 3.4 17 20 2.8 14 17 MHz 2.0 4.5 6.0 Fig


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PDF 74HC/HCT4059 divide-by-10, divide-by-10 4000B" PC74HC/HCT08. PC74HC/HCT4075. PC74HC/HCT4002. PC74HC/HCT04. bcd switch PROGRAMMABLE DIVIDE BY 4059 4000B series cmos gate hct4059 decade counter digits 16 "BCD Switch" 74HCT 74HC 100X6
2002 - MAX9316

Abstract: MAX9322 MAX9322ECY MAX9322ETK
Text: QD1 QD5 19 QD1 18 QD2 17 QD2 16 QD3 15 QD5 50 QD3 14 50 , . 16 22 QD5 Noninverting QD5 Output. Typically terminate with 50 resistor to VCC - 2V. 17 , . Typically terminate with 50 resistor to VCC - 2V. 28, 29 1, 17 , 18, 34, 35, 38, 39, 51, 52, 68 , VCCO N.C. 17 35 N.C. N.C. VCCO QD0 QD0 QD1 QD1 QD2 QD2 QD3 QD3


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PDF 300mV 900ps MAX9322ECY MAX9322ETK* MAX9322 MAX9316 MAX9322 MAX9322ECY MAX9322ETK
2009 - Not Available

Abstract: No abstract text available
Text: 280 12 / 14 17 / 16 -151 -150 Max. Units mV mV dB dB mV mV mV mV fs fs ps ps dBc/Hz dBc/Hz 7 , connection Interface Schematic 7 HIGH SPEED LOGIC - SMT 2, 5, 8, 11, 14, 17 , 21, 24 GND Signal


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PDF HMC791LC4B HMC791LC4B 660mW 600mV
2007 - MAX9316

Abstract: MAX9322 MAX9322ECY MAX9322ETK
Text: 21 QD0 QD4 20 QD1 QD5 19 QD1 18 QD2 17 QD2 16 QD3 15 QD5 , Noninverting QD5 Output. Typically terminate with 50 resistor to VCC - 2V. 17 23 QD4 Inverting QD4 , . Typically terminate with 50 resistor to VCC - 2V. 28, 29 1, 17 , 18, 34, 35, 38, 39, 51, 52, 68 , VCCO N.C. 17 35 N.C. N.C. VCCO QD0 QD0 QD1 QD1 QD2 QD2 QD3 QD3


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PDF MAX9322 MAX9322 MAX9316 MAX9322ECY MAX9322ETK
2007 - Not Available

Abstract: No abstract text available
Text: 24 25 26 QD0 QD4 21 QD0 QD4 20 QD1 QD5 19 QD1 18 QD2 17 , . 17 23 QD4 Inverting QD4 Output. Typically terminate with 50Ω resistor to VCC - 2V. 18 , QD0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 28, 29 1, 17 , 18, 34, 35, 38 , VCCO N.C. 17 35 N.C. N.C. VCCO QD0 QD0 QD1 QD1 QD2 QD2 QD3 QD3


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PDF MAX9322 MAX9322
2007 - Not Available

Abstract: No abstract text available
Text: CLK1 VBB 10 FSELC 11 FSELD 12 ZO = 50 Q_ VEE 13 14 15 16 17 18 19 20 , CLK1 VBB 11 13 FSELC 12 13 14, 27, 30, 39, 40, 47, 52 15 16 17 18 14 15, 16 19, 20, 33 , QFN 25 26 27 28 29 30 31 32 1, 17 , 18, 34, 35, 38, 39, 51, 52, 68 41 42 43 44 45 46 47 48 55 56 57 58 , FSELC 13 FSELD 14 VEE 15 VEE 16 N.C. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VCCO


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PDF MAX9322 MAX9322EC
2001 - Not Available

Abstract: No abstract text available
Text: in USA. 17 Aug 2006. PAGE 1 Divide-by-2 Output Power, 3rd Harmonic & Input Feedthru Min/Max , subject to change without notice. Copyright © 2001-2006 Centellax, Inc. Printed in USA. 17 Aug 2006 , Centellax, Inc. Printed in USA. 17 Aug 2006. PAGE 3 Application Notes Divider Mode The UXC20P , subject to change without notice. Copyright © 2001-2006 Centellax, Inc. Printed in USA. 17 Aug 2006 , . Copyright © 2001-2006 Centellax, Inc. Printed in USA. 17 Aug 2006. PAGE 5 Differential vs


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PDF UXC20P 20GHz 10kHz MO-220 UXC20P
2010 - Not Available

Abstract: No abstract text available
Text: Input, 20% - 80% 12 / 14 ps CK/4 Output Rise/Fall Time @ 28 GHz Input, 20% - 80% 17 / 16 , shown herein was measured with these pins connected to RF/DC ground externally. 2, 5, 8, 11, 14, 17


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PDF HMC791LC4B HMC791LC4B 660mW 600mV
2002 - MAX9316

Abstract: MAX9322 MAX9322ECY MAX9322ETK 36CW
Text: QD4 21 QD0 QD4 20 QD1 QD5 19 QD1 18 QD2 17 QD2 16 QD3 15 , Noninverting QD5 Output. Typically terminate with 50 resistor to VCC - 2V. 17 6 23 QD4 Inverting , terminate with 50 resistor to VCC - 2V. 28, 29 1, 17 , 18, 34, 35, 38, 39, 51, 52, 68 N.C. No , VCCO N.C. 17 35 N.C. N.C. VCCO QD0 QD0 QD1 QD1 QD2 QD2 QD3 QD3


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PDF MAX9322 MAX9322 MAX9316 MAX9322ECY MAX9322ETK 36CW
2007 - maxim MAX9322ECY D

Abstract: No abstract text available
Text: CLK1 VBB 10 FSELC 11 FSELD 12 ZO = 50 Q_ VEE 13 14 15 16 17 18 19 20 , CLK1 VBB 11 13 FSELC 12 13 14, 27, 30, 39, 40, 47, 52 15 16 17 18 14 15, 16 19, 20, 33 , QFN 25 26 27 28 29 30 31 32 1, 17 , 18, 34, 35, 38, 39, 51, 52, 68 41 42 43 44 45 46 47 48 55 56 57 58 , FSELC 13 FSELD 14 VEE 15 VEE 16 N.C. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VCCO


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PDF MAX9322 MAX9322ECY MAX9322ECY-T MAX9322ECY MAX9322ECY-TD MAX9322ECY-D maxim MAX9322ECY D
2005 - TRF3761-B

Abstract: TRF3761-A QFN-40 thermal resistance TRF3761-H TRF3761-E TRF3761-F TRF3761-C
Text: VCO FEATURES LOCK_DETECT AVDD_REF · · · · · · · GND 10 11 12 13 14 15 16 17 , NO. 1 2 3 4 5 6, 7 8 9 13 14 15 17 18 19 21 23 24 25 26 28 29 10, 11, 12, 16, 20, 22, 27, 30, 31, 33 , CHARACTERISTICS (continued) Figure 17 . Direct Output: PFD Frequency Spurs PRODUCT PREVIEW 16 Figure 18 , Noise Figure 25. Closed Loop VCO Phase Noise Submit Documentation Feedback 17 PRODUCT , ,B4>:10 :11 8/9 16/ 17 32/33 64/65 6-bit A counter 13-bit B counter Reserved Reserved Lock PLL


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PDF TRF3761 SLWS181B TRF3761-A TRF3761-B TRF3761-C TRF3761-D TRF3761-E TRF3761-F TRF3761-G TRF3761-H QFN-40 thermal resistance
prescaler 120 ghz

Abstract: BF08 uPG504 5 GHz DIVIDE-BY-2 STATIC PRESCALER UPG100B
Text: 80 15.0 16 40 B08 6-11 U 3G105B-1 2.7 to 4.2 25 ±2.5 1.7 9 35 , ) (dB) 1.4 40 30 R L in (dB) 17 Switching OT)rough) (Open) PldB Speed (dB) (dB) (dBM) (ns) R , Ceramic Chip Page No. 6-18 13 9 25 5 UFG107P DC to 3.4 1.4 40 30 17


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2005 - j 4315-0

Abstract: TRF376121IRHAT TRF376119IRHAT
Text: 15 16 17 18 21 19 20 AVDD APPLICATIONS Wireless Infrastructure ­ WCDMA ­ CDMA ­ GSM , REF_IN LOCK_DETECT DVDD2 NO. 1 2 3 4 5 6, 7 8 9 13 14 15 17 18 19 21 23 24 25 26 28 29 10, 11, 12, 16, 20 , 10 M -170 100 1k 10 k 100 k f - Frequency Offset - Hz 1M 10 M Figure 17 . Open Loop , Frequency Spurs Figure 28. Divide-By-4 Output: PFD Frequency Spurs Submit Documentation Feedback 17 , ,B4>:10 :11 8/9 16/ 17 32/33 64/65 6-bit A counter 13-bit B counter Reserved Reserved Lock PLL


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PDF TRF3761 SLWS181A TRF3761-1579 TRF3761-1700 TRF3761-1817 TRF3761-1947 TRF3761-2116 TRF3761-2289 TRF3761 j 4315-0 TRF376121IRHAT TRF376119IRHAT
Not Available

Abstract: No abstract text available
Text: between divide-by-5 and divide-by-4095 MB15S00 2.7 to 3.6 V 3.5 mA 300 MHz 16/ 17 or 32/33


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PDF MB15S00 divide-by-4095 divide-by-31 MB15S00
2005 - TRF3761-A

Abstract: TRF3761-B TRF3761 TRF3761-E TRF3761-H TRF3761-F TRF3761-C
Text: 18 RBIAS2 16 17 AVDD_VCOBUF Wireless Infrastructure ­ WCDMA, CDMA, GSM ­ Wideband , 22 GND 18 AVDD GND 16 17 21 19 20 RBIAS2 15 AVDD_VCOBUF 14 VCO_OUTP , capacitors in parallel. AVDD_VCOBUF 17 Power supply for VCO buffers, requires 4.5 to 5.25 V , Feedback 17 TRF3761 www.ti.com SLWS181F ­ OCTOBER 2005 ­ REVISED JANUARY 2007 TRP3761-C TYPICAL , Output: PFD Frequency Spurs Figure 17 . Divide-By-2 Output: PFD Frequency Spurs Figure 18


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PDF TRF3761 SLWS181F TRF3761-A TRF3761-B TRF3761 TRF3761-E TRF3761-H TRF3761-F TRF3761-C
1995 - cmos 3F transistor

Abstract: FCT3932
Text: , loop filter and VCO. The FCT3932 requires no external loop filter components. The FCT3932 provides 17 , state. 0.5 MICRON CMOS Technology Guaranteed low skew 16 programmable frequency configurations 17 , 35 Q88 AGND 15 34 Q87 GND 16 33 GND OE1 17 32 Q86 OE2 18


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PDF IDT54/74FCT3932 IDT74FCT3932 FCT3932 SO48-1) SO48-2) cmos 3F transistor
1996 - 100MHz oscillator

Abstract: 2.2f 5.5v cmos 3F transistor PLL 100Mhz FCT3932
Text: , loop filter and VCO. The FCT3932 requires no external loop filter components. The FCT3932 provides 17 , state. 0.5 MICRON CMOS Technology Guaranteed low skew 16 programmable frequency configurations 17 , NC 14 35 Q88 AGND 15 34 Q87 GND 16 33 17 32 Q86 OE2 18


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PDF IDT54/74FCT3932 IDT74FCT3932 FCT3932 SO48-1) SO48-2) 100MHz oscillator 2.2f 5.5v cmos 3F transistor PLL 100Mhz
2002 - Not Available

Abstract: No abstract text available
Text: Pulling (into a 2.0:1 VSWR) Pushing @ Vtune= 5V Frequency Drift Rate -7 -28 - 17 -40 0.6 5 1.5 dBc dBc , . MIXER 17 - 25Vcc= GHz Frequency Tuning Voltage, T= 25°C Frequency Tuning Voltage, +5V 13.8 13.7 13.8 , GHz Divided Frequency vs. Tuning Voltage, Vcc= +5V DIVIDED OUTPUT FREQUENCY (GHz) 1.72 1.71 1.7


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PDF HMC401QS16G QSOP16G HMC401QS16G
Not Available

Abstract: No abstract text available
Text: , edge-triggered) 2 LE latch enable (active HIGH) 3, 4, 5, 6, 22, 21, 20, 19, 18, 17 , 16, 15, 10, 9, 8 , . JAM DIVIDED PRESET INPUTS BY STATE USED BCD MAX. J1 8 7 J2J3J4 15 999 17 331 , H 2 1 J1 8 7 J2J3J4 15 999 17 331 L L H H 4 3 J1J2 4 , 6 16 19 6.0 4.2 12 3.4 2.8 21 36 17 14 4.5 43 20 17 , 40 50 propagation delay LE to Q 200 21 14 tTHL/ tTLH 58 17 tPHL/ tPLH


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PDF 74HC/HCT/HCU/HCMOS 74HC/HCT4059
2004 - HMC401QS16G

Abstract: No abstract text available
Text: Output Divided Output Tune Voltage Typ. µA 2 1/2 3/2 2nd 5/2 dB -7 -28 - 17 -40 , Frequency vs. Tuning Voltage, Vcc= +5V PUMPED MIXER 17 - 25 GHz Frequency vs. Tuning Voltage, T= 25 , vs. Tuning Voltage, Vcc= +5V 1.7 1.69 1.68 1.67 1.66 1.65 1.64 +25 C 1.63 +85 C -40


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PDF HMC401QS16G QSOP16G HMC401QS16G
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