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Not Available

Abstract: No abstract text available
Text: DIN8 DIN4 3 32 DIN3 4 41 DIN9 DIN2 5 40 DIN10 DIN1 6 39 DIN11 6 DIN0 7 , DIN8 DIN9 DIN10 DIN11 RXINC RR RADE/RX RCLK 15 DO2 18 WADE/RX 16 RXAD 10 , /TR WADE/RX WXAD WCLK DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 MSM548331TS-K (2/3) INPUT DIN0 - DIN11 IE OE RADE/RX RCLK RE RX RR RXAD RXINC WADE/RX WCLK WE WR/TR WXAD WXINC , READ ADDRESS CONTROL RXINC DIN0 - DIN11 7 - 2, 44 - 39, 30 - 31 MEMORY CONTROLLER WCLK


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PDF MSM548331TS-K DIN10 DIN11 12-BIT
2005 - LF3320

Abstract: LF3320QC12G cf02
Text: column-vector, will be loaded through DIN11-0. DIN11-0 RIN11-0 12 0 A ALU B 0 A ALU 0 , coefficient sets to be updated within vertical blanking. LF3320 BLOCK DIAGRAM ROUT11-0 DIN11-0 CAA7 , RSLB OUT15-12 1-16 CAA7-0 DIN11-0 ROUT11-4 1-16 4 8 1-16 1-16 CFA11-0 12 , FORMATS The rising edge of CLK strobes all enabled registers. Inputs DIN11-0 - Data Input DIN11-0 is the 12-bit data input port to Filter A. In Dual Filter Mode, DIN11-0 can also be the 12


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PDF LF3320 12-bit 24-bit) 32-Tap 16-bit CFA11 CFA10 ROUT11 ROUT10 LF3320 LF3320QC12G cf02
2007 - LF3320

Abstract: lf3320 r CF1-2
Text: , will be loaded through DIN11-0. DIN11-0 RIN11-0 12 0 A ALU B 0 A ALU 0 0 , . LF3320 BLOCK DIAGRAM ROUT11-0 DIN11-0 CAA7-0 12 12 INTERLEAVE / DECIMATION REGISTERS , -0 DIN11-0 ROUT11-4 1-16 4 8 1-16 1-16 CFA11-0 12 RSLB OUT11-0 ROUT3 , CLK strobes all enabled registers. Inputs DIN11-0 - Data Input DIN11-0 is the 12-bit data input port to Filter A. In Dual Filter Mode, DIN11-0 can also be the 12-bit input port to Filter B. Data


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PDF LF3320 12-bit 24-bit) 32-Tap 16-bit 3320-R LF3320 lf3320 r CF1-2
Not Available

Abstract: No abstract text available
Text: DIAGRAM 12 DIN11-0 16-TAP HORIZONTAL FILTER 256 COEFFICIENT SET STORAGE 3K LINE BUFFER 3K LINE , HCF11-0 12 1-16 1-16 I/D REGISTERS FIGURE 1. DIN11-0 TXFR LF3310 Horizontal , (Sign) DIN11-0 — Data Input DIN11-0 is the 12-bit registered data input port. Data is latched on , loading of data into the input register ( DIN11-0 ). If the device is configured such that the vertical , input register ( DIN11-0 ) and the line buffers in the vertical filter. It is important to note that in


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PDF LF3310 12-bit 12-bit, DIN11 DIN10 LF3310QC15 LF3310QC12 MIL-STD-883
1999 - LF3310

Abstract: SH15 743H
Text: other coefficient sets in the same filter. LF3310 BLOCK DIAGRAM 12 DIN11-0 16-TAP HORIZONTAL , FIGURE 1. DIN11-0 TXFR LF3310 Horizontal / Vertical Digital Image Filter LF3310 FUNCTIONAL , Vertical Accumulator Output (Sign) DIN11-0 - Data Input DIN11-0 is the 12-bit registered data , loading of data into the input register ( DIN11-0 ). If the device is configured such that the vertical , input register ( DIN11-0 ) and the line buffers in the vertical filter. It is important to note that in


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PDF LF3310 12-bit 12-bit, DIN11 DIN10 LF3310QC15 LF3310QC12 MIL-STD-883 LF3310 SH15 743H
2005 - Not Available

Abstract: No abstract text available
Text: column-vector, will be loaded through DIN11-0. DIN11-0 RIN11-0 12 0 A ALU B 0 A ALU 0 , coefficient sets to be updated within vertical blanking. LF3320 BLOCK DIAGRAM ROUT11-0 DIN11-0 CAA7 , RSLB OUT15-12 1-16 CAA7-0 DIN11-0 ROUT11-4 1-16 4 8 1-16 1-16 CFA11-0 12 , . ACCUMULATOR OUTPUT FORMATS The rising edge of CLK strobes all enabled registers. Inputs DIN11-0 — Data Input DIN11-0 is the 12-bit data input port to Filter A. In Dual Filter Mode, DIN11-0 can also be the


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PDF LF3320 12-bit 24-bit) 32-Tap 16-bit 3320-Q
2001 - 743H

Abstract: VCF9 3310 DIODE DATASHEET LF3310 SH15
Text: DIN11-0 16-TAP HORIZONTAL FILTER 256 COEFFICIENT SET STORAGE 3K LINE BUFFER 3K LINE BUFFER , HCF11-0 12 1-16 1-16 I/D REGISTERS FIGURE 1. DIN11-0 TXFR LF3310 Horizontal , Inputs DIN11-0 - Data Input DIN11-0 is the 12-bit registered data input port. Data is latched on the , filter, HSHEN also enables or disables the loading of data into the input register ( DIN11-0 ). If the , or disables the loading of data into the input register ( DIN11-0 ) and the line buffers in the


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PDF LF3310 12-bit 12-bit, VCF11 VCF10 DOUT11 DOUT10 LF3310QC15 743H VCF9 3310 DIODE DATASHEET LF3310 SH15
2003 - CXD3531R

Abstract: CXA7004R VC0 LQFP48
Text: 32 31 30 29 28 27 26 25 D_IN11 37 24 SID_OUT TG SID D_IN10 38 , Equivalent circuit Description VDD 37 to 48 D_IN11 to D_IN0 I High: 2.0V Low: 0.8V 1k 37 to 48 Digital data input. D_IN0: LSB D_IN11 : MSB GND 35 VDD 3.3V 3.3V , D_IN8 33 38 SENB D_IN9 34 24 DGND D_IN10 35 A 37 DGND D_IN11 , Operation The flow of internal operations is described below. The digital signals input to D_IN0 to D_IN11


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PDF CXA7004R CXA7004R 12-bit 48PIN LQFP-48P-L01 P-LQFP48-7x7-0 CXD3531R VC0 LQFP48
2005 - Horizontal Digital Image Filter

Abstract: LF3320QC12 LF3320 cf02
Text: , will be loaded through DIN11-0. DIN11-0 RIN11-0 12 0 A ALU B 0 A ALU 0 0 , coefficient sets to be updated within vertical blanking. LF3320 BLOCK DIAGRAM ROUT11-0 DIN11-0 CAA7 , RSLB OUT15-12 1-16 CAA7-0 DIN11-0 ROUT11-4 1-16 4 8 1-16 1-16 CFA11-0 12 , FORMATS The rising edge of CLK strobes all enabled registers. Inputs DIN11-0 - Data Input DIN11-0 is the 12-bit data input port to Filter A. In Dual Filter Mode, DIN11-0 can also be the 12


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PDF LF3320 12-bit 24-bit) 32-Tap 16-bit 3320-Q Horizontal Digital Image Filter LF3320QC12 LF3320 cf02
2002 - LF3311

Abstract: 743H LF3310 LF3320 RV15 VCF5 VCF9
Text: time 1 1.5 10 4 1.5 Figure 2. LF3311 Block Diagram DIN11-0 12 16-TAP HORIZONTAL , HPAUSE I DIN11-0 O DATA DELAY 12 E 1-16 1-16 1-16 1-16 1-16 1-16 , into the input register ( DIN11-0 ) and the line buffers. It is important to note that in Orthogonal Mode, either HSHEN or VSHEN can disable the loading of data into the input register ( DIN11-0 ), I/D , line buffers to be loaded in parallel. When Bit 1 is "1", the input register ( DIN11-0 ) loads all seven


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PDF LF3311 12-bit 12-bit, DIN11 DIN10 HCF11 HCF10 311-A LF3311 743H LF3310 LF3320 RV15 VCF5 VCF9
2003 - LF3321

Abstract: LF3320
Text: -0 DIN11-0 CAA7-0 12 12 INTERLEAVE / DECIMATION REGISTERS 12 12 8 8 12 12 , -0 DIN11-0 ROUT11-4 1-16 1-16 PAUSEA RSLB OUT11-0 OEC 1-16 1-16 CFB11-0 1-16 , filter taps (see Figure 8). COUT11-0 of one device should be connected to DIN11-0 of another device , filter mode. In Single Filter Mode, DIN11-0 is the data input for the filter and DOUT15-0 is the data , /D REGISTERS FILTER A DIN11-0 RIN11-0 FILTER B 12 COUT11-0 RSL CIRCUIT 16


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PDF LF3321 12-bit 24-bit) 32-Tap 16-bit LF3321 CFA11 CFA10 ROUT11 ROUT10 LF3320
2001 - LF3310

Abstract: 3310 h5 LIFO VCF9 VCF11
Text: DIN11-0 16-TAP HORIZONTAL FILTER 256 COEFFICIENT SET STORAGE 3K LINE BUFFER 3K LINE BUFFER , 1-16 I/D REGISTERS FIGURE 1. DIN11-0 TXFR LF3310 Horizontal / Vertical Digital Image , Coefficient Input Vertical Accumulator Output (Sign) DIN11-0 - Data Input DIN11-0 is the 12 , loading of data into the input register ( DIN11-0 ). If the device is configured such that the vertical , input register ( DIN11-0 ) and the line buffers in the vertical filter. It is important to note that in


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PDF LF3310 12-bit 12-bit, DIN11 DIN10 LF3310QC15 LF3310QC12 MIL-STD-883 LF3310 3310 h5 LIFO VCF9 VCF11
2005 - LF3310

Abstract: Vertical Digital Image Filter lf3310 i VCF9 VCF5 VCF01 SV15 743H RV15 HCF11-9
Text: 256 COEFFICIENT SET STORAGE DIN11-0 3K LINE BUFFER 12 3K LINE BUFFER DOUT11-0 Video , DATA DELAY 1-16 12 12 1-16 I/D REGISTERS 1-16 HCF11-0 DIN11-0 TXFR LF3310 , FORMATS Horizontal Accumulator Output 31 30 29 220 219 218 Inputs DIN11-0 is the 12-bit registered , ) DIN11-0 - Data Input S6 S5 F6 F5 F7 F6 F8 F7 ··· ··· ··· F24 F23 , the loading of data into the input register ( DIN11-0 ). ter's contents will not be changed. If the


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PDF LF3310 12-bit 12-bit, 9/14/2005-LDS 3310-I LF3310 Vertical Digital Image Filter lf3310 i VCF9 VCF5 VCF01 SV15 743H RV15 HCF11-9
2005 - Not Available

Abstract: No abstract text available
Text: -TAP VERTICAL FILTER 256 COEFFICIENT SET STORAGE DIN11-0 3K LINE BUFFER 12 3K LINE BUFFER DOUT11 , INTERFACE DATA DELAY 1-16 12 12 1-16 I/D REGISTERS 1-16 HCF11-0 DIN11-0 TXFR , ACCUMULATOR FORMATS Horizontal Accumulator Output 31 30 29 220 219 218 Inputs DIN11-0 is the 12 , ) DIN11-0 — Data Input S6 S5 F6 F5 F7 F6 F8 F7 ··· ··· ··· F24 , the loading of data into the input register ( DIN11-0 ). ter’s contents will not be changed. If the


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PDF LF3310 12-bit 12-bit, 9/14/2005-LDS 3310-I
LF3320

Abstract: Discrete Cosine Transform with the LF3320 Back F38H idct accumulator CA-008 CA001 C14H DIN110 RIN11
Text: . MATRIX-VECTOR MULTIPLY MODE N DIN11-0 RIN11-0 12 0 A ALU B 0 A ALU 0 B A ALU , DOUT15-0 of the first device will become the input DIN11-0 to the second device. The final 16 , have 8, 12-bit coefficients. The input data, [8x1] column-vector, will be loaded through DIN11-0 for , through DIN11-0. Mode Configuration To configure the LF3320 for matrix-vector multiplication, bit 4 of , Mode 0 : Single Filter Mode 1 : Dual Filter Mode 2 Filter B Input 0 : RIN11-0 1 : DIN11-0


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PDF LF3320 LF3320 DIN11-0 RIN11-0 CA001 CA008 CA009 CA000 CA015 Discrete Cosine Transform with the LF3320 Back F38H idct accumulator CA-008 CA001 C14H DIN110 RIN11
2002 - LF3320

Abstract: LF3321
Text: Enable Delay 10 8 Figure 2. LF3321 Block Diagram ROUT11-0 DIN11-0 CAA7-0 12 12 , RSLB OUT15-12 1-16 4 8 1-16 1-16 CAA7-0 DIN11-0 ROUT11-4 1-16 1-16 , should be connected to DIN11-0 of another device. ROUT11-0 of one device should be connected to RIN11 , filter taps. Bit 1 in Configuration Register 5 determines the filter mode. In Single Filter Mode, DIN11-0 , . Single Filter Mode ROUT11-0 12 12 I/D REGISTERS 12 I/D REGISTERS FILTER A DIN11-0


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PDF LF3321 16-bit 12-bit 24-bit) 32-Tap 12-bit, CFA11 CFA10 ROUT11 ROUT10 LF3320 LF3321
1999 - Not Available

Abstract: No abstract text available
Text: -0 DIN11-0 CAA7-0 INTERLEAVE / DECIMATION REGISTERS 12 12 8 8 12 12 CENA CFA11 , 1-16 1-16 FILTER A I/D REGISTERS 1-16 RSLB OUT15-12 1-16 CAA7-0 DIN11-0 ROUT11 , 31 30 29 –220 219 218 DIN11-0 — Data Input Accumulator B Output (Sign) DIN11-0 is the 12-bit data input port to Filter A. In Dual Filter Mode, DIN11-0 can also be the 12-bit input , -bit registered cascade output port. COUT11-0 should be connected to DIN11-0 of another LF3320. In Dual Filter


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PDF LF3320 12-bit 24-bit) 32-Tap 16-bit DOUT15 DOUT14 DOUT13 DOUT12
1999 - LF3320

Abstract: No abstract text available
Text: -0 DIN11-0 CAA7-0 INTERLEAVE / DECIMATION REGISTERS 12 12 8 8 12 12 CENA CFA11 , 1-16 1-16 FILTER A I/D REGISTERS 1-16 RSLB OUT15-12 1-16 CAA7-0 DIN11-0 ROUT11 , ­220 219 218 DIN11-0 - Data Input Accumulator B Output (Sign) DIN11-0 is the 12-bit data input port to Filter A. In Dual Filter Mode, DIN11-0 can also be the 12-bit input port to Filter B , . COUT11-0 should be connected to DIN11-0 of another LF3320. In Dual Filter Mode, COUT11-0 is a 12


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PDF LF3320 12-bit 24-bit) 32-Tap 16-bit DOUT15 DOUT14 DOUT13 DOUT12 LF3320
2005 - hdr2x20

Abstract: PARALLEL OPTIC VCSEL array, 850nm 24 fiber mtp array polarity HFBR-7700 HFBR-772B HFBR-779B HFBR-7800 DIN7 CONNECTOR
Text: + Din10- J5 J6 Din10+ J7 Din11- J8 Din11+ J28 TX_DIS J27 TX_EN DNC - DO NOT , Din9+ GND Din10- GND Din10+ GND Din11- GND Din11+ J30 -FAULT -FAULT , + GND GND C DNC GND Din11+ DNC GND GND Din11- Din10+ GND Din6- Din6 , - Din11+ Din0+ Din11- D1 + - Tx_EN Tx_DIS FAULT S1 J29 J28 J3 0 J27 , /Din9 +/Din10 +/ Din11 +/- Serial Data Inputs (I) CML* 100 W differential termination, CML


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PDF HFBR-772/782BX HFBR-779/789BX HFBR772/782BX HFBR-779/789BX HFBR7700 HFBR-7800 Dout11- Dout11+ 12-Channel hdr2x20 PARALLEL OPTIC VCSEL array, 850nm 24 fiber mtp array polarity HFBR-7700 HFBR-772B HFBR-779B HFBR-7800 DIN7 CONNECTOR
2003 - Not Available

Abstract: No abstract text available
Text: FRP CLK VDD 36 35 34 33 32 31 30 29 28 27 26 25 D_IN11 37 , CKPOL. High: reverse polarity Low: positive polarity GND VDD 37 to 48 D_IN11 to D_IN0 I High: 2.0V Low: 0.8V 1k 37 to 48 Digital data input. D_IN0: LSB D_IN11 : MSB GND ­5­ , FRP CLK VDD VCC A 36 D_IN11 D_IN10 D_IN9 D_IN8 D_IN7 D_IN6 D_IN5 D_IN4 D_IN3 D_IN2 , below. The digital signals input to D_IN0 to D_IN11 are internally demultiplexed into 6 phases, and then


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PDF CXA7004R CXA7004R 12-bit 48PIN LQFP-48P-L01 P-LQFP48-7x7-0
2003 - Not Available

Abstract: No abstract text available
Text: VDD 36 35 34 33 32 31 30 29 28 27 26 25 D_IN11 37 VCC TG , Equivalent circuit Description 37 to 48 D_IN11 to D_IN0 I High: 2.0V Low: 0.8V 1k 37 to 48 Digital data input. D_IN0: LSB D_IN11 : MSB GND 35 VDD 3.3V 15.5V 15.5V DGND AGND , A 36 D_IN11 D_IN10 D_IN9 D_IN8 D_IN7 D_IN6 D_IN5 D_IN4 D_IN3 D_IN2 D_IN1 D_IN0 35 34 33 , operations is described below. The digital signals input to D_IN0 to D_IN11 are internally demultiplexed into


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PDF CXA7004R CXA7004R 12-bit 48PIN LQFP-48P-L01 P-LQFP48-7x7-0
LF3320QC12

Abstract: CFB9 LF3320 frequency multiplication
Text: ROUT11-0 DIN11-0 CAA7-0 12 12 INTERLEAVE / DECIMATION REGISTERS 12 12 8 8 12 , 1-16 1-16 FILTER A I/D REGISTERS 1-16 RSLB OUT15-12 1-16 CAA7-0 DIN11-0 ROUT11 , ­220 219 218 DIN11-0 - Data Input Accumulator B Output (Sign) DIN11-0 is the 12-bit data input port to Filter A. In Dual Filter Mode, DIN11-0 can also be the 12-bit input port to Filter B , -bit registered cascade output port. COUT11-0 should be connected to DIN11-0 of another LF3320. In Dual Filter


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PDF LF3320 12-bit 24-bit) 32-Tap 16-bit DOUT15 DOUT14 DOUT13 DOUT12 LF3320QC12 CFB9 LF3320 frequency multiplication
2001 - CFB9

Abstract: No abstract text available
Text: Supply u 144 Lead PQFP LF3320 BLOCK DIAGRAM ROUT11-0 12 12 RIN11-0 DIN11-0 CAA7-0 CENA , 8 ALU B B A A A A A A B A B B A B B A B B A B A B B A B B A B 1-16 DIN11-0 A ALU B , rising edge of CLK strobes all enabled registers. Inputs DIN11-0 - Data Input DIN11-0 is the 12-bit data input port to Filter A. In Dual Filter Mode, DIN11-0 can also be the 12-bit input port to Filter B. Data , , COUT11-0 is a 12-bit registered cascade output port. COUT11-0 should be connected to DIN11-0 of another


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PDF LF3320 LF3320 32-tap 16-tap COUT11 COUT10 CFB11 CFB9
2001 - led matrix 8x8 mini circuits

Abstract: mini matrix 8x8 LF3320 CAA70
Text: coefficient sets to be updated within vertical blanking. LF3320 BLOCK DIAGRAM ROUT11-0 DIN11-0 CAA7 , 1-16 RSLB OUT15-12 1-16 CAA7-0 DIN11-0 ROUT11-4 1-16 1-16 4 8 1-16 ROUT3 , . Accumulator A Output Inputs 31 30 29 ­220 219 218 DIN11-0 - Data Input Accumulator B Output (Sign) DIN11-0 is the 12-bit data input port to Filter A. In Dual Filter Mode, DIN11-0 can also be , a 12-bit registered cascade output port. COUT11-0 should be connected to DIN11-0 of another


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PDF LF3320 12-bit 24-bit) 32-Tap 16-bit DOUT15 DOUT14 DOUT13 DOUT12 led matrix 8x8 mini circuits mini matrix 8x8 LF3320 CAA70
2005 - LF3311

Abstract: Vertical Digital Image Filter VCF01 200H 201H LF3310 8 tap fir filter VCF5
Text: 1.5 10 4 1.5 Figure 2. LF3311 Block Diagram DIN11-0 12 16-TAP HORIZONTAL FILTER 256 , CLK 12 1-16 1-16 LOGIC Devices Incorporated O DIN11-0 LF3311 Horizontal / Vertical , enables or disables the loading of data into the input register ( DIN11-0 ) and the line buffers. It is , input register ( DIN11-0 ), I/D Registers, and line buffers. Both must be active to enable data loading , Register 3 allows the line buffers to be loaded in parallel. When Bit 1 is "1", the input register ( DIN11-0


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PDF LF3311 12-bit 12-bit, 3311-C LF3311 Vertical Digital Image Filter VCF01 200H 201H LF3310 8 tap fir filter VCF5
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