The Datasheet Archive

DHVQFN14 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2007 - 74HC02

Abstract: 74HCT02 74LV02 74LV02BQ 74LV02D 74LV02PW JESD22-A114E TSSOP14 DHVQFN14
Text: package; 14 leads; body width 4.4 mm SOT402-1 74LV02BQ -40 °C to +125 °C DHVQFN14 plastic , . Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description , TSSOP14 package [3] - 500 mW DHVQFN14 package [4] - 500 mW [1] The input , Semiconductors Quad 2-input NOR gate DHVQFN14 : plastic dual in-line compatible thermal enhanced very thin , ISSUE DATE 02-10-17 03-01-27 Fig 10. Package outline SOT762-1 ( DHVQFN14 ) 74LV02_4 Product data


Original
PDF 74LV02 74LV02 74HC02 74HCT02. JESD22-A114E JESD22-A115-A 74HCT02 74LV02BQ 74LV02D 74LV02PW TSSOP14 DHVQFN14
2007 - Not Available

Abstract: No abstract text available
Text: DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 , or input. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 , linearly with 8 mW/K. For TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN14 , Quad 2-input OR gate DHVQFN14 : plastic dual in-line compatible thermal enhanced very thin quad flat , 02-10-17 03-01-27 Fig 10. Package outline SOT762-1 ( DHVQFN14 ) 74ALVC32_2 Product data sheet Â


Original
PDF 74ALVC32 74ALVC32 JESD8B/JESD36 JESD22-A114E JESD22-A115-A
2007 - dhvqfn14

Abstract: 74AHCT08D NXP 74AHC08 JESD22-A114E 74AHCT08PW 74AHCT08D 74AHCT08 74AHC08PW 74AHC08D 74AHC08BQ
Text: outline package; 14 leads; body width 4.4 mm SOT402-1 -40 °C to +125 °C DHVQFN14 plastic dual , 5. Pin configuration DHVQFN14 74AHC_AHCT08_3 Product data sheet © NXP B.V. 2007. All rights , ] - 500 mW DHVQFN14 package [4] - 500 mW [1] The input and output voltage , 74AHC08; 74AHCT08 NXP Semiconductors Quad 2-input AND gate DHVQFN14 : plastic dual in-line , . Package outline SOT762-1 ( DHVQFN14 ) 74AHC_AHCT08_3 Product data sheet © NXP B.V. 2007. All rights


Original
PDF 74AHC08; 74AHCT08 74AHCT08 74AHC08 JESD22-A114E JESD22-A115-A dhvqfn14 74AHCT08D NXP 74AHCT08PW 74AHCT08D 74AHC08PW 74AHC08D 74AHC08BQ
2007 - 74HC04 nxp

Abstract: dhvqfn14 74HCT04 74LV04 74LV04BQ 74HC04 74LV04DB 74LV04N 74LV04PW JESD22-A114E
Text: outline package; 14 leads; body width 4.4 mm SOT402-1 74LV04BQ -40 °C to +125 °C DHVQFN14 , . Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 74LV04_3 , mW DHVQFN14 package [1] [2] [5] - 500 mW The input and output voltage ratings , 4 December 2007 11 of 15 74LV04 NXP Semiconductors Hex inverter DHVQFN14 : plastic , . Package outline SOT762-1 ( DHVQFN14 ) 74LV04_3 Product data sheet © NXP B.V. 2007. All rights


Original
PDF 74LV04 74LV04 74HC04 74HCT04. JESD22-A114E JESD22-A115-A 74HC04 nxp dhvqfn14 74HCT04 74LV04BQ 74LV04DB 74LV04N 74LV04PW
2008 - Not Available

Abstract: No abstract text available
Text: 74HC27BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin , ; 14 leads; body width 4.4 mm 74HCT27BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line , configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A , temperature −65 +150 °C DIP14 package - 750 mW SO14, (T)SSOP14 and DHVQFN14 , above 70 °C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN14


Original
PDF 74HC27; 74HCT27 74HCT27 JESD22-A114E JESD22-A115-A 74HC27N DIP14
2007 - Not Available

Abstract: No abstract text available
Text: −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad , DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin , DHVQFN14 package [5] - 500 mW [1] The input and output voltage ratings may be exceeded if , Semiconductors Quad 2-input NAND gate DHVQFN14 : plastic dual in-line compatible thermal enhanced very thin , ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline SOT762-1 ( DHVQFN14 ) 74LV00_3 Product data


Original
PDF 74LV00 74LV00 74HC00 74HCT00. JESD22-A114E JESD22-A115-A
2007 - Not Available

Abstract: No abstract text available
Text: width 4.4 mm SOT402-1 74LV86BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line , and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 74LV86_3 Product data sheet © NXP B.V , DHVQFN14 package [5] - 500 mW [1] The input and output voltage ratings may be exceeded if , 11 of 15 74LV86 NXP Semiconductors Quad 2-input exclusive-OR gate DHVQFN14 : plastic dual , outline SOT762-1 ( DHVQFN14 ) 74LV86_3 Product data sheet © NXP B.V. 2007. All rights reserved


Original
PDF 74LV86 74LV86 74HC86 74HCT86. JESD22-A114E JESD22-A115-A
2007 - 74ALVC32

Abstract: 74ALVC32BQ 74ALVC32D 74ALVC32PW DHVQFN14 JESD22-A114E TSSOP14
Text: package; 14 leads; body width 4.4 mm SOT402-1 74ALVC32BQ -40 °C to +85 °C DHVQFN14 plastic , configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 74ALVC32_2 Product data sheet © NXP , . For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K. 74ALVC32_2 Product data sheet , Semiconductors Quad 2-input OR gate DHVQFN14 : plastic dual in-line compatible thermal enhanced very thin , ISSUE DATE 02-10-17 03-01-27 Fig 10. Package outline SOT762-1 ( DHVQFN14 ) 74ALVC32_2 Product


Original
PDF 74ALVC32 74ALVC32 JESD8B/JESD36 JESD22-A114E JESD22-A115-A 74ALVC32BQ 74ALVC32D 74ALVC32PW DHVQFN14 TSSOP14
2007 - DHVQFN14

Abstract: 74AHCU04 74AHCU04BQ 74AHCU04D 74AHCU04PW JESD22-A114E TSSOP14
Text: 74AHCU04BQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad , configuration DHVQFN14 5.1 Pin description Table 2. Pin description Symbol Pin Description 1A , linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW , inverter DHVQFN14 : plastic dual in-line compatible thermal enhanced very thin quad flat package; no , 02-10-17 03-01-27 Fig 17. Package outline SOT762-1 ( DHVQFN14 ) 74AHCU04_3 Product data sheet


Original
PDF 74AHCU04 74AHCU04 JESD22-A114E: JESD22-A115-A: JESD22-C101C: DHVQFN14 74AHCU04BQ 74AHCU04D 74AHCU04PW JESD22-A114E TSSOP14
2008 - 74HC27

Abstract: dhvqfn14 74HC27N 74HC27D 74HC27DB 74HC27BQ 74HCT27 JESD22-A114E HCT273 74HC27PW
Text: -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762 , 74HCT27BQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762 , . Pin configuration DIP14, SO14, (T)SSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description , package - 750 mW SO14, (T)SSOP14 and DHVQFN14 packages - 500 mW [2] total , packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN14 packages: Ptot derates linearly


Original
PDF 74HC27; 74HCT27 74HCT27 JESD22-A114E JESD22-A115-A 74HC27N DIP14 74HC27 dhvqfn14 74HC27N 74HC27D 74HC27DB 74HC27BQ HCT273 74HC27PW
2007 - dhvqfn14

Abstract: 74HCU04 74LVU04 74LVU04BQ 74LVU04D 74LVU04DB 74LVU04N 74LVU04PW JESD22-A114E
Text: -1 74LVU04BQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad , . Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 6.2 Pin , package [3] - 500 mW (T)SSOP14 package [4] - 500 mW DHVQFN14 package [5 , - 20 December 2007 15 of 19 74LVU04 NXP Semiconductors Hex inverter DHVQFN14 , . Package outline SOT762-1 ( DHVQFN14 ) 74LVU04_6 Product data sheet © NXP B.V. 2007. All rights


Original
PDF 74LVU04 74LVU04 74HCU04. JESD22-A114E JESD22-A115-A dhvqfn14 74HCU04 74LVU04BQ 74LVU04D 74LVU04DB 74LVU04N 74LVU04PW
2007 - 74AHC08PW TSSOP14 NXP

Abstract: dhvqfn14 74AHC08BQ 74AHC08D 74AHC08PW 74AHC08 74AHCT08D 74AHCT08PW JESD22-A114E 74AHCT08
Text: outline package; 14 leads; body width 4.4 mm SOT402-1 -40 °C to +125 °C DHVQFN14 plastic dual , 5. Pin configuration DHVQFN14 74AHC_AHCT08_3 Product data sheet © NXP B.V. 2007. All rights , [2] - 500 mW TSSOP14 package [3] - 500 mW DHVQFN14 package [4] - , Semiconductors Quad 2-input AND gate DHVQFN14 : plastic dual in-line compatible thermal enhanced very thin , ISSUE DATE 02-10-17 03-01-27 Fig 10. Package outline SOT762-1 ( DHVQFN14 ) 74AHC_AHCT08_3 Product


Original
PDF 74AHC08; 74AHCT08 74AHCT08 74AHC08 JESD22-A114E JESD22-A115-A 74AHC08PW TSSOP14 NXP dhvqfn14 74AHC08BQ 74AHC08D 74AHC08PW 74AHCT08D 74AHCT08PW
2007 - 74HC132

Abstract: 74HCT132 74LV132 74LV132BQ 74LV132D 74LV132DB 74LV132N 74LV132PW JESD22-A114E
Text: mm SOT402-1 74LV132BQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal , , SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 6.2 Pin description Table 2. Pin , DHVQFN14 package [5] - 500 mW [1] The input and output voltage ratings may be exceeded if , Semiconductors Quad 2-input NAND Schmitt trigger DHVQFN14 : plastic dual in-line compatible thermal enhanced , PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 17. Package outline SOT762-1 ( DHVQFN14 ) 74LV132_4


Original
PDF 74LV132 74LV132 74HC132 74HCT132. 74HCT132 74LV132BQ 74LV132D 74LV132DB 74LV132N 74LV132PW JESD22-A114E
2008 - dhvqfn14

Abstract: 076E06 74AHCT02PW 74AHCT02D 74AHCT02 74AHC02PW 74AHC02D 74AHC02BQ 74AHC02 JESD22-A114E
Text: outline package; 14 leads; body width 4.4 mm SOT402-1 -40 °C to +125 °C DHVQFN14 plastic dual , 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin , package [3] - 500 mW DHVQFN14 package [4] - 500 mW [1] The input and , DHVQFN14 : plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762 , Fig 10. Package outline SOT762-1 ( DHVQFN14 ) 74AHC_AHCT02_3 Product data sheet © NXP B.V. 2008


Original
PDF 74AHC02; 74AHCT02 74AHCT02 74AHC02 JESD22-A114E JESD22-A115-A dhvqfn14 076E06 74AHCT02PW 74AHCT02D 74AHC02PW 74AHC02D 74AHC02BQ
2008 - 74ALVC125

Abstract: 74ALVC125BQ 74ALVC125D 74ALVC125PW JESD22-A114E TSSOP14
Text: SOT402-1 74ALVC125PW -40 °C to +85 °C 74ALVC125BQ -40 °C to +85 °C DHVQFN14 plastic dual , . Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 74ALVC125_2 , -state DHVQFN14 : plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762 , Fig 11. Package outline SOT762-1 ( DHVQFN14 ) 74ALVC125_2 Product data sheet © NXP B.V. 2008. All , appropriate. Section 3: DHVQFN14 package added. Section 7: derating values added for DHVQFN14 package


Original
PDF 74ALVC125 74ALVC125 JESD8B/JESD36 74ALVC125BQ 74ALVC125D 74ALVC125PW JESD22-A114E TSSOP14
2003 - dhvqfn14

Abstract: SV00418 04482
Text: configuration (SO14, SSOP14, TSSOP14) SV01923 Figure 2. Pin configuration ( DHVQFN14 ; top view) 2003 Apr , 74LVC10A DHVQFN14 : plastic dual in-line compatible thermal enhanced very thin quad flat package; no , DHVQFN14 package to Ordering Information table; add DHVQFN14 pin configuration drawing; add DHVQFN14


Original
PDF 74LVC10A 74LVC10A dhvqfn14 SV00418 04482
2007 - 74HC86

Abstract: 74HCT86 74LV86 74LV86BQ 74LV86D 74LV86DB 74LV86N 74LV86PW JESD22-A114E
Text: -1 74LV86BQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad , configuration DHVQFN14 74LV86_3 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 03 - , ] - 500 mW DHVQFN14 package [1] [2] [5] - 500 mW The input and output , Semiconductors Quad 2-input exclusive-OR gate DHVQFN14 : plastic dual in-line compatible thermal enhanced , PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline SOT762-1 ( DHVQFN14 ) 74LV86_3


Original
PDF 74LV86 74LV86 74HC86 74HCT86. JESD22-A114E JESD22-A115-A 74HCT86 74LV86BQ 74LV86D 74LV86DB 74LV86N 74LV86PW
2007 - 74HC00

Abstract: JESD22-A114E 74LV00PW 74LV00N 74LV00DB 74LV00D 74LV00BQ 74LV00 74HCT00 74LV001
Text: DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 , )SSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol , (T)SSOP14 package [4] - 500 mW DHVQFN14 package [1] [2] [5] - 500 mW , Quad 2-input NAND gate DHVQFN14 : plastic dual in-line compatible thermal enhanced very thin quad , 02-10-17 03-01-27 Fig 12. Package outline SOT762-1 ( DHVQFN14 ) 74LV00_3 Product data sheet © NXP


Original
PDF 74LV00 74LV00 74HC00 74HCT00. JESD22-A114E JESD22-A115-A 74LV00PW 74LV00N 74LV00DB 74LV00D 74LV00BQ 74HCT00 74LV001
2007 - dhvqfn14

Abstract: 74HC32 74HCT32 74LV32 74LV32D 74LV32DB 74LV32N 74LV32PW JESD22-A114E
Text: DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 , . Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 74LV32_3 , package [3] - 500 mW (T)SSOP14 package [4] - 500 mW DHVQFN14 package [1 , 9 November 2007 11 of 15 74LV32 NXP Semiconductors Quad 2-input OR gate DHVQFN14 , . Package outline SOT762-1 ( DHVQFN14 ) 74LV32_3 Product data sheet © NXP B.V. 2007. All rights


Original
PDF 74LV32 74LV32 74HC32 74HCT32. JESD22-A114E JESD22-A115-A dhvqfn14 74HCT32 74LV32D 74LV32DB 74LV32N 74LV32PW
2009 - dhvqfn14

Abstract: 74AHC30 74AHC30D 74AHC30PW 74AHCT30 74AHCT30D 74AHCT30PW JESD22-A114E
Text: -1 -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin , configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description A , : above 60 °C the value of Ptot derates linearly at 5.5 mW/K. For DHVQFN14 packages: above 60 °C the , -input NAND gate DHVQFN14 : plastic dual in-line compatible thermal enhanced very thin quad flat package; no , 02-10-17 03-01-27 Fig 10. Package outline SOT762-1 ( DHVQFN14 ) 74AHC_AHCT30_3 Product data sheet


Original
PDF 74AHC30; 74AHCT30 74AHCT30 74AHC30: 74AHCT30: JESD22-A114E JESD22-A115-A dhvqfn14 74AHC30 74AHC30D 74AHC30PW 74AHCT30D 74AHCT30PW
2009 - 74hc05

Abstract: 74HC05 datasheet tssop14 nxp 74HC05D DHVQFN14 JESD22-A114E TSSOP14
Text: +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat , . Pin configuration SOT402-1 (TSSOP14) Fig 5. Pin configuration SOT762-1 ( DHVQFN14 ) 5.2 Pin , DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 °C. 8. Recommended operating conditions , DHVQFN14 : plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762 , Fig 10. Package outline SOT762-1 ( DHVQFN14 ) 74HC05_2 Product data sheet © NXP B.V. 2009. All


Original
PDF 74HC05 74HC05 74HC05: JESD22-A114E JESD22-C101C 74HC05 datasheet tssop14 nxp 74HC05D DHVQFN14 TSSOP14
2007 - nxp 74hct14

Abstract: 74LV14D nxp 74LV14N JESD22-A114E 74LV14PW 74LV14DB 74LV14D 74LV14BQ 74LV14 74HCT14
Text: -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat , , SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 6.2 Pin description Table 2. Pin , (T)SSOP14 package [4] - 500 mW DHVQFN14 package [1] [2] [5] - 500 mW , Schmitt trigger DHVQFN14 : plastic dual in-line compatible thermal enhanced very thin quad flat package , 02-10-17 03-01-27 Fig 19. Package outline SOT762-1 ( DHVQFN14 ) 74LV14_3 Product data sheet © NXP


Original
PDF 74LV14 74LV14 74HC14 74HCT14. nxp 74hct14 74LV14D nxp 74LV14N JESD22-A114E 74LV14PW 74LV14DB 74LV14D 74LV14BQ 74HCT14
2008 - ahct125

Abstract: NA1211 74AHC125 datasheet dhvqfn14 74AHC125PW 74AHC126 74AHC125D 74AHCT125D 74AHCT126 JESD22-A114E
Text: leads; body width 4.4 mm SOT402-1 -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible , TSSOP14 Fig 5. Pin configuration DHVQFN14 74AHC_AHCT125_4 Product data sheet © NXP B.V. 2008 , [3] - 500 mW DHVQFN14 package [4] - 500 mW [1] The input and output , driver; 3-state DHVQFN14 : plastic dual in-line compatible thermal enhanced very thin quad flat package , 02-10-17 03-01-27 Fig 11. Package outline SOT762-1 ( DHVQFN14 ) 74AHC_AHCT125_4 Product data sheet


Original
PDF 74AHC125; 74AHCT125 74AHCT125 74AHC126; 74AHCT126 ahct125 NA1211 74AHC125 datasheet dhvqfn14 74AHC125PW 74AHC126 74AHC125D 74AHCT125D JESD22-A114E
2007 - dhvqfn14

Abstract: JESD22-A114E 74AHCT86PW 74AHCT86D 74AHCT86 74AHC86PW 74AHC86D 74AHC86BQ 74AHC86 AHCT86
Text: shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 -40 °C to +125 °C DHVQFN14 , . Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin , mW DHVQFN14 package [4] - 500 mW [1] The input and output voltage ratings may be , Semiconductors Quad 2-input EXCLUSIVE-OR gate DHVQFN14 : plastic dual in-line compatible thermal enhanced , PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 10. Package outline SOT762-1 ( DHVQFN14 ) 74AHC


Original
PDF 74AHC86; 74AHCT86 74AHCT86 74AHC86 JESD22-A114E JESD22-A115-A dhvqfn14 74AHCT86PW 74AHCT86D 74AHC86PW 74AHC86D 74AHC86BQ AHCT86
2007 - Not Available

Abstract: No abstract text available
Text: -1 -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat , configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 5.1 Pin description Table 2. Symbol 1A , : above 60 °C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C the , Semiconductors 74AHCU04 Hex inverter DHVQFN14 : plastic dual in-line compatible thermal enhanced very thin , PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 17. Package outline SOT762-1 ( DHVQFN14 ) 74AHCU04_3 © NXP B.V


Original
PDF 74AHCU04 74AHCU04 JESD22-A114E: JESD22-A115-A: JESD22-C101C: 74AHCU04D 74AH13
Supplyframe Tracking Pixel