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DDR333 datasheet (1)

Part ECAD Model Manufacturer Description Type PDF
DDR333 DDR333 ECAD Model Infineon Technologies Memory DRAM Modules Original PDF

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2005 - DDR333

Abstract: micron ddr TN-46-13 DDR400 DDR200 DDR266 MT46V64M8
Text: ) Micron DDR SDRAM DDR333 DDR400 DDR333 1 333 M , JEDEC AC DDR200 JEDEC tRCD (Row-to-Column delay ) 20ns DDR333 18ns tRCD ( 1 ) DDR200 tRCD 2 DDR333 3 PDF , TN-46-13 DDR SDRAM AC 1 JEDEC DDR200 DDR333 tRCD t RCD , = 3 x 7.5ns) DDR333 18ns tRCD 3 (18ns / 6ns = 3 ) DDR266 18ns


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PDF TN-46-13 MT46V64M8) DDR200 DDR266 DDR333 DDR400 09005aef81c057dd/Source: DDR333 micron ddr TN-46-13 DDR400 DDR200 DDR266 MT46V64M8
2007 - sdram pcb layout guide

Abstract: vhdl code for sdr sdram controller memory Controller FPGA EC20 TN1050 samsung K4 ddr dqs detect DDR400 infineon sdr sdram pcb layout guidelines 256MX4
Text: No file text available


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PDF TN1050 200MHz LatticeEC20 sdram pcb layout guide vhdl code for sdr sdram controller memory Controller FPGA EC20 TN1050 samsung K4 ddr dqs detect DDR400 infineon sdr sdram pcb layout guidelines 256MX4
2001 - 256mb ddr333 200 pin

Abstract: A11 MARKING CODE mark DM 8M16 DDR200 DDR266 DDR333 MT46V16M8 MT46V32M4 MT46V8M16
Text: Timing - Cycle Time 6ns @ CL = 2.5 ( DDR333B­FBGA )1 6ns @ CL = 2.5 ( DDR333B­TSOP )1 7.5ns @ CL = 2 , utilized for DDR333. This JEDEC-defined package promotes better package parasitic parameters and a smaller , PRELIMINARY 128Mb: x4, x8, x16 DDR333 SDRAM Addendum MT46V32M4 ­ 8 Meg x 4 x 4 banks , FEATURES DDR333 COMPATIBILITY · 167 MHz Clock, 333 Mb/s/p data rate · VDD = +2.5V ±0.2V, VDDQ = , with DDR200 and DDR266 DDR333 meets or surpasses all DDR266 timing requirements thus assuring full


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PDF 128Mb: DDR333 MT46V32M4 MT46V16M8 MT46V8M16 256Mb: 256mb ddr333 200 pin A11 MARKING CODE mark DM 8M16 DDR200 DDR266 MT46V16M8 MT46V32M4 MT46V8M16
2001 - MT46V16M16

Abstract: No abstract text available
Text: -Ball FBGA (16x9mm) · Timing - Cycle Time 6ns @ CL = 2.5 ( DDR333B­FBGA )1 6ns @ CL = 2.5 ( DDR333B­TSOP )1 7.5ns , package, a 60-ball FBGA package is utilized for DDR333. This JEDEC-defined package promotes better package , PRELIMINARY 256Mb: x4, x8, x16 DDR333 SDRAM Addendum DOUBLE DATA RATE (DDR) SDRAM FEATURES , revisions, please refer to the Micron Web site: www.micron.com/dramds DDR333 COMPATIBILITY DDR333 meets , improved timing performance. The 256Mb, DDR333 device will support an (tREFI) average periodic refresh


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PDF 256Mb: DDR333 lengtDDR333 256Mx4x8x16DDR333 MT46V16M16
H9ccnnn

Abstract: H9CKNNNB H5MS1G22AFRE3M H5MS2G22MFR-J3M H5MS2G62 H55S2622JFR-60M H9TKNNN2GDMP-LRNDM DDR333 H5MS2G62AFR-J3M H5MS1G22AFR-E3M
Text: FBGA(60ball) 4Bank, 1.8V/ 1.8V Now DDR333 H5MS2G62MFR-J3M FBGA(60ball) 4Bank, 1.8V/ 1.8V Now DDR400 H5MS2G62AFR-EBM FBGA(60ball) 4Bank, 1.8V/ 1.8V Now DDR333 , , 1.8V/ 1.8V Now DDR333 H5MS2G32BFR-J3M FBGA(90ball) 4Bank, 1.8V/ 1.8V Now DDR400 H5MS2G22MFR-EBM FBGA(90ball) 4Bank, 1.8V/ 1.8V Now DDR333 H5MS2G22MFR-J3M FBGA(90ball) 4Bank, 1.8V/ 1.8V Now DDR400 H5MS2G22AFR-EBM FBGA(90ball) 4Bank, 1.8V/ 1.8V Now DDR333


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PDF 166MHz H55S2G62MFP-60M 54ball) 133MHz H55S2G62MFP-75M H55S2G22MFP-60M 90ball) H9ccnnn H9CKNNNB H5MS1G22AFRE3M H5MS2G22MFR-J3M H5MS2G62 H55S2622JFR-60M H9TKNNN2GDMP-LRNDM DDR333 H5MS2G62AFR-J3M H5MS1G22AFR-E3M
HYB25D512400BG

Abstract: LFXP20C samsung K4 ddr TN1050 EC20 DDR-266 mt46v8m16 lfxp6c
Text: Max Data Rate Clock Speed 32Mx4 DDR266 MT46V16M8TG 16Mx8 DDR333 DDR266 133MHz , MT46V128M4FN MT46V128M4TG Micron 512MB 16Mx16 32Mx16 9-32 DDR333 DDR266 DDR400 DDR333 DDR266 DDR400 DDR333 DDR266 DDR400 200MHz 167MHz 133MHz 200MHz 167MHz 133MHz DDR333 DDR266 200MHz 167MHz 133MHz DDR266 133MHz DDR400 200MHz 167MHz 133MHz DDR333 DDR266 DDR400 DDR333 DDR266 200MHz 167MHz 133MHz DDR266 133MHz DDR400 200MHz 167MHz 133MHz DDR333 DDR266


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PDF TN1050 DQSFPGA90 90DQDQS 9-29-3DQDQS/ SDRAMDQSx8x16x32 DQS8DDR10 I/O1DQS8DQ1DMLatticeECP/ECLatticeXP16I/O DQSLatticeXP14I/ODQS 200MHzREAD HYB25D512400BG LFXP20C samsung K4 ddr EC20 DDR-266 mt46v8m16 lfxp6c
2001 - MT46V16M16

Abstract: 66 pin tsop package DDR200 DDR266 DDR333 MT46V32M8 MT46V64M4 256mb ddr333 200 pin
Text: Timing - Cycle Time 6ns @ CL = 2.5 ( DDR333B­FBGA )1 6ns @ CL = 2.5 ( DDR333B­TSOP )1 7.5ns @ CL = 2 , -pin TSOP package, a 60-ball FBGA package is utilized for DDR333. This JEDEC-defined package promotes , PRELIMINARY 256Mb: x4, x8, x16 DDR333 SDRAM Addendum MT46V64M4 ­ 16 Meg x 4 x 4 banks , FEATURES DDR333 COMPATIBILITY · 167 MHz Clock, 333 Mb/s/p data rate · VDD = +2.5V ±0.2V, VDDQ = , with DDR200 and DDR266 DDR333 meets or surpasses all DDR266 timing requirements thus assuring full


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PDF 256Mb: DDR333 MT46V64M4 MT46V32M8 MT46V16M16 MT46V16M16 66 pin tsop package DDR200 DDR266 MT46V32M8 MT46V64M4 256mb ddr333 200 pin
2001 - 256mb ddr333 200 pin

Abstract: mark DM 8M16 DDR200 DDR266 DDR333 MT46V16M8 MT46V32M4 MT46V8M16
Text: Timing - Cycle Time 6ns @ CL = 2.5 ( DDR333B­FBGA )1 6ns @ CL = 2.5 ( DDR333B­TSOP )1 7.5ns @ CL = 2 , utilized for DDR333. This JEDEC-defined package promotes better package parasitic parameters and a smaller , PRELIMINARY 128Mb: x4, x8, x16 DDR333 SDRAM Addendum MT46V32M4 ­ 8 Meg x 4 x 4 banks , FEATURES DDR333 COMPATIBILITY · 167 MHz Clock, 333 Mb/s/p data rate · VDD = +2.5V ±0.2V, VDDQ = , with DDR200 and DDR266 DDR333 meets or surpasses all DDR266 timing requirements thus assuring full


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PDF 128Mb: DDR333 MT46V32M4 MT46V16M8 MT46V8M16 256Mb: 256mb ddr333 200 pin mark DM 8M16 DDR200 DDR266 MT46V16M8 MT46V32M4 MT46V8M16
2001 - 75Z MARKING

Abstract: No abstract text available
Text: (16x9mm) · Timing - Cycle Time 6ns @ CL = 2.5 ( DDR333B­FBGA )1 6ns @ CL = 2.5 ( DDR333B­TSOP )1 7.5ns @ CL = , the standard 66-pin TSOP package, a 60-ball FBGA package is utilized for DDR333. This JEDEC-defined , PRELIMINARY 128Mb: x4, x8, x16 DDR333 SDRAM Addendum DOUBLE DATA RATE (DDR) SDRAM FEATURES , revisions, please refer to the Micron Web site: www.micron.com/dramds DDR333 COMPATIBILITY DDR333 meets , improved timing performance. The 128Mb, DDR333 device will support an (tREFI) average periodic refresh


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PDF 128Mb: DDR333 256Mb: 128Mx4x8x16DDR333 75Z MARKING
2001 - 256mb ddr333 200 pin

Abstract: MT46V16M16
Text: -Ball FBGA (16x9mm) · Timing - Cycle Time 6ns @ CL = 2.5 ( DDR333B­FBGA )1 6ns @ CL = 2.5 ( DDR333B­TSOP )1 7.5ns , -pin TSOP package, a 60-ball FBGA package is utilized for DDR333. This JEDEC-defined package promotes better , PRELIMINARY 256Mb: x4, x8, x16 DDR333 SDRAM Addendum DOUBLE DATA RATE (DDR) SDRAM FEATURES , revisions, please refer to the Micron Web site: www.micron.com/dramds DDR333 COMPATIBILITY DDR333 meets , improved timing performance. The 256Mb, DDR333 device will support an (tREFI) average periodic refresh


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PDF 256Mb: DDR333 lenDDR333 256Mx4x8x16DDR333 256mb ddr333 200 pin MT46V16M16
2003 - Not Available

Abstract: No abstract text available
Text: -75B NT128D64SH4B0GM-75B REV 1.1 12/19/2003 Preliminary Speed DDR400A DDR400B DDR333 DDR266B , / DDR333 /400A) CL=3 (DDR400B) DDR SDRAM Device Access Time from Clock 10 CL=2.5 (DDR266B/ DDR333 /400A) CL=3 (DDR400B) SSTL 2.5V 04 DDR266B 7.5ns 75 DDR333 6.0ns 60 5.0ns 50 DDR266B 0.75ns 75 DDR333 0.70ns 70 0.60ns 60 DDR400A DDR400B , : DDR333 2/2.5 0C CAS Latencies Supported DDR400A 2/2.5 0C DDR400B 18 2.5/3


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PDF NT128D64SH4B0GM NT128D64SH4BBGM 128MB PC3200 PC2700 PC2100 DDR400/333/266 16Mx16 200-Pin 16Mx64
2000 - 66 pin tsop package

Abstract: 256mb ddr333 200 pin
Text: the standard 66-pin TSOP package, a 60-ball FBGA package is utilized for DDR333. This JEDEC-defined , PREVIEW 256Mb: x4, x8, x16 DDR333 SDRAM Addendum DOUBLE DATA RATE (DDR) SDRAM FEATURES · , to the Micron Web site: www.micron.com/dramds DDR333 COMPATIBILITY DDR333 meets or surpasses all , . The 256Mb, DDR333 device will support an (tREFI) average periodic refresh interval of 7.8us. The , ( DDR333B )1 6ns @ CL = 3 7.5ns @ CL = 2 (DDR266A)2 7.5ns @ CL = 2.5 (DDR266B)3 · Self Refresh Standard NOTE


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PDF 256Mb: DDR333 256Mx4x8x16DDR333 66 pin tsop package 256mb ddr333 200 pin
2003 - SSTV16857

Abstract: DDR 333 pc2700 RDIMM PC2100 SN74SSTV32867 SN74SSTV32877 SN74SSTVF16857 SSTVF16857 a2b 340
Text: ( DDR-333 ) RDIMMs Tomdio Nana and Roland Pang Standard Linear & Logic ABSTRACT The high-capacity , PC2700 RDIMM ( DDR-333 ) applications during simultaneous switching. This application report discusses the , design a planar PC2700 RDIMM. Keywords: 1U, 2.5 V, buffer, DDR, DDR-333 , DIMM, RDIMM, low profile , SN74SSTVF16857 in Planar PC2700 ( DDR-333 ) RDIMMs SCEA031 1 Introduction The increasing demand for more , PC2700 ( DDR-333 ) planar RDIMMs. The SN74SSTV16859, SN74SSTVF16859, SN74SSTV32852 and SN74SSTVF32852 are


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PDF SCEA031 SN74SSTVF16857 PC2700 DDR-333) SSTV168reproduction SSTV16857 DDR 333 pc2700 RDIMM PC2100 SN74SSTV32867 SN74SSTV32877 SN74SSTVF16857 SSTVF16857 a2b 340
2003 - Not Available

Abstract: No abstract text available
Text: -Pin TSOP (OCPL) Lead-Free 60-Ball FBGA (16x9mm) • Timing - Cycle Time 6ns @ CL = 2.5 ( DDR333B–FBGA )1 6ns @ CL = 2.5 ( DDR333B–TSOP )1 7.5ns @ CL = 2 (DDR266A)2 • Self Refresh Standard 32 Meg x 4 , -pin TSOP package, a 60-ball FBGA package is utilized for DDR333. This JEDEC-defined package promotes , PRELIMINARY‡ 128Mb: x4, x8, x16 DDR333 SDRAM Addendum MT46V32M4 – 8 Meg x 4 x 4 banks , FEATURES DDR333 COMPATIBILITY • 167 MHz Clock, 333 Mb/s/p data rate • VDD = +2.5V ±0.2V, VDDQ =


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PDF 128Mb: DDR333 MT46V32M4 MT46V16M8 MT46V8M16 256Mb: 128Mx4x8x16DDR333
2003 - Not Available

Abstract: No abstract text available
Text: 200PIN DDR333 Unbuffered SO-DIMM 512MB With 32Mx8 CL2.5 TS64MSD64V3F Description Placement The TS64MSD64V3F is a 64M x 64bits Double Data Rate SDRAM high-density for DDR333. The TS64MSD64V3F , . 1 E K 200PIN DDR333 Unbuffered SO-DIMM 512MB With 32Mx8 CL2.5 TS64MSD64V3F Dimensions , Clock SDA Transcend Information Inc. Address in EEPROM No Connection 200PIN DDR333 , 200PIN DDR333 Unbuffered SO-DIMM 512MB With 32Mx8 CL2.5 TS64MSD64V3F Block Diagram A0~A12, BA0


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PDF 200PIN DDR333 512MB 32Mx8 TS64MSD64V3F TS64MSD64V3F 64bits DDR333. 16pcs
2006 - Not Available

Abstract: No abstract text available
Text: 200PIN DDR333 Unbuffered SO-DIMM 512MB With 32Mx8 CL2.5 TS64MSD72V3F Description Placement The TS64MSD72V3F is a 64M x 72bits Double Data Rate SDRAM high-density for DDR333. The TS64MSD72V3F , & Interleave) Transcend Information Inc. 1 C K L 200PIN DDR333 Unbuffered SO-DIMM , Transcend Information Inc. Address in EEPROM No Connection 200PIN DDR333 Unbuffered SO-DIMM 512MB , DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU 200PIN DDR333


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PDF 200PIN DDR333 512MB 32Mx8 TS64MSD72V3F TS64MSD72V3F 72bits DDR333. 18pcs
RG82845GV

Abstract: RG82845GV SL6PU rg82845g rg82845gl QD18 RG82845gv pin details QD73 PC133 registered reference design QD66 82845GV
Text: chipset Added Specification Change C1, 82845GV Adds DDR333 Capability Added Erratum #A2,B2,C2, VGA Panning , ,B3,C3, VGA Timing -005 -006 (1) (1) (2) Added Specification Change C2, 82845GV Adds DDR333 Capability , CHANGES 82845GV Adds DDR333 Capability 82845GV Adds DDR333 Capability Only at FSB 533 MHz NO. 1 A2,B2 , /82845GV GMCH Specification Changes C1 82845GV Adds DDR333 Capability Reference the Intel® 845G/845GL , (DDR) SDRAM Configuration", add a line which says " DDR333 unregistered, 184-pin non-ECC DDR SDRAM DIMMS


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PDF 845G/845GL/845GV 82845G/82845GL/82845GV 82845GL 82845GV 82845G RG82845GV RG82845GV SL6PU rg82845g rg82845gl QD18 RG82845gv pin details QD73 PC133 registered reference design QD66
2003 - DDR400B

Abstract: No abstract text available
Text: -6K NT256D64SH8BAGM-75B NT256D64SH8B0GM-75B DDR333 DDR266B REV 1.1 12/19/2003 1 NANYA reserves the right , ') Voltage Interface Level of this Assembly DDR SDRAM Device Cycle Time 9 CL=2.5 (DDR266B/ DDR333 /400A) CL=3 (DDR400B) DDR SDRAM Device Access Time from Clock 10 CL=2.5 (DDR266B/ DDR333 /400A) CL=3 (DDR400B) 11 12 13 , =2.5 (DDR266B/ DDR333 /400A) CL=3 (DDR400B) Maximum Data Access Time from Clock at 24 CL=2 (DDR266B/ DDR333 /400A) CL=2.5 (DDR400B) DDR266B/333 DDR400A/B DDR266B DDR333 DDR400A DDR400B DDR266B DDR333 DDR400A DDR400B


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PDF NT256D64SH8B0GM NT256D64SH8BAGM 256MB PC3200 PC2700 PC2100 DDR400/333/266 16Mx16 200-Pin 32Mx64 DDR400B
2000 - 256mb ddr333

Abstract: No abstract text available
Text: NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333 SDRAM Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz)* DDR333 (-6) 133 166 · Double data rate , . NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333 SDRAM Pin Configuration - 400mil TSOP II , NT5DS32M8AT NT5DS32M8AW 256Mb DDR333 SDRAM Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package NT5DS32M8AW 256Mb DDR333 SDRAM Input/Output Functional Description Symbol CK, CK Type Input Function


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PDF NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333 DDR333 256mb ddr333
HYMP512S64CP8-Y5

Abstract: HYMP564S64CP6-Y5 H5TQ1G63BFR-H9C h5ps2g83afr-s6c H5PS1G63EFR-Y5C H5TQ1G83BFR-H9C HYMP564S64CP6-C4 HY5PS121621Cfp-y5 H5PS1G63EFR-S5C HY5PS12821CFP-Y5
Text: 128MX72 (ECC) BASED COMPONENT 64MX8 SPEED DDR400 DDR333 DDR266B 128MX64 64MX8 DDR400 DDR333 DDR266B 64Mx72 64MX8 DDR400 DDR333 DDR266B 32MX8 DDR400 DDR333 DDR266A 512MB 64MX72 (ECC) 64MX64 32Mx8 DDR266B 64MX8 DDR400 DDR333 DDR266B 32Mx8 DDR500 DDR400 DDR333 DDR266A DDR266B PART NUMBER HYMD512726A8J-D43 HYMD512726B(P)8J , ECC DDR333 DDR266A DDR266B 32Mx64 32Mx8 DDR333 DDR266A DDR266B 16Mx16


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PDF 256Mx4 H5TQ1G43AFP-H9C 78ball) H5TQ1G43BFR-H9C H5TQ1G43TFR-H9C H5TQ1G43AFP-G7C H5TQ1G43BFR-G7C HYMP512S64CP8-Y5 HYMP564S64CP6-Y5 H5TQ1G63BFR-H9C h5ps2g83afr-s6c H5PS1G63EFR-Y5C H5TQ1G83BFR-H9C HYMP564S64CP6-C4 HY5PS121621Cfp-y5 H5PS1G63EFR-S5C HY5PS12821CFP-Y5
2003 - DDR333

Abstract: NT5DS32M8AT NT5DS32M8AT-6 NT5DS32M8AW NT5DS32M8AW-6 NT5DS64M4AT NT5DS64M4AT-6 NT5DS64M4AW NT5DS64M4AW-6 256mb ddr333 200 pin
Text: NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333 SDRAM Features · Data mask (DM , Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR333 (-6) 133 166 · Double data , 256Mb DDR333 SDRAM Pin Configuration - 400mil TSOP II VDD VDD 1 66 VSS VSS NC , . NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333 SDRAM Pin Configuration - 60 balls , Specifications without notice. NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333 SDRAM


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PDF NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333 66pin DDR333 NT5DS32M8AT-6 NT5DS32M8AW NT5DS32M8AW-6 NT5DS64M4AT-6 NT5DS64M4AW NT5DS64M4AW-6 256mb ddr333 200 pin
2002 - 256mb ddr333

Abstract: DDR333 NT5DS32M8AT NT5DS32M8AT-6 NT5DS32M8AW NT5DS32M8AW-6 NT5DS64M4AT NT5DS64M4AT-6 NT5DS64M4AW NT5DS64M4AW-6
Text: NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333 SDRAM Features · Data mask (DM , Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR333 (-6) 133 166 · Double data , NT5DS32M8AW 256Mb DDR333 SDRAM Pin Configuration - 400mil TSOP II VDD VDD 1 66 VSS VSS , . NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333 SDRAM Pin Configuration - 60 balls , TECHNOLOGY CORP. All rights reserved. NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333


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PDF NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333 66pin DDR333 256mb ddr333 NT5DS32M8AT-6 NT5DS32M8AW NT5DS32M8AW-6 NT5DS64M4AT-6 NT5DS64M4AW NT5DS64M4AW-6
2010 - EDJ2116DASE

Abstract: EDE2116ACBG ECM220ACBCN ELPIDA EDJ2116DASE EDJ1108DBSE EDE1032AGBG GDDR5 EDX1032BASE DDR3-1333H EDE1116AGBG
Text: 128M x 16 4 DDR400(3-3-3) DDR333 (3-3-3) EDD20161ABH 5BTS-F 1.8+0.15/-0.1V 6ETS-F 4 DDR400(3-3-3) DDR333 (3-3-3) EDD20163ABH 5BTS-F 6ETS-F 4 DDR400(3-3-3) DDR333 (3-3-3) EDD20321ABH 4 DDR400(3-3-3) DDR333 (3-3-3) EDD20323ABH 5BTS-F 6ETS-F 5BLS-F 6ELS-F 4 DDR400(3-3-3) DDR333 (3-3-3) EDD10161BBH 4 DDR400(3-3-3) DDR333 (3-3-3) EDD10163BBH 4 DDR400(3-3-3) DDR333 (3-3-3) EDD10321BBH 4 DDR400(3-3-3) DDR333 (3-3-3) EDD10323BBH 4


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PDF J1610E30 240-pin EDU1032AABG 136-FBGA M01J0706 TEL033281-1563 TEL066390-8727 EDJ2116DASE EDE2116ACBG ECM220ACBCN ELPIDA EDJ2116DASE EDJ1108DBSE EDE1032AGBG GDDR5 EDX1032BASE DDR3-1333H EDE1116AGBG
2005 - Not Available

Abstract: No abstract text available
Text: 184PIN DDR333 ECC Unbuffered DIMM 512MB With 32Mx8 CL2.5 TS64MLD72V3F5 Description Placement The TS64MLD72V3F5 is a 64Mx72bits Double Data Rate SDRAM high density for DDR333. The , 184PIN DDR333 ECC Unbuffered DIMM 512MB With 32Mx8 CL2.5 TS64MLD72V3F5 Dimensions Pin , DDR333 ECC Unbuffered DIMM 512MB With 32Mx8 CL2.5 TS64MLD72V3F5 Pinouts: Pin Pin Pin No Name , SA1 SA2 VDDSPD 184PIN DDR333 ECC Unbuffered DIMM 512MB With 32Mx8 CL2.5 TS64MLD72V3F5 Block


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PDF 184PIN DDR333 512MB 32Mx8 TS64MLD72V3F5 TS64MLD72V3F5 64Mx72bits DDR333. 18pcs
2005 - Not Available

Abstract: No abstract text available
Text: 184PIN DDR333 Unbuffered DIMM 128MB With 16Mx16 CL2.5 TS16MLD64V3G Description Placement The TS16MLD64V3G is a 16M x 64bits Double Data Rate SDRAM high-density for DDR333.The , (2,4,8 ) Data Sequence (Sequential & Interleave) Transcend Information Inc. 1 184PIN DDR333 , Transcend Information Inc. Address in EEPROM No Connection 184PIN DDR333 Unbuffered DIMM 128MB , DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD 184PIN DDR333


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PDF 184PIN DDR333 128MB 16Mx16 TS16MLD64V3G TS16MLD64V3G 64bits
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