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    hynix dram numbering

    Abstract: DDR266A 200pin SO DIMM ddr 200pin SO DIMM HYMR26416H-XXX hynix hy 16MX8 HY5DV
    Text: DDR266A /B, DDR201 DDR266AVB , DDR200 DDR266B.DDR200 DDR266A /B, DDR200 DDR266B, DDR200 DDR266A /B,DDR200 , 200MHz 183MHz 166MHz DDR266A DDR266B DDR200 POWER CONSUMPTION DATA WIDTH & FEATURES 4 8 16 32 : x4 , ,16)22T SSTL-2 SSTL-2 SSTL-2 300/250/222 DDR266A /B, DDR200 DDR266A /B, DDR200 144ball FBGA 66pin , /233/200/183 DDR266B.DDR200 DDR266A /B, DDR200 100pin LQFP 100pin LQFP 66pin TSOP-II 66pin TSOP-II 2K , DDR266A /B, DDR200 DDR266B, DDR200 DDR266A /B, DDR200 DDR266A /B, DDR200 DDR266B, DDR200 DDR266A /B.DDR200


    OCR Scan     		PDF 300MHz 275MHz 250MHz 233MHz 222MHz 200MHz 183MHz 166MHz DDR266A DDR266B hynix dram numbering 200pin SO DIMM ddr 200pin SO DIMM HYMR26416H-XXX hynix hy 16MX8 HY5DV
    2007 - DDR333

    Abstract: PC2700 WV3EG216M64STSU-D4 DDR266A
    Text: ActivePrecharge ICC0* tRC = tRC(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS , * All banks idle; power - down mode; CKE = DDR266A & , # > = VIH(min);All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B , = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM 280 mA , precharge; tRC = tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs


    Original     		PDF WV3EG216M64STSU-D4 256MB 2x16Mx64 WV3EG216M64STSU 16Mx16 PC2700 DDR333 WV3EG216M64STSU-D4 DDR266A
    2003 - q1257

    Abstract: Q1129 Q4331 TSOP66 Q4311 tsop 4021 tsop ddr2 ram DDR RAM 512M DRAM spectrum infineon TSOP-66
    Text: DDR266A 2-3-3 / PC133 2-2-2 DDR266 2-2-2 DDR266B 2.5-3-3 / PC133 3-3-3 DDR200 2-2-2 / PC100 2-2-2 , ) 64Mx4 TSOP-66 (400mil) Latency DDR200 2-2-2 DDR266A 2-3-3 DDR266A 2-3-3 2-3-3 DDR333 2.5-3-3 DDR266A 256 Mb DDR266A 2-3-3 DDR266 2-2-2 DDR266A TSOP , DDR266A FBGA 64Mx4 FBGA 60 (12x8mm) 3-3-3 DDR266A 256 Mb 2.5-3-3 2-3-3 DDR333 , Q67100 Q4770 DDR266A SD = Stacked Die FBGA 60 (12x8mm) X = Lead-Free 2-3-3 DDR333


    Original     		PDF 2002791-D-RAM hoch17 DDR400 PC3200) B112-H6731-G10-X-7600 q1257 Q1129 Q4331 TSOP66 Q4311 tsop 4021 tsop ddr2 ram DDR RAM 512M DRAM spectrum infineon TSOP-66
    2005 - DDR266A

    Abstract: DDR266B TSOP 173 g DDR333 PC2700 WV3EG216M64STSU-D4
    Text: ActivePrecharge IDD0* tRC = tRC(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS , * All banks idle; power - down mode; CKE = DDR266A & , # > = VIH(min);All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B , = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM 280 mA , precharge; tRC = tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs


    Original     		PDF WV3EG216M64STSU-D4 256MB 2x16Mx64 WV3EG216M64STSU 16Mx16 PC2700 DDR266A DDR266B TSOP 173 g DDR333 WV3EG216M64STSU-D4
    2001 - M383L1713CT1

    Abstract: No abstract text available
    Text: DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and , =100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - , , 133Mhz for DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; Vin = , banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other , 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - -


    Original     		PDF M383L1713CT1 184pin 128MB 16Mx72 16Mx8 72-bit M383L1713CT1
    2001 - Not Available

    Abstract: No abstract text available
    Text: , 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and control , DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - Precharge , for DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; Vin = Vref , idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other , 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - -


    Original     		PDF 172pin M463L0914BT0 8Mx64 8Mx16 64-bit
    2000 - M368L3223BT1

    Abstract: PC200
    Text: DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and , =100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - , , 133Mhz for DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; Vin = , banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other , 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - -


    Original     		PDF M368L3223BT1 184pin 256MB 32Mx64 32Mx8 64-bit 133Mhz) M368L3223BT1 PC200
    Not Available

    Abstract: No abstract text available
    Text: =100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle , ); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - , , 133Mhz for DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; Vin = , banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other , 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - -


    Original     		PDF 172pin M463L1624BG0 128MB 16Mx64 16Mx16 64-bit
    2001 - M470L1624BT0

    Abstract: No abstract text available
    Text: current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ , current; All banks idle; power - down mode; CKE = DDR266A & , # > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B , = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with , , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - - Active standby current


    Original     		PDF M470L1624BT0 200pin 128MB 16Mx64 16Mx16 64-bit M470L1624BT0
    2001 - M470L1713CT0

    Abstract: No abstract text available
    Text: current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ , current; All banks idle; power - down mode; CKE = DDR266A & , # > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B , = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with , , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - - Active standby current


    Original     		PDF M470L1713CT0 200pin 128MB 16Mx64 64bit M470L1713CT0
    M485L0914BT0

    Abstract: No abstract text available
    Text: Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing , down mode; CKE = DDR266A & DDR266B; Vin = Vref for DQ , ; CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control , DDR266A & DDR266B; Address and other control inputs stable with keeping >= VIH(min) or =100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ


    Original     		PDF M485L0914BT0 200pin 8Mx72 8Mx16 72-bit M485L0914BT0
    SDRAM 64MX64

    Abstract: 2MX32 16MX8 8MX16 DDR266A
    Text: HY5DV283222F X4/8/16, 2.5V, DDR266B/DDR200 X4/8/16, 2.5V, DDR266A /B,DDR200 4Mx32, 2.5V, 200/222/250MHZ 4Mx32, 3.3V, 200/250/300MHz 291 349 409 459 256M -bit HY5DU564(8,16)22T X4/8/16, 2.5V, DDR266A /B,DDR200 511 512M-bit HY5DU124(8,16)22T X4/8/16, 2.5V, DDR266A /B.DDR200 573 Rambus DRAM 2 5 6 M I 288M


    OCR Scan     		PDF 64M-brt HY5DV651622T HY5DU641622AT HY5DV641622AT HY5DU663222Q HY5DU663222Q-7M HY5DU643222AQ 4Mx16, SDRAM 64MX64 2MX32 16MX8 8MX16 DDR266A
    2001 - Not Available

    Abstract: No abstract text available
    Text: DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and , =100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - , , 133Mhz for DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; Vin = , banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other , 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - -


    Original     		PDF M383L1713CT1 184pin 128MB 16Mx72 16Mx8 72-bit
    2001 - Not Available

    Abstract: No abstract text available
    Text: DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and , =100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - , , 133Mhz for DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; Vin = , banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other , 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - -


    Original     		PDF M368L3313CT1 184pin 256MB 32Mx64 16Mx64 16Mx8 64-bit
    2001 - Not Available

    Abstract: No abstract text available
    Text: current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ , current; All banks idle; power - down mode; CKE = DDR266A & , # > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B , = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with , , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - - Active standby current


    Original     		PDF M470L1713CT0 200pin 128MB 16Mx64 64bit
    2001 - M470L0914BT0

    Abstract: No abstract text available
    Text: =100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle , ); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - , , 133Mhz for DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; Vin = , banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other , 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - -


    Original     		PDF M470L0914BT0 200pin 8Mx64 8Mx16 64-bit M470L0914BT0
    2000 - M383L2828BT1

    Abstract: 1638B
    Text: Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & , , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - Precharge Floating , DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS , > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs , for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - - Active


    Original     		PDF M383L2828BT1 184pin 128Mx72 64Mx72) 64Mx4 72-bit M383L2828BT1 1638B
    2001 - M381L1713CT1

    Abstract: No abstract text available
    Text: Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & , , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - Precharge Floating , DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS , > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs , for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - - Active


    Original     		PDF M381L1713CT1 184pin 128MB 16Mx72 16Mx8 72-bit M381L1713CT1
    M463L1624BT0

    Abstract: No abstract text available
    Text: Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing , down mode; CKE = DDR266A & DDR266B; Vin = Vref for DQ , ; CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control , DDR266A & DDR266B; Address and other control inputs stable with keeping >= VIH(min) or =100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ


    Original     		PDF 172pin M463L1624BT0 128MB 16Mx64 16Mx16 64-bit M463L1624BT0
    2001 - Not Available

    Abstract: No abstract text available
    Text: ; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock , for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and , current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & , ); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM Active standby


    Original     		PDF M470L3224BT0 200pin 256MB 32Mx64 16Mx16 64-bit
    2001 - Not Available

    Abstract: No abstract text available
    Text: ; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock , for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and , current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & , ); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM Active standby


    Original     		PDF M470L1714BT0 200pin 128MB 16Mx64 8Mx16 64-bit
    2001 - M381L6523MT1

    Abstract: DDR266A
    Text: current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ , current; All banks idle; power - down mode; CKE = DDR266A & , # > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B , = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with , , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - - Active standby current


    Original     		PDF M381L6523MT1 184pin 512MB 64Mx72 64Mx8 72-bit M381L6523MT1 DDR266A
    2001 - Not Available

    Abstract: No abstract text available
    Text: current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ , current; All banks idle; power - down mode; CKE = DDR266A & , # > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B , = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with , , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - - Active standby current


    Original     		PDF M470L1713BT0 200pin 128MB 16Mx64 64bit
    2001 - Not Available

    Abstract: No abstract text available
    Text: DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs , , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - Precharge Floating , DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS , > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs , for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - - Active


    Original     		PDF M470L6423CK0 200pin 512MB 64Mx64 64bit
    2001 - M470L1713BT0

    Abstract: No abstract text available
    Text: current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ , current; All banks idle; power - down mode; CKE = DDR266A & , # > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B , = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with , , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD3P - - Active standby current


    Original     		PDF M470L1713BT0 200pin 128MB 16Mx64 64bit M470L1713BT0
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