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hynix dram numbering

Abstract: DDR266A 200pin SO DIMM ddr 200pin SO DIMM HYMR26416H-XXX hynix hy 16MX8 HY5DV
Text: 200MHz 183MHz 166MHz DDR266A DDR266B DDR200 POWER CONSUMPTION DATA WIDTH & FEATURES 4 8 16 32 : x4 , ,16)22T SSTL-2 SSTL-2 SSTL-2 300/250/222 DDR266A/B, DDR200 DDR266A/B, DDR200 144ball FBGA 66pin , /233/200/183 DDR266B.DDR200 DDR266A/B, DDR200 100pin LQFP 100pin LQFP 66pin TSOP-II 66pin TSOP-II 2K , 32MX8 32MX8 32Mx8 16MX8 16MX8 32MX4 32MX4 16Mx8 16Mx8 32MX8 64Mx4 32Mx8 Speed(MHz) DDR266B, DDR200 DDR266A/B, DDR200 DDR266B, DDR200 DDR266A/B, DDR200 DDR266A/B, DDR200 DDR266B, DDR200 DDR266A/B.DDR200


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PDF 300MHz 275MHz 250MHz 233MHz 222MHz 200MHz 183MHz 166MHz DDR266A DDR266B hynix dram numbering 200pin SO DIMM ddr 200pin SO DIMM HYMR26416H-XXX hynix hy 16MX8 HY5DV
2002 - PCK2057DGG-T

Abstract: DDR200 motherboard ic list GTL2005 PCA9544 PCK2002PL PCK2022RA PCK2057 PCK2509SL dimm ddr 400
Text: , zero delay replicas of the memory clock to drive the clock inputs of the DDR-200 DIMMs PCK 2057 DDR-200 DIMM DDR-200 DIMM DDR-200 DIMM DDR-200 DIMM DDR-200 DIMM DDR-200 DIMM DDR-200 DIMM DDR-200 DIMM On the memory card, the PCK2057 creates 10 low-jitter, zero-delay replicas of the memory clock to drive the clock inputs of the DDR DIMMs. REMC PCK 2057 DDR-200 DIMM DDR-200 DIMM DDR-200 DIMM DDR-200 DIMM DDR-200 DIMM Additional devices featured on the


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PDF PCK2022RA/PCK2057 PCK2002PL/PCK2509SL PCK2022RA 2002PL PCK2057DGG-T DDR200 motherboard ic list GTL2005 PCA9544 PCK2002PL PCK2022RA PCK2057 PCK2509SL dimm ddr 400
2005 - DDR333

Abstract: micron ddr TN-46-13 DDR400 DDR200 DDR266 MT46V64M8
Text: DDR200 DDR266 2 100 MHz 133 MHz 1 200M / 266M / ( M , / 167 MHz DDR400 200 MHz DDR200 2 Micron , JEDEC AC DDR200 JEDEC tRCD (Row-to-Column delay ) 20ns DDR333 18ns tRCD ( 1 ) DDR200 tRCD 2 DDR333 3 PDF , TN-46-13 DDR SDRAM AC 1 JEDEC DDR200 DDR333 tRCD t RCD


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PDF TN-46-13 MT46V64M8) DDR200 DDR266 DDR333 DDR400 09005aef81c057dd/Source: DDR333 micron ddr TN-46-13 DDR400 DDR200 DDR266 MT46V64M8
2007 - DDR333

Abstract: PC2700 WV3EG216M64STSU-D4 DDR266A
Text: ActivePrecharge ICC0* tRC = tRC(min); tCK = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; DQ,DM and DQS , * All banks idle; power - down mode; CKE = DDR200 , 133Mhz for DDR266A & , # > = VIH(min);All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B , = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM 280 mA , precharge; tRC = tRASmax; tCK = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs


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PDF WV3EG216M64STSU-D4 256MB 2x16Mx64 WV3EG216M64STSU 16Mx16 PC2700 DDR333 WV3EG216M64STSU-D4 DDR266A
2005 - DDR266A

Abstract: DDR266B TSOP 173 g DDR333 PC2700 WV3EG216M64STSU-D4
Text: ActivePrecharge IDD0* tRC = tRC(min); tCK = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; DQ,DM and DQS , * All banks idle; power - down mode; CKE = DDR200 , 133Mhz for DDR266A & , # > = VIH(min);All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B , = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM 280 mA , precharge; tRC = tRASmax; tCK = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs


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PDF WV3EG216M64STSU-D4 256MB 2x16Mx64 WV3EG216M64STSU 16Mx16 PC2700 DDR266A DDR266B TSOP 173 g DDR333 WV3EG216M64STSU-D4
2002 - Not Available

Abstract: No abstract text available
Text: Symbol A2(DDR266@CL=2) B0(DDR266@CL=2.5) A0( DDR200@CL=2 ) Unit IDD0 480 440 mA 660 , DDR266A To DDR266B DDR200 DDR266A DDR266B DDR200 Min. Min. Max. Min. Max , /hold time(tIS/tIH) at slow slew rate in DDR200 /266 AC specification Deleted Exit self refresh to write command(tXSW) in DDR200 /266 AC specification Rename tXSA(exit self refresh to bank active command) to tXSNR(exit self refresh to non read command) at DDR200 /266 Rename tXSR(exit self refresh to read


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PDF M368L1624BTL 184pin 128MB 16Mx64 16Mx16 64-bit DDR266A
2001 - M383L1713CT1

Abstract: No abstract text available
Text: A2(DDR266@CL=2) typical worst B0(DDR266@CL=2.5) typical worst A0( DDR200@CL=2 ) typical , DDR200 , 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and , =100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200 , banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and other


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PDF M383L1713CT1 184pin 128MB 16Mx72 16Mx8 72-bit M383L1713CT1
2001 - Not Available

Abstract: No abstract text available
Text: (DDR266@CL=2) typical worst B0(DDR266@CL=2.5) typical worst A0( DDR200@CL=2 ) typical worst , Typical Worst Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200 , DDR200 , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200 , 133Mhz , idle; CKE > = VIH(min); tCK = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and other


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PDF 172pin M463L0914BT0 8Mx64 8Mx16 64-bit
2002 - DDR300

Abstract: SSTV16857 JESD89 SSTV16857DGG PCKV857 SSTV16859 SSTVF16857 DDR200 DDR266 DDR333
Text: PCKV857/PCKVF857 SSTV16857/SSTVF16857 Complete Register & PLL Solution for DDR200 , DDR266 , ).Available performance grades support speeds ranging from DDR200 up to DDR333, plus the ability to drive , frequency range from 100 MHz ( DDR200 ) to 167 MHz (DDR333) Family Overview Part Number PCKV857 , differential 1:10 clock driver for DDR200 ­ DDR266 DIMMs 70-190 MHz differential 1:10 clock driver for DDR300 ­ DDR333 DIMMs 14-bit SSTL_2 registered driver with differential clock inputs for DDR200 ­ DDR266


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PDF PCKV857/PCKVF857 SSTV16857/SSTVF16857 DDR200, DDR266, DDR300 DDR333 SSTV16859 DDR200 DDR333, SSTV16857/SSTVF16857 SSTV16857 JESD89 SSTV16857DGG PCKV857 SSTV16859 SSTVF16857 DDR266 DDR333
2001 - M381L6523MT1

Abstract: DDR266A
Text: =2.5) A0( DDR200@CL=2 ) Unit typical worst typical worst typical worst IDD0 1170 , current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; DQ , current; All banks idle; power - down mode; CKE = DDR200 , 133Mhz for DDR266A & , # > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B , = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with


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PDF M381L6523MT1 184pin 512MB 64Mx72 64Mx8 72-bit M381L6523MT1 DDR266A
2001 - Not Available

Abstract: No abstract text available
Text: worst B0(DDR266@CL=2.5) typical worst A0( DDR200@CL=2 ) typical worst Unit IDD0 800 , current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; DQ , current; All banks idle; power - down mode; CKE = DDR200 , 133Mhz for DDR266A & , # > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B , = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with


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PDF M470L1713BT0 200pin 128MB 16Mx64 64bit
2001 - Not Available

Abstract: No abstract text available
Text: (DDR266@CL=2.5) worst typical A0( DDR200@CL=2 ) worst typical worst Unit IDD0 T.B.D , Worst Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200 , 133Mhz for , power-down standby current; All banks idle; power - down mode; CKE = DDR200 , standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200 , 133Mhz for , > = VIH(min); tCK = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and other control inputs


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PDF M470L6423CK0 200pin 512MB 64Mx64 64bit
2001 - M470L1713BT0

Abstract: No abstract text available
Text: worst B0(DDR266@CL=2.5) typical worst A0( DDR200@CL=2 ) typical worst Unit IDD0 800 , current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; DQ , current; All banks idle; power - down mode; CKE = DDR200 , 133Mhz for DDR266A & , # > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B , = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with


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PDF M470L1713BT0 200pin 128MB 16Mx64 64bit M470L1713BT0
M485L1624BT0

Abstract: No abstract text available
Text: (DDR266@CL=2) typical worst B0(DDR266@CL=2.5) typical worst A0( DDR200@CL=2 ) typical worst , Typical Worst Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200 , DDR200 , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200 , 133Mhz , idle; CKE > = VIH(min); tCK = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and other


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PDF M485L1624BT0 200pin 128MB 16Mx72 16Mx16 72-bit M485L1624BT0
2000 - M368L3223BT1

Abstract: PC200
Text: worst B0(DDR266@CL=2.5) typical worst A0( DDR200@CL=2 ) typical worst Unit IDD0 800 , DDR200 , 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and , =100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200 , banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and other


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PDF M368L3223BT1 184pin 256MB 32Mx64 32Mx8 64-bit 133Mhz) M368L3223BT1 PC200
Not Available

Abstract: No abstract text available
Text: (DDR266@CL=2) B0(DDR266@CL=2.5) A0( DDR200@CL=2 ) typical worst Unit typical worst , =100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle , ); tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM IDD2P - - Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200 , banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and other


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PDF 172pin M463L1624BG0 128MB 16Mx64 16Mx16 64-bit
2001 - M470L1624BT0

Abstract: No abstract text available
Text: =2.5) A0( DDR200@CL=2 ) typical worst Unit typical worst typical worst IDD0 400 , current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; DQ , current; All banks idle; power - down mode; CKE = DDR200 , 133Mhz for DDR266A & , # > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B , = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with


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PDF M470L1624BT0 200pin 128MB 16Mx64 16Mx16 64-bit M470L1624BT0
2001 - M470L1713CT0

Abstract: No abstract text available
Text: worst B0(DDR266@CL=2.5) typical worst A0( DDR200@CL=2 ) typical worst Unit IDD0 640 , current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; DQ , current; All banks idle; power - down mode; CKE = DDR200 , 133Mhz for DDR266A & , # > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B , = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with


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PDF M470L1713CT0 200pin 128MB 16Mx64 64bit M470L1713CT0
M485L0914BT0

Abstract: No abstract text available
Text: ( DDR200@CL=2 ) typical worst Unit IDD0 500 575 500 575 450 500 mA IDD1 , Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing , down mode; CKE = DDR200 , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ , ; CKE > = VIH(min); tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and other control , standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200 , 133Mhz for


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PDF M485L0914BT0 200pin 8Mx72 8Mx16 72-bit M485L0914BT0
2000 - M383L2828BT1

Abstract: 1638B
Text: =2) typical worst B0(DDR266@CL=2.5) typical worst A0( DDR200@CL=2 ) typical worst Unit , Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200 , 133Mhz for DDR266A & , power-down standby current; All banks idle; power - down mode; CKE = DDR200 , standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200 , 133Mhz for , > = VIH(min); tCK = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and other control inputs


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PDF M383L2828BT1 184pin 128Mx72 64Mx72) 64Mx4 72-bit M383L2828BT1 1638B
2001 - Not Available

Abstract: No abstract text available
Text: SODIMM A0( DDR200@CL=2 ) typical 540 680 260 320 300 320 360 900 1000 880 192 186 1420 worst 600 760 280 , ; tRC=tRCmin;tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock , power-down standby current; All banks idle; power - down mode; CKE = DDR200 , 133Mhz , );All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and , current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200 , 133Mhz for DDR266A &


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PDF M470L3224BT0 200pin 256MB 32Mx64 16Mx16 64-bit
2001 - Not Available

Abstract: No abstract text available
Text: SODIMM A0( DDR200@CL=2 ) typical 540 640 260 360 320 300 360 780 820 900 188 184 1300 worst 580 720 280 , ; tRC=tRCmin;tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock , power-down standby current; All banks idle; power - down mode; CKE = DDR200 , 133Mhz , );All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and , current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200 , 133Mhz for DDR266A &


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PDF M470L1714BT0 200pin 128MB 16Mx64 8Mx16 64-bit
2001 - M381L1713CT1

Abstract: No abstract text available
Text: worst B0(DDR266@CL=2.5) typical worst A0( DDR200@CL=2 ) typical worst Unit IDD0 720 , Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200 , 133Mhz for DDR266A & , power-down standby current; All banks idle; power - down mode; CKE = DDR200 , standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=100Mhz for DDR200 , 133Mhz for , > = VIH(min); tCK = 100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and other control inputs


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PDF M381L1713CT1 184pin 128MB 16Mx72 16Mx8 72-bit M381L1713CT1
M463L1624BT0

Abstract: No abstract text available
Text: spec table Symbol A2(DDR266@CL=2) B0(DDR266@CL=2.5) A0( DDR200@CL=2 ) typical worst Unit , Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing , down mode; CKE = DDR200 , 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ , ; CKE > = VIH(min); tCK=100Mhz for DDR200 , 133Mhz for DDR266A & DDR266B; Address and other control , standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200 , 133Mhz for


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PDF 172pin M463L1624BT0 128MB 16Mx64 16Mx16 64-bit M463L1624BT0
2003 - DDR266

Abstract: DDR333 K4H561638 k4h561638f-tc
Text: bank Active-Precharge; tRC=tRCmin; tCK=10ns for DDR200 , 7.5ns for DDR266, 6ns for DDR333; DQ,DM and , ; power - down mode; CKE = DDR200 ,7.5ns for DDR266, 6ns for DDR333; Vin = Vref , > = VIH(min); tCK=10ns for DDR200 , 7.5ns for DDR266, 6ns for DDR333; Address and other control inputs , ; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK=10ns for DDR200 , 7.5ns for DDR266, 6ns for , (max); tCK=10ns for DDR200 , 7.5ns for DDR266, 6ns for DDR333; Vin = Vref for DQ,DQS and DM IDD3P


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PDF 256Mb K4H560838F) DDR266 DDR333 K4H561638 k4h561638f-tc
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