The Datasheet Archive

Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
74SSTL16837ADGGRG4 74SSTL16837ADGGRG4 ECAD Model Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, GREEN, PLASTIC, TSSOP-64
74SSTL16857DGGRG4 74SSTL16857DGGRG4 ECAD Model Texas Instruments SSTL SERIES, 14-BIT DRIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48
SN74SSTL16837ADGGR SN74SSTL16837ADGGR ECAD Model Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64
74SSTL16837ADGGRE4 74SSTL16837ADGGRE4 ECAD Model Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64
SN74SSTL16837DGGR SN74SSTL16837DGGR ECAD Model Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, SSOP-64
74SSTL16847DGGRE4 74SSTL16847DGGRE4 ECAD Model Texas Instruments SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64

DDR2 SSTL class Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
Not Available

Abstract: No abstract text available
Text: . 36 2.7 DDR2 SO-DIMM , . 124 5.5 DDR2 SDRAM , Two 40-pin expansion headers o PCI Express 2.0 (x8 lane) connector • Memory o DDR2 SO-DIMM , €¢ 64MB Flash (32M x16) with a 16-bit data bus 2MB SSRAM (1M x 16) 2Kb EEPROM 9 Two DDR2 SO-DIMM


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PDF 64-bit
NXP ATOP

Abstract: No abstract text available
Text: the DDR2 SO-DIMM , .69 DDR2 SDRAM , equipped for high-speed inter-connection and configurable I/O standards. The DDR2 SO-DIMM socket puts the , Configuration Device Altera Stratix III 3SL340 (DE3-340) or 3SL260 (DE3-260) or 3SL150 (DE3-150) DDR2 , ® Two 40-pin Expansion Headers  Memory Interface:  DDR2 SO-DIMM socket  SD Card


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2009 - AN328

Abstract: AP1910 MT47H64M16BT-37E MT47H32M16CC-3 AL1510 EP2SGX90FF1508C3 AL15-10 MT47H64M8CB-3 MT47H64M16 MT47H64M16BT-37E eye
Text: AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices © October 2009 AN-328-6.0 Introduction This application note provides information about interfacing DDR2 , for implementing a DDR2 SDRAM memory interface on a Stratix II, Stratix II GX, or Arria GX FPGA , : Instantiating the PHY to a DDR2 SDRAM component Setting the appropriate constraints on the PHY , design examples interface with five DDR2 SDRAM components (amounting to a 72-bit interface) available in


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PDF AN-328-6 AN328 AP1910 MT47H64M16BT-37E MT47H32M16CC-3 AL1510 EP2SGX90FF1508C3 AL15-10 MT47H64M8CB-3 MT47H64M16 MT47H64M16BT-37E eye
2009 - SSTL-18

Abstract: EPM2210F256FBGA DDR2 SSTL class g22 touch 3C120F780 AN386 EPM2210 CKE 2009 MT47H32M16CC lcd N7
Text: top_oe_n_to_the_max2 E25 Output enable (active low) Output 1.8 V Bidirectional SSTL -18 Class I Top , Negative differential clock Input Bidirectional SSTL -18 Class I top_ddr2top_a[0] J13 Address Output SSTL -18 Class I top_ddr2top_a[1] G18 Address Output SSTL -18 Class I top_ddr2top_a[2] E8 Address Output SSTL -18 Class I top_ddr2top_a[3] D24 Address Output SSTL -18 Class I top_ddr2top_a[4] D7 Address Output SSTL -18 Class I top_ddr2top_a[5


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PDF 3C120 DS-01002-1 3C120F780 3C120 SSTL-18 EPM2210F256FBGA DDR2 SSTL class g22 touch AN386 EPM2210 CKE 2009 MT47H32M16CC lcd N7
2004 - XAPP758c

Abstract: ISERDES spartan 6 ISERDES XAPP678 FF1136 Virtex-4 serdes XAPP858 XAPP136 XAPP266 XAPP802
Text: Memory Technology and I/O Std DDR2 SDRAM SSTL1.8V Class II DDR SDRAM SSTL -2.5V Class I/II , (Continued) Memory Technology and I/O Std DDR2 SDRAM SSTL -1.8V Class II DDR SDRAM SSTL , bits (Components) Virtex-4 DDR2 SDRAM SSTL1.8V Class II DDR SDRAM SSTL -2.5V Class I/II , XC4VLX25 FF668 All banks supported XAPP702 XAPP701 DDR2 SDRAM SSTL -1.8V Class II 240 MHz 1 , FCRAM-I SSTL -2.5V Class I/II XAPP454/XAPP768c DDR2 SDRAM SSTL1.8V Class II Number of Interfaces


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PDF XAPP802 XAPP701, XAPP702, XAPP703, XAPP709, XAPP710, XAPP852. 32-bit XAPP454 XAPP768c. XAPP758c ISERDES spartan 6 ISERDES XAPP678 FF1136 Virtex-4 serdes XAPP858 XAPP136 XAPP266 XAPP802
EQFP-144

Abstract: ttl to mini-lvds SSTL-18 EP3C10 EP3C120 EP3C16 EP3C25 EP3C40 EP3C55 mini-lvds source driver
Text: certain I/O standards. The LVTTL, LVCMOS, SSTL -2 Class I and II, SSTL -18 Class I and II, HSTL18 Class I , -18 Class II 16 16 SSTL -18 Class I 8 8 10 10 12 12 12 12 16 16 HSTL-15 Class I SSTL -18 Class II SSTL -2 Class I SSTL -2 Class II 8 8 12 12 16 , OCT without calibration for all non-voltage reference and HSTL/ SSTL class I I/O standards. The default setting is 25 OCT without calibration for HSTL/ SSTL class II I/O standards. The default current


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2008 - K1B3216B2E

Abstract: Marvell PHY 88E1111 K1B3216B2E-B170 LTI-SASF546-P26-X1 12 pin 7 segment display layout -LD-5461BS Marvell PHY 88E1111 errata Marvell PHY 88E1111 Datasheet LT4601 lcd screen LVDS connector 40 pins LDQ-M2212R1
Text: 14-Pin LCD Header 1.8-V SSTL 1.8-V SSTL 1-GByte DDR2 (x72) CMOS + LVDS USB 2.0 , 1.8-V SSTL 136 18 data strobe signal (DQS) pins DDR2 devices 1.8-V SSTL 74 Four DQS , . . . . . . . . 2­49 DDR2 SDRAM DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2­49 DDR2 SDRAM Devices . . . . . , Stratix III device supplies internal memory while also providing I/O support for a variety of SDRAM ( DDR2


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PDF 3SL150 K1B3216B2E Marvell PHY 88E1111 K1B3216B2E-B170 LTI-SASF546-P26-X1 12 pin 7 segment display layout -LD-5461BS Marvell PHY 88E1111 errata Marvell PHY 88E1111 Datasheet LT4601 lcd screen LVDS connector 40 pins LDQ-M2212R1
DDR2 SSTL class

Abstract: SSTL_18 DDR1-400 DDR2 SDRAM with SSTL_18 interface TVSOP-48 SSTL-18 PCK2059 SSTV16857 DDR200 hp SSTU32866
Text: Registers ­ DDR and DDR2 technology 3.3 SSTL16877 2.5 200 14 x SSTL -2 14 x SSTL -2 2.4 , 25 x 1.8 0.5 0.5 0 to +70 basic DDR2 register LFBGA-96 HVQFN-56 SSTL _18 SSTL _18 DDR stacked SDRAM register DDR2 400 - 533 Registered DIMMs SSTU32865 1.8 450 28 x SSTL _18 56 x SSTL _18 1.8 0.5 0.5 0 to +70 parity function TFBGA-160 DDR2 400 - 533 2 , series PLL clock buffers DDR200 to DDR266 · SSTV and SSTL series registered drivers · PCKV series


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PDF PC100 PC133 PCK2509 PCK2510 DDR200 DDR266 DDR333 DDR400 PCKVF857 DDR2-400 DDR2 SSTL class SSTL_18 DDR1-400 DDR2 SDRAM with SSTL_18 interface TVSOP-48 SSTL-18 PCK2059 SSTV16857 hp SSTU32866
HSTL-12

Abstract: mini-lvds EQFP-144 EP3C10 EP3C120 EP3C16 EP3C25 EP3C40 EP3C55 SSTL-18
Text: certain I/O standards. The LVTTL, LVCMOS, SSTL -2 Class I and II, SSTL -18 Class I and II, HSTL18 Class I , -18 Class II 16 16 SSTL -18 Class I 8 8 10 10 12 12 12 12 16 16 HSTL-15 Class I SSTL -18 Class II SSTL -2 Class I SSTL -2 Class II 8 8 12 12 16 , OCT without calibration for all non-voltage reference and HSTL/ SSTL class I I/O standards. The default setting is 25 OCT without calibration for HSTL/ SSTL class II I/O standards. The default current


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PDF CIII51007-1 HSTL-12 mini-lvds EQFP-144 EP3C10 EP3C120 EP3C16 EP3C25 EP3C40 EP3C55 SSTL-18
2009 - EP3C16

Abstract: A7 v72 diode qdrii sram
Text: Class II DDR2 SDRAM DDR SDRAM QDRII SRAM SSTL -18 Class I SSTL -18 Class II SSTL -2 Class I SSTL -2 Class II 1.8 V HSTL Class I 1.8 V HSTL Class II DDR2 SDRAM DDR SDRAM QDRII SRAM SSTL -18 Class I SSTL -18 Class II SSTL -2 Class I SSTL -2 Class II 1.8 V HSTL Class I 1.8 V HSTL Class II DDR2 SDRAM DDR SDRAM QDRII , SSTL and HSTL I/O Reference Voltage Specifications I/O Standard SSTL -2 Class I, II SSTL -18 Class I, II , Signal Specifications I/O Standard SSTL -2 Class I SSTL -2 Class II SSTL -18 Class I SSTL -18 Class II HSTL


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PDF CIII52001-3 EP3C16 A7 v72 diode qdrii sram
2010 - ddr3 ram

Abstract: SSTL-18 hyperlynx DDR3 phy pin diagram MT9HTF12872AY-800 DDR3 SSTL class
Text: DDR2 SDRAM Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2­3 , DDR2 and DDR3 SDRAM Designs Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , and command path timing Clock to strobe timing (tDQSS in DDR, DDR2 , and DDR3 SDRAM, and tKHK#H in QDR II and QDRII+ SRAM Read resynchronization path timing (applicable for DDR, DDR2 , and , timing Read postamble path timing (applicable for DDR, DDR2 , and DDR3 SDRAM in Arria II GX, Stratix


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2009 - Not Available

Abstract: No abstract text available
Text: and HSTL I/O Reference Voltage Specifications I/O Standard SSTL -2 Class I, II SSTL -18 Class I, II HSTL , Single-Ended SSTL and HSTL I/O Standards Signal Specifications I/O Standard SSTL -2 Class I SSTL -2 Class II SSTL -18 Class I SSTL -18 Class II HSTL-18 Class I HSTL-18 Class II HSTL-15 Class I HSTL-15 Class II HSTL-12 Class , SSTL -2 Class I, II SSTL -18 Class I, II 2.375 1.7 Typ 2.5 1.8 Max Min Max VCCIO VCCIO Min VCCIO/2 ­ 0.2 , Channel-to-Channel Skew (TCCS) ­ Write Side (Note 1) Memory Standard Column I/Os (ps) I/O Standard Lead SSTL -18 Class


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PDF CIII52001-3
2004 - Not Available

Abstract: No abstract text available
Text: Output Buffer Levels Output AC Test Conditions Symbol Parameter SSTL _18 Class II Units VOH , Drive Symbol Parameter SSTl _18 Class II Units Notes IOH(dc) 2. 3. 4. - 13.4 , Bytes DDR2 SDRAM 14 10 1 rank ← ← ← ← ← ← 72 Bits 64 Bits SSTL 1.8V 5.0 ns , 64Mx64 / 64Mx72 bits Unbuffered DDR2 SDRAM Pb-FREE DIMM HYMP564U64P8/HYMP564U72P8 Revision , . 0.1 / May. 2004 1 64Mx64 / 64Mx72 bits Unbuffered DDR2 SDRAM Pb-FREE DIMM HYMP564U64P8


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PDF 64Mx64 64Mx72 HYMP564U64P8/HYMP564U72P8 HYMP564U64 240-pin
2004 - PS 229

Abstract: No abstract text available
Text: Pull-down under AC Test Load Output Timing Measurement Reference Level SSTL _18 Class II VTT + 0.603 VTT - , Minimum Sink DC Current SSTl _18 Class II - 13.4 13.4 Units mA mA Notes 1, 3, 4 2, 3, 4 VDDQ = 1.7 V , ), C5( DDR2 533 5-5-5) Function Supported 128 Bytes 256 Bytes DDR2 SDRAM 13 10 1 rank 64 Bits SSTL 1.8V , Unbuffered DDR2 SDRAM Lead-Free DIMM HYMP532U64(L)P6 Revision History No. History Defined Target , DDR2 SDRAM Lead-Free DIMM HYMP532U64(L)P6 DESCRIPTION Hynix HYMP532U646 series is unbuffered 240


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PDF HYMP532U64 32Mx64 HYMP532U646 240-pin PS 229
2006 - ITT RZ2

Abstract: JESD8-15a Ras 1210 FDS6375 DDR2 SSTL class 470uF 25V TANT FDS7088N3 MSOP-10 SD101AWS SP2996
Text: consumption and higher data rates, DDR2 operates from 1.8V supply with VTT = 0.9V. The revised JEDEC SSTL 1.8 , ( SSTL ) is the preferred termination architecture for critical control and data signals. It dramatically , margins. The JEDEC SSTL 2 standard defines the termination scheme featured in Figure 1. Figure 1 SSTL 2 Standard In Figure 1, the value of RT can be either 50 ( Class 1 Termination) or 25 ( Class 2 , guarantee correct recognition of a 1 or 0. From this requirement, using SSTL 2 data [1] we can derive the


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PDF SP2996B SP2996 JESD8-15A ITT RZ2 Ras 1210 FDS6375 DDR2 SSTL class 470uF 25V TANT FDS7088N3 MSOP-10 SD101AWS
2010 - 74 series family

Abstract: EP3C10 EP3CLS200 mini-lvds driver AN-447 BGA and eQFP Package EP3CLS70 EQFP-144 mini-lvds source driver receiver altLVDS
Text: . The LVTTL, LVCMOS, SSTL -2 Class I and II, SSTL -18 Class I and II, HSTL-18 Class I and II, HSTL , HSTL-18 Class I 8, 10, 12 8, 10, 12 3.3-V LVCMOS (2) HSTL-18 Class II 16 16 SSTL -18 Class I 8, 10, 12 8, 10, 12 SSTL -18 Class II 12, 16 12, 16 SSTL -2 Class I 8, 12 8, 12 SSTL -2 Class II 16 16 8, 12, 16 8, 12, 16 BLVDS Notes to Table 6­1: (1 , reference and HSTL/ SSTL Class I I/O standards. The default setting is 25- OCT without calibration for HSTL


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sdr sdram pcb layout guidelines

Abstract: DDR2 sdram pcb layout guidelines DDR 333 CII51009-3 CY7C1313V18 EP2C20 EP2C35 EP2C50 SSTL-18 "sdr sdram" pcb layout
Text: class II (3) QDRII SRAM (4) SSTL -18 class I (2) SSTL -18 class II (3) DDR2 SDRAM 36 100 , -2 class I (2) 72 167 333 (1) SSTL -2 class II (2) DDR SDRAM 72 133 267 (1) 72 , bidirectional data strobes or unidirectional read clocks. 1 DDR2 and QDRII interfaces with class II I/O , broad range of external memory interfaces, such as SDR SDRAM, DDR SDRAM, DDR2 SDRAM, and QDRII SRAM , device at clock speeds up to 167 MHz/333 Mbps for DDR and DDR2 SDRAM devices and 167 MHz/667 Mbps for


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PDF CII51009-3 sdr sdram pcb layout guidelines DDR2 sdram pcb layout guidelines DDR 333 CY7C1313V18 EP2C20 EP2C35 EP2C50 SSTL-18 "sdr sdram" pcb layout
2004 - DDR2-400

Abstract: DDR2-533 MO-237 PC2-3200 PC2-4300 HYmp564u64p8
Text: Test Conditions Symbol Parameter SSTL _18 Class II Units VOH Minimum Required Output , Parameter SSTl _18 Class II Units Notes IOH(dc) 2. 3. 4. - 13.4 mA 1, 3, 4 IOL , 64Mx64 / 64Mx72 bits Unbuffered DDR2 SDRAM Pb-FREE DIMM HYMP564U64P8/HYMP564U72P8 Revision , DDR2 SDRAM Pb-FREE DIMM HYMP564U64P8/HYMP564U72P8 DESCRIPTION Hynix HYMP564U64(72)8 series is , ) 64Mx8 DDR2 SDRAM in 60-Lead FBGA packages. Hynix HYMP564U64(72)8 series provide a high performance 8


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PDF 64Mx64 64Mx72 HYMP564U64P8/HYMP564U72P8 HYMP564U64 240-pin DDR2-400 DDR2-533 MO-237 PC2-3200 PC2-4300 HYmp564u64p8
2004 - dm0165

Abstract: HYMP564U64 DDR2-400 DDR2-533 MO-237 PC2-3200 PC2-4300 DDR2 DIMM 240 pin names
Text: Parameter SSTL _18 Class II Units VOH Minimum Required Output Pull-up under AC Test Load VTT + , under test is referenced. Output DC Current Drive Symbol Parameter SSTl _18 Class II Units , 64Mx64 / 64Mx72 bits Unbuffered DDR2 SDRAM DIMM HYMP564U648/HYMP564U728 Revision History No , 2004 1 64Mx64 / 64Mx72 bits Unbuffered DDR2 SDRAM DIMM HYMP564U648/HYMP564U728 DESCRIPTION , HYMP564U64(72)8 series consists of eignt(nine) 64Mx8 DDR2 SDRAM in 60-Lead FBGA packages. Hynix HYMP564U64


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PDF 64Mx64 64Mx72 HYMP564U648/HYMP564U728 HYMP564U64 240-pin dm0165 DDR2-400 DDR2-533 MO-237 PC2-3200 PC2-4300 DDR2 DIMM 240 pin names
2004 - HYMP112U64

Abstract: No abstract text available
Text: Output Timing Measurement Reference Level SSTL _18 Class II VTT + 0.603 VTT - 0.603 0.5 * VDDQ Units V V V , SSTl _18 Class II - 13.4 13.4 Units mA mA Notes 1, 3, 4 2, 3, 4 VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - , DDR2 SDRAM 14 10 1 rank 64 Bits SSTL 1.8V 5.0 ns 3.75 ns +/-0.6ns +/-0.5ns None 7.8us & Self refresh x8 , Unbuffered DDR2 SDRAM DIMM HYMP112U648/HYMP112U728 Revision History No. 0.1 Defined target spec , DDR2 SDRAM DIMM HYMP112U648/HYMP112U728 DESCRIPTION Preliminary 128Mx64 / 128Mx72 bits Hynix


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PDF HYMP112U648/HYMP112U728 128Mx64 128Mx72 HYMP112U64 240-pin
2004 - Not Available

Abstract: No abstract text available
Text: Buffer Levels Output AC Test Conditions Symbol Parameter SSTL _18 Class II Units VOH , Drive Symbol Parameter SSTl _18 Class II Units Notes IOH(dc) 2. 3. 4. - 13.4 , Bytes DDR2 SDRAM 13 10 1 rank 80 08 08 0D 0A 60 64 Bits SSTL 1.8V 5.0 ns 3.75 ns + , 32Mx64 bits Unbuffered DDR2 SDRAM Lead-Free DIMM HYMP532U64(L)P6 Revision History No , DDR2 SDRAM Lead-Free DIMM HYMP532U64(L)P6 DESCRIPTION Hynix HYMP532U646 series is unbuffered 240


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PDF 32Mx64 HYMP532U64 HYMP532U646 240-pin
2010 - DDR3 pcb layout motherboard

Abstract: leveling micron ddr3 DDR2 sdram pcb layout guidelines DDR3 "application note" DDR3 pcb layout ddr3 ram UniPHY SSTL-18 hyperlynx
Text: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2­3 Clock-to-Strobe (for DDR and DDR2 , Chip Select DDR2 and DDR3 SDRAM Designs Background . . . . . . . . . . . . . . . . . . . . . . . . . . , , DDR2 , and DDR3 SDRAM, and tKHK#H in QDR II and QDRII+ SRAM Read resynchronization path timing (applicable for DDR, DDR2 , and DDR3 SDRAM in Arria II GX, Stratix III, Stratix IV, and Stratix V devices) © July 2010 Read datapath timing Read postamble path timing (applicable for DDR, DDR2 , and DDR3


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2004 - Not Available

Abstract: No abstract text available
Text: AC Test Conditions Symbol Parameter SSTL _18 Class II Units VOH Minimum Required , Symbol Parameter SSTl _18 Class II Units Notes IOH(dc) 2. 3. 4. - 13.4 mA 1 , 64Mx64 / 64Mx72 bits Unbuffered DDR2 SDRAM DIMM HYMP264U64(L)8/HYMP264U72(L)8 DESCRIPTION , HYMP264U64(72)8 series consists of sixteen(eighteen) 32Mx8 DDR2 SDRAM in 60-Lead FBGA packages. Hynix , bandwidth. All input and output voltage levels are compatible with SSTL _1.8. High speed frequencies


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PDF 64Mx64 64Mx72 HYMP264U64 8/HYMP264U72 240-pin 32Mx8 60-Lead
2004 - HYMP125U64

Abstract: DDR2-400 ECC hynix HYMP125U72
Text: Output Pull-down under AC Test Load Output Timing Measurement Reference Level SSTL _18 Class II VTT + , Output Minimum Sink DC Current SSTl _18 Class II - 13.4 13.4 Units mA mA Notes 1, 3, 4 2, 3, 4 VDDQ = , Function Supported 256Mx64 128 Bytes 256 Bytes DDR2 SDRAM 14 10 30.0mm/planar/2ranks 64 Bits SSTL 1.8V 5.0 , Unbuffered DDR2 SDRAM DIMM HYMP125U64(L)8/HYMP125U72(L)8 Revision History No. 0.1 History , Unbuffered DDR2 SDRAM DIMM HYMP125U64(L)8/HYMP125U72(L)8 DESCRIPTION 256Mx64 / 256Mx72 bits Hynix


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PDF HYMP125U64 8/HYMP125U72 256Mx64 256Mx72 240-pin DDR2-400 ECC hynix HYMP125U72
2004 - Not Available

Abstract: No abstract text available
Text: Test Conditions Symbol Parameter SSTL _18 Class II Units VOH Minimum Required Output , Parameter SSTl _18 Class II Units Notes IOH(dc) 2. 3. 4. - 13.4 mA 1, 3, 4 IOL , 64Mx64 / 64Mx72 bits Unbuffered DDR2 SDRAM DIMM HYMP564U648/HYMP564U728 Revision History No , / 64Mx72 bits Unbuffered DDR2 SDRAM DIMM HYMP564U648/HYMP564U728 DESCRIPTION Preliminary Hynix , consists of eignt(nine) 64Mx8 DDR2 SDRAM in 60-Lead FBGA packages. Hynix HYMP564U64(72)8 series provide a


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PDF 64Mx64 64Mx72 HYMP564U648/HYMP564U728 HYMP564U64 240-pin
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