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Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
TPH9R00CQH TPH9R00CQH ECAD Model Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 150 V, 64 A, 0.009 Ohm@10V, SOP Advance / SOP Advance(N)
XPH2R106NC XPH2R106NC ECAD Model Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 60 V, 110 A, 0.0021 Ω@10V, SOP Advance(WF)
XPH3R206NC XPH3R206NC ECAD Model Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 60 V, 70 A, 0.0032 Ω@10V, SOP Advance(WF)
TPHR7404PU TPHR7404PU ECAD Model Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 40 V, 0.00074 Ω@10V, SOP Advance, U-MOS-H
5016451620 5016451620 ECAD Model Molex DIP CONNECTOR
5016453220 5016453220 ECAD Model Molex DIP CONNECTOR

D16 PACKAGE DIAGRAM Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
HP 3D6

Abstract: CY7C429 CY7C412 7C429-65 MK4501 CY7C412-30DC
Text: Package Type Operating Range 30 CY7C412-30 PC P15 Commercial CY7C412-30 JC J65 CY7C412-30 DC D16 , CY7C412-65 DMB D16 Military CY7C412-65 LMB L55 Speed (ns) Ordering Code Package Type Operating Range , rings and a substrate bias generator. Logic Block Diagram DATA INPUTS (D0-D8) Pin Configurations LCC , can be monitored. Switching Waveforms Asynchronous Read and Write Timing Diagram Depth Expansion , Mode. Q0-Q8 D0-D8 Master Reset Timing Diagram MR \ EF Notes: 1- tMRSC ™ tPMR + tRMR V


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PDF CY7C412 CY7C424/CY7C429 CY7C424-40 CY7C424-65 CY7C429-30 HP 3D6 CY7C429 7C429-65 MK4501 CY7C412-30DC
Not Available

Abstract: No abstract text available
Text: -65 DMB D16 CY7C412-65 LMB L55 CY7C424-65 LMB L55 Ordering Code Package Type , asynchronous; each can occur at a rate of 25 MHz. The write operation occurs Logic Block Diagram when , monitored. Switching Waveforms Asynchronous Read and Write Timing Diagram Q0-Q8 D0 - D 8 ( DATA IN VALID ) - M aster Reset Timing Diagram t PMR • M R b, wZZZZZZZZZZ2 , Switching Waveforms (Continued) Half-Full Flag Timing Diagram Last WRITE to First READ Full Flag Timing


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PDF CY7C412 CY7C424/CY7C429 CY7C412-65 CY7C429-30 CY7C429-40
2002 - 68SV8000X

Abstract: SV800 D-16 "256K x 16" SRAM PLCC
Text: from the PUMA 68SV2000X. Block Diagram 1.80 W (Max) 1.12 W (Max) 432 mW (Max) · , supply. Pin Definition D16 NC A17 BS3 BS2 BS1 BS0 CS2 VCC NC CS1 OE WE A16 A15 A14 , -15 D16 -31 A0-A17 D17 D18 D19 VSS D20 D21 D22 D23 VCC D24 D25 D26 D27 VSS D28 D29 D30 , Connect Power (+3.3V) Ground A0 - A17 D0 - D31 CS1~2 BS0~3 WE OE NC VCC GND Package , diagram * VCC=3.3V±10% Operation Truth Table CS1 CS2 BS0 BS1 BS2 BS3 L L L L L L L L L L


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PDF 68SV8000X 219OC SV800 D-16 "256K x 16" SRAM PLCC
CY7C425

Abstract: CY7C420 CY7C429-30DC CY7C42I-25JI CY7C421-40DC CY7C421 CY7C429 IDT7201 IDT7203 CY7C429-30PC
Text: , CY7C428, CY7C429 Speed (ns) Ordering Code Package ■type Operating Range 20 CY7C420-20DC D16 Commercial , Code Package type Operating Range 20 CY7C424-20DC D16 Commercial CY7C424-20PC P15 25 CY7C424-25DC D16 , Industrial CY7C424-65PI P15 CY7C424-65DMB D16 Military Speed (ns) Ordering Code Package type Opcrating , 65DMB D16 Military Speed Ordering Code Package Operating (ns) Tfrpe Range ' 20 CY7C429-20DC D22 , bias generator. Logic Block Diagram DATA INPUTS (Do-Da) WHITE CONTROL HEAD CONTROL wane POINTER -N -V


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PDF CY7C420, CY7C421 CY7C424, CY7C425 CY7C428Â CY7C429 333-MHz 300-mil outpCY7C429 CY7C420 CY7C429-30DC CY7C42I-25JI CY7C421-40DC IDT7201 IDT7203 CY7C429-30PC
S8000

Abstract: bhz 4-8 125OC
Text: PUMA 68S2000X. Block Diagram · Very Fast Access Times of 12/15/17/20 ns. · JEDEC 68 'J' , supply. Pin Definition D16 NC A17 BS3 BS2 BS1 BS0 CS2 VCC NC CS1 OE WE A16 A15 A14 D15 BS3 BS2 CS2 9 BS1 BS0 CS1 256Kx16 SRAM 256Kx16 SRAM OE WE D0-15 D16 , A13 A12 A11 A10 A9 A8 A7 D0 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Package , diagram * VCC=5V±10% Operation Truth Table CS1 CS2 BS0 BS1 BS2 BS3 L L L L L L L L L L L


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PDF 68S8000X 68S8000X 219OC, 125OC 183OC, S8000 bhz 4-8
1998 - cmos 16-bit shift register

Abstract: DO15 M66008
Text: conversion · Division of I/O bit in parallel data input/output · Low power consumption of 50 µW/ package , output (DO, D1~ D16 ) · With parallel data input/output (D1~ D16 ) · Wide operating supply voltage range , CLK 3 CHIP SELECT INPUT CS 4 VCC SET INPUT 5 S 6 S GND 7 D16 PARALLEL DATA D15 INPUT/OUTPUT D14 D13 8 D16 D8 9 D15 D9 16 10 , parallel/serial data conversion MCU, etc. BLOCK DIAGRAM VCC SET INPUT S 6 CHIP SELECT INPUT


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PDF M66008P/FP 16-BIT M66008 cmos 16-bit shift register DO15
S2000

Abstract: bhz 4-8 DIN 2510
Text: available. Block Diagram · Very Fast Access Times of 15/17/20/25 ns. · JEDEC 68 'J' leaded , (Max) 110 mW (Max) Pin Definition D16 NC NC BS3 BS2 BS1 BS0 CS2 VCC NC CS1 OE WE NC , -15 D16 -31 A0-A15 D17 D18 D19 GND D20 D21 D22 D23 VCC D24 D25 D26 D27 GND D28 D29 D30 , A11 A10 A9 A8 A7 D0 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Package Details , and Output timing reference levels: 1.5V 100pF * Output load: see diagram * VCC


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PDF 68S2000X 68S2000X 68S2000XLI S2000 S2000 bhz 4-8 DIN 2510
ad 42830

Abstract: CY7C425 42830
Text: -65PI CY7C420-65DMB Package Type PJ5 D 16 P15 D16 P15 D16 P15 D16 P15 D16 P15 D16 P15 D16 P15 D16 P15 D16 , -65PI CY7C424-65DMB Package Type P I5 D16 P15 D16 P15 D16 P15 D16 P15 D16 P15 D16 P15 D16 P15 D16 P15 D16 , -40DC CY7C428-40PI CY7C428-40DMB 65 CY7C428-65PC CY7C428-65DC CY7C428-65PI CY7C428-65DMB Package Type P15 D16 , information. Switching Waveforms Asynchronous Read and Write Timing Diagram -'RC- "V - · lzr - I , Timing Diagram ,D ]1_ ca r,w W W W f t > Notes: 1 tMRSC = tpMR + tRMR 2. W and R = V jh around


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PDF CY7C420, CY7C421, CY7C424 CY7C425, CY7C428, CY7C429 38-00079-F ad 42830 CY7C425 42830
Not Available

Abstract: No abstract text available
Text: Division of I/O bit in parallel data input/output Low power consumption of 50 ^iW/ package maximum (Vcc , ~ D16 ) With parallel data input/output (D1~ D16 ) Wide operating supply voltage range (Vcc=2~6V) Wide operating temperature range (Ta=-20~75°C ) D13 GND D16 D8 - - D15 D9 - - D14 D10 - ÎÏÏ] « D10 - D16 PARALLEL DATA D15 INPUT/OUTPUT D14^ FEATURES • • • â , parallel/serial data conversion MCU, etc. BLOCK DIAGRAM Vcc GND ♦ GND MITSUBISHI W


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PDF M66008P/FP 16-BIT M66008
2012 - IR LED and photodiode heart rate

Abstract: pulse oximeter using microcontroller OP marking code D22 Photodiodes AFE4400 sensor oximeter plethysmograph IR SENSOR to detect heart rate ti so cf fault map class 2b marking code D22
Text: Cable On/Off Detection Supplies: ­ Rx = 2.0 V to 3.6 V ­ Tx = 3.0 V to 3.6 V Package : Compact QFN-40 (6 , AFE solution packaged in a single, compact QFN-40 package (6 mm × 6 mm) and is specified over the , information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report , tSIMOHD tSIMOSU SPI SIMO A7 A6 A1 A0 tSOMIHD tSOMIPD tSOMIPD D23 D22 D17 D16 SPI SOMI D7 D6 , Timing Diagram , Read Operation (1)(2)(3) 8 Submit Documentation Feedback Product Folder Links


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PDF AFE4400 SBAS601D 95-dB IR LED and photodiode heart rate pulse oximeter using microcontroller OP marking code D22 Photodiodes AFE4400 sensor oximeter plethysmograph IR SENSOR to detect heart rate ti so cf fault map class 2b marking code D22
1999 - 512k x 8 chip block diagram

Abstract: 512K x 8 bit sram 32 pin 2M x 32 chip block diagram 512k x 8 SRAM
Text: 64Mbit Static RAM Module offered in a low profile 72 pin ZIP package , organised as 2M x 32. The module , . Features · · · · · · · · Access Times of 15/20/25 ns. 72 Pin Zig-zag-In-line Package (ZIP). 5 , . On-board Supply Decoupling Capacitors. Pin Definition Block Diagram See page 7. TOP VIEW Pin , (+5V) Ground Issue 1.2 : April 1999 A0 - A20 D0 - D31 CS1~4 WE OE NC VCC GND Package , 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 CS3 A16 GND D16 D17 D18


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PDF SYS322000ZK-015/020/025 SYS322000ZK 64Mbit SYS322000ZKI-15 512k x 8 chip block diagram 512K x 8 bit sram 32 pin 2M x 32 chip block diagram 512k x 8 SRAM
1999 - Not Available

Abstract: No abstract text available
Text: . Block Diagram (PUMA 68 S4000A page 2) A0-A16 OE WE Pin Definition (PUMA 68 S4000A page 2) CS3 GND , 31 32 33 34 35 36 37 38 39 40 41 42 43 D16 D17 D18 D19 D20 D21 D22 D23 GND D24 D25 D26 D27 D28 D29 D30 D31 128Kx8 SRAM CS1 CS2 CS3 CS4 D0-7 D8-15 D16 -23 D24-31 128Kx8 SRAM 128Kx8 SRAM , Enable No Connect Power (+5V) Ground A0 - A16 D0 - D31 CS1~4 WE1~4 OE NC VCC GND Package Details , : December 1999 PUMA 68 S4000A Pinout and Block Diagram . A0 ~A16 /OE /WE4 /WE3 /WE2 /WE1 128K x 8


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PDF 68S4000/A 32-BIT) PUMA68S4000/A JED-STD-020. 200pcs 183OC 225OC 219OC
CY7C425

Abstract: C4206 1DT7201 CY7C429-20DC CY7C420
Text: -65DI CY7C420-65PI CY7C420-65DMB Package type D16 P15 D16 P15 D16 P15 D16 D16 P15 D16 P15 D16 D16 P15 D16 P15 D16 D16 P15 D16 P15 D16 Military 40 Industrial Military Commercial Industrial Industrial Military , , CY7C424 CY7C425, CY7C428, CY7C429 T -46-35 Package type D16 P15 D16 P15 D16 P15 D16 D 16 P15 D16 P15 , be asynchronous; each can occur at a rate of' Logic Block Diagram Pin Configurations PLCC/LCC , (continued) Empty Flag and Empty Boundary Timing Diagram T-46-35 5-36 YPRESS SEMICONDUCTOR i


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PDF CY7C420, CY7C421 CY7C424, CY7C425 CY7C428* CY7C429 T-46-35 C4206 1DT7201 CY7C429-20DC CY7C420
2002 - 64mbit 72-pin simm

Abstract: 72-pin simm 2m x 32 SRAM SIMM
Text: · · · Access Times of 15/20/25 ns. 72 Pin SIMM package . 5 Volt Supply ± 10%. Operating Power (32bit , low profile 72 pin SIMM package , organised as 2M x 32. The module utilises sixteen 512K x 8 SRAM , multiple bytes. The module also incorporates on-board decoupling. Pin Definition Block Diagram See Page 7 NC PD4 PD1 D0 D1 D2 D3 VCC A7 A8 A9 D4 D5 D6 D7 WE A14 CS1 CS3 A16 GND D16 D17 D18 D19 A10 A11 , ) Ground A0 - A20 D0 - D31 CS1~4 WE OE NC VCC GND Package Details Plastic 72 Pin SIMM PD2 = PD3 = GND


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PDF SYS322000LKXA 32bit 935mW 64Mbit AI-15 64mbit 72-pin simm 72-pin simm 2m x 32 SRAM SIMM
1997 - D3057

Abstract: No abstract text available
Text: : 3.3 V ±0.3 V · Static operation · Package : 70-pin, 500-mil SSOP · Addressable page: 4 Double words or , A2 A3 A4 A5 VCC D0 D16 D1 D17 GND VCC D2 D18 D3 D19 D4 D20 D5 D21 GND VCC D6 D22 D7 D23 GND A6 A7 A8 , DECODER 17 D19 15 D18 11 D17 9 D16 62 60 56 54 52 50 46 44 26 24 20 18 16 14 10 8 D15 D14 D13 D12 D11 , 2 A1 53BV16900-2 Figure 2. LH53BV16900 Block Diagram 2 CMOS 16M (1M x 16/512K x 32 , ) Ground No connection TRUTH TABLE CE OE W A-1 (D31) DATA OUTPUT D0 - D15 D16 - D31 ADDRESS INPUT LSB


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PDF LH53BV16900 70-pin, 500-mil LH53BV16900 16M-bit 70SSOP SSOP70-P-500) LH53BV16900T D3057
1999 - 512k x 8 chip block diagram

Abstract: TSOP II 54 64mbit 72-pin simm
Text: plastic 64Mbit Static RAM Module offered in a low profile 72 pin SIMM package , organised as 2M x 32. The , /25 ns. 72 Pin SIMM package . 5 Volt Supply ± 10%. Operating Power (32bit mode) 7.60W (Max , Block Diagram See Page 7 TOP VIEW Pin Functions Address Inputs Data Input/Output Chip Selects , VCC GND Package Details Plastic 72 Pin SIMM NC PD4 PD1 D0 D1 D2 D3 VCC A7 A8 A9 D4 , A16 GND D16 D17 D18 D19 A10 A11 A12 A13 D20 D21 D22 D23 GND A19 NC 38 40 42 44


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PDF SYS322000LKXA 64Mbit 512k x 8 chip block diagram TSOP II 54 64mbit 72-pin simm
1999 - Not Available

Abstract: No abstract text available
Text: is a plastic 64Mbit Static RAM Module offered in a low profile 72 pin SIMM package , organised as 2M , €¢ • • • Access Times of 15/20/25 ns. 72 Pin SIMM package . 5 Volt Supply ± 10 , Decoupling Capacitors. Pin Definition Block Diagram See Page 7 TOP VIEW Pin Functions Address , A0 - A20 D0 - D31 CS1~4 WE OE NC VCC GND Package Details Plastic 72 Pin SIMM NC PD4 , 20 22 24 26 28 30 32 34 36 CS3 A16 GND D16 D17 D18 D19 A10 A11 A12 A13 D20 D21


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PDF SYS322000LKXA 64Mbit
2001 - 68S4000

Abstract: S4000A 68S4000a d1914
Text: A1 Block Diagram 1 68 67 66 65 64 63 62 61 D0 D16 59 D17 D2 12 58 D18 , 21 49 D11 CS1 CS2 CS3 CS4 D0-7 D8-15 D16 -23 D24-31 128Kx8 SRAM 60 D5 , - A16 D0 - D31 CS1~4 WE1~4 OE NC VCC GND Package Details Plastic 68 J-Leaded JEDEC PLCC PUMA 68S4000/A - 020/025/35/45 ISSUE 4.5 : April 2001 PUMA 68 S4000A Pinout and Block Diagram , A9 A10 VCC D0~7 D8~15 D16 ~23 D24~31 9 8 7 6 5 4 3 2 1 68 67 66 65


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PDF 68S4000/A PUMA68S4000/A 128Kx8 JED-STD-020. 200pcs 183OC 225OC 219OC 68S4000 S4000A 68S4000a d1914
Not Available

Abstract: No abstract text available
Text: Pin Definition A1 Block Diagram 1 68 67 66 65 64 63 62 61 D0 D16 59 D17 D2 , 50 D25 D10 21 49 D11 CS1 CS2 CS3 CS4 D0-7 D8-15 D16 -23 D24-31 128Kx8 , 37 38 39 40 41 42 43 A0 - A16 D0 - D31 CS1~4 WE1~4 OE NC VCC GND Package Details , S4000A Pinout and Block Diagram . A0 ~A16 /OE /WE4 /WE3 /WE2 /WE1 128K x 8 SRAM 128K x 8 , GND /CS4 /WE1 A6 A7 A8 A9 A10 VCC D0~7 D8~15 D16 ~23 D24~31 9 8 7 6 5 4


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PDF 68S4000/A PUMA68S4000/A 128Kx8 JED-STD-020. 200pcs 183OC 225OC 219OC
1999 - Not Available

Abstract: No abstract text available
Text: 2) A2 (PUMA 68 S4000A page 2) A3 Pin Definition A1 Block Diagram 1 68 67 66 65 64 63 62 61 D0 128Kx8 SRAM 60 D16 59 D17 D2 12 58 D18 13 57 D19 , D11 CS1 CS2 CS3 CS4 D0-7 D8-15 D16 -23 D24-31 128Kx8 SRAM 11 D4 128Kx8 SRAM , VCC GND Package Details Plastic 68 J-Leaded JEDEC PLCC PUMA 68S4000/A - 020/025/35/45 ISSUE 4.4 : December 1999 PUMA 68 S4000A Pinout and Block Diagram . A0 ~A16 /OE /WE4 /WE3 /WE2


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PDF 68S4000/A PUMA68S4000/A 128Kx8 JED-STD-020. 200pcs 183OC 225OC 219OC
2001 - Not Available

Abstract: No abstract text available
Text: . Special power-up sequencing is not required. Package : 44-pin PLCC with internally fused pins (suffix ED , isolation. Pin-out Diagram LOAD 43 SUPPLY1 SENSE1 OUT1A ENABLE1 GND GND GND NC OUT1B 40 NC NC 41 44 , information Characteristic Package Thermal Resistance Symbol RJA RJT Test Conditions* 4-layer PCB based on , DIAGRAM VDD LOGIC SUPPLY CHARGE PUMP BANDGAP VDD CREG TSD VBB1 + CP2 LOAD SUPPLY1 BANDGAP , Ratio Gain (Gm) Error (note 3) Symbol IREF VIO VREF/VS EG Test Conditions VREF = 2.6 V D16 = 1 D16


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PDF A3974
1997 - Not Available

Abstract: No abstract text available
Text: Mode Read Cycle 5 LH53BV32R00 CMOS 32M (2M x 16/1M x 32) MROM PACKAGE DIAGRAM 70SSOP , TTL compatible · Supply voltage: 3.3 V ±0.3 V · Static operation · Package : 70 pin, 500-mil SSOP · , 70-PIN SSOP A0 A1 A2 A3 A4 A5 VCC D0 D16 D1 D17 GND VCC D2 D18 D3 D19 D4 D20 D5 D21 GND VCC D6 D22 D7 , ) ADDRESS DECODER ADDRESS BUFFER 17 D19 15 D18 11 D17 9 D16 62 60 56 54 52 50 46 44 26 24 20 18 16 14 , GND 63 A-1 1 A0 2 A1 53BV32R00-2 Figure 2. LH53BV32R00 Block Diagram 2 CMOS 32M


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PDF LH53BV32R00 500-mil LH53BV32R00 32M-bit sili08] 70SSOP 70-pin, SSOP70-P-500) LH53BV32R00N
CY7C425

Abstract: 7C421 dip 28 7c424
Text: CY7C424 -65DC CY7C424-65PC CY7C424- 65PI CY7C424 - 65DMB Package Type D16 P15 D16 PI 5 P15 D16 D16 P15 P15 D16 D16 P15 PI 5 D16 D16 P15 PI 5 D16 Package Type 28-Lead (600-Mil) CerDIP 28-Lead (600 , D16 P15 D16 PI 5 P15 D16 D16 P15 P15 D16 D16 P15 P15 D16 D16 P15 P15 D16 Package lypt 28-Lead (600 , Switching Waveforms (continued) Data In Timing Diagram C408A-13 Bubble-Back, Data Out To Data In Diagram Notes: 18. FIFO contains 55 words. 19. FIFO contains 56 words. 20. FIFO contains 54 words


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PDF CY7C420, CY7C421 CY7C424, CY7C425 CY7C428, CY7C429 7C421 dip 28 7c424
1997 - Not Available

Abstract: No abstract text available
Text: LH53BV32900 CMOS 32M (2M x 16/1M x 32) MROM PACKAGE DIAGRAM 70SSOP (SSOP70-P-500) 0.40 [0.015] 0.20 , : 3.3 V ±0.3 V · Static operation · Package : 70-pin, 500-mil SSOP · Addressable page: 4 Double words or , technology. CMOS 32M (2M × 16/1M × 32) MROM PIN CONNECTIONS 70-PIN SSOP A0 A1 A2 A3 A4 A5 VCC D0 D16 D1 , 62 60 56 54 52 50 46 44 26 24 20 18 16 14 10 8 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 , Figure 2. LH53BV32900 Block Diagram 2 CMOS 32M (2M x 16/1M x 32) MROM LH53BV32900 PIN


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PDF LH53BV32900 70-pin, 500-mil LH53BV32900 32M-bit 70SSOP SSOP70-P-500) LH53BV32900T
OTO70

Abstract: No abstract text available
Text: PACKAGE 16 Ld SBDIP 16 Ld SBDIP 16 Ld SBDIP 16 Ld SBDIP PKG. NO. D16 .3 D16 .3 D16 .3 D16 .3 Pinouts IH5052 (SBDIP) TOP VIEW Functional Diagram (1/4 AS SHOWN) IH5053 (SBDIP) TOP VIEW LI U


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PDF IH5052, IH5053 IH5053 10jiA. 1000ns) 500ns) IH5052 OTO70
Supplyframe Tracking Pixel