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Part Manufacturer Description Datasheet Download Buy Part
CY7C1514KV18-250BZI Cypress Semiconductor QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, FBGA-165
CY7C1514KV18-333BZXC Cypress Semiconductor QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, FBGA-165
CY7C1514KV18-250BZC Cypress Semiconductor QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, FBGA-165
CY7C1514KV18-300BZXI Cypress Semiconductor QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, FBGA-165
CY7C1514KV18-250BZXC Cypress Semiconductor QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, FBGA-165
CY7C1514KV18-333BZXI Cypress Semiconductor QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, FBGA-165
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CY7C1514KV18-250BZCKG Cypress Semiconductor Rochester Electronics 22 - -
CY7C1514KV18-250BZI Cypress Semiconductor Future Electronics - $128.33 $128.33
CY7C1514KV18-250BZI Cypress Semiconductor Rochester Electronics 102 $210.97 $171.41
CY7C1514KV18-250BZXC Cypress Semiconductor Future Electronics - $98.71 $98.71
CY7C1514KV18-250BZXC CYPRESS SEMICONDUCTOR New Advantage Corporation 3 $193.20 $180.32
CY7C1514KV18-250BZXC Cypress Semiconductor Future Electronics 5 $135.24 $120.71
CY7C1514KV18-250BZXC Cypress Semiconductor Rochester Electronics 8 $162.30 $131.87
CY7C1514KV18-250BZXI Cypress Semiconductor Rochester Electronics 166 $210.97 $171.41
CY7C1514KV18-250BZXI Cypress Semiconductor Future Electronics 5 $159.13 $136.14
CY7C1514KV18-250BZXI CYPRESS SEMICONDUCTOR New Advantage Corporation 3 $227.33 $212.17
CY7C1514KV18-250CKB Cypress Semiconductor Rochester Electronics 136 $141.12 $114.66
CY7C1514KV18-250XCKG Cypress Semiconductor Rochester Electronics 1,294 - -
CY7C1514KV18-300BZI Cypress Semiconductor Rochester Electronics 162 $169.34 $137.59
CY7C1514KV18-300BZXC Cypress Semiconductor Rochester Electronics 5 $169.34 $137.59
CY7C1514KV18-300BZXI Cypress Semiconductor Rochester Electronics 102 $194.73 $158.22
CY7C1514KV18-333BZI Cypress Semiconductor Rochester Electronics 137 $206.44 $167.74
CY7C1514KV18-333BZXC Cypress Semiconductor Rochester Electronics 534 $206.44 $167.74
CY7C1514KV18-333BZXI Cypress Semiconductor Rochester Electronics 152 $206.44 $167.74
CY7C1514KV18-333ZCES Cypress Semiconductor Rochester Electronics 172 - -

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CY7C1514KV18 datasheet (17)

Part Manufacturer Description Type PDF
CY7C1514KV18-200BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 200MHZ 165FBGA Original PDF
CY7C1514KV18-250BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 250MHZ 165FBGA Original PDF
CY7C1514KV18-250BZI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 250MHZ 165FBGA Original PDF
CY7C1514KV18-250BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 250MHZ 165FBGA Original PDF
CY7C1514KV18-250BZXI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 250MHZ 165FBGA Original PDF
CY7C1514KV18-300BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 300MHZ 165FBGA Original PDF
CY7C1514KV18-300BZC Cypress Semiconductor 72-Mbit QDR -II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V Original PDF
CY7C1514KV18-300BZI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 300MHZ 165FBGA Original PDF
CY7C1514KV18-300BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 300MHZ 165FBGA Original PDF
CY7C1514KV18-300BZXC Cypress Semiconductor 72-Mbit QDR -II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V Original PDF
CY7C1514KV18-300BZXI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 300MHZ 165FBGA Original PDF
CY7C1514KV18-333BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 333MHZ 165FBGA Original PDF
CY7C1514KV18-333BZC Cypress Semiconductor 72-Mbit QDR -II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V Original PDF
CY7C1514KV18-333BZI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 333MHZ 165FBGA Original PDF
CY7C1514KV18-333BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 333MHZ 165FBGA Original PDF
CY7C1514KV18-333BZXC Cypress Semiconductor 72-Mbit QDR -II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V Original PDF
CY7C1514KV18-333BZXI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 333MHZ 165FBGA Original PDF

CY7C1514KV18 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2010 - Not Available

Abstract: No abstract text available
Text: 2M x 36 (2 arrays each of 1M x 36) for CY7C1514KV18. Therefore, only 22 address inputs are needed to , 20 address inputs for CY7C1514KV18. These inputs are ignored when the appropriate port is deselected , to CY7C1510KV18, CY7C1525KV18, and CY7C1514KV18. enables for a seamless transition between devices , CY7C1512KV18, CY7C1514KV18 ® Configurations CY7C1510KV18 ­ 8M x 8 CY7C1525KV18 ­ 8M x 9 CY7C1512KV18 ­ 4M x 18 CY7C1514KV18 ­ 2M x 36 Separate Independent Read and Write Data Ports Supports concurrent


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PDF 72-Mbit CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 CY7C1510KV18 CY7C1525KV18 CY7C1512KV18
2010 - 350bz

Abstract: No abstract text available
Text: 2M x 36 (2 arrays each of 1M x 36) for CY7C1514KV18. Therefore, only 22 address inputs are needed to , 20 address inputs for CY7C1514KV18. These inputs are ignored when the appropriate port is deselected , to CY7C1510KV18, CY7C1525KV18, and CY7C1514KV18. enables for a seamless transition between devices , CY7C1512KV18, CY7C1514KV18 ® Configurations CY7C1510KV18 ­ 8M x 8 CY7C1525KV18 ­ 8M x 9 CY7C1512KV18 ­ 4M x 18 CY7C1514KV18 ­ 2M x 36 Separate Independent Read and Write Data Ports Supports concurrent


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PDF 72-Mbit CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 350bz
2009 - CY7C1512KV18-250BZXC

Abstract: CY7C1512KV18-250BZC CY7C1525KV18-250BZXC MO-216
Text: CY7C1514KV18. Therefore, only 22 address inputs are needed to access the entire memory array of CY7C1510KV18 and CY7C1525KV18, 21 address inputs for CY7C1512KV18, and 20 address inputs for CY7C1514KV18. These , sections. The same basic descriptions apply to CY7C1510KV18, CY7C1525KV18, and CY7C1514KV18. lower 18 , CY7C1512KV18, CY7C1514KV18 ® Configurations CY7C1510KV18 ­ 8M x 8 CY7C1525KV18 ­ 8M x 9 CY7C1512KV18 ­ 4M x 18 CY7C1514KV18 ­ 2M x 36 Separate Independent Read and Write Data Ports Supports concurrent


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PDF 72-Mbit CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1512KV18-250BZXC CY7C1512KV18-250BZC CY7C1525KV18-250BZXC MO-216
2011 - bzx 650

Abstract: No abstract text available
Text: CY7C1514KV18. Therefore, only 22 address inputs are needed to access the entire memory array of CY7C1510KV18 and CY7C1525KV18, 21 address inputs for CY7C1512KV18, and 20 address inputs for CY7C1514KV18. These , . The same basic descriptions apply to CY7C1510KV18, CY7C1525KV18, and CY7C1514KV18. Read , CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 ® 72-Mbit QDR II SRAM 2-Word Burst , x 18 Two-word burst on all accesses CY7C1514KV18 ­ 2M x 36 Double data rate (DDR


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PDF CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit CY7C1510KV18 CY7C1512KV18 bzx 650
2012 - Not Available

Abstract: No abstract text available
Text: arrays each of 2 M × 18) for CY7C1512KV18, and 2 M × 36 (2 arrays each of 1 M × 36) for CY7C1514KV18. , inputs for CY7C1512KV18, and 20 address inputs for CY7C1514KV18. These inputs are ignored when the , following sections. The same basic descriptions apply to CY7C1525KV18, and CY7C1514KV18. Functional , CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR® II SRAM Two-Word Burst Architecture 72 , CY7C1512KV18 ­ 4 M × 18 CY7C1514KV18 ­ 2 M × 36 Separate independent read and write data ports Supports


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PDF CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit CY7C1525KV18 CY7C1512KV18
2009 - Not Available

Abstract: No abstract text available
Text: CY7C1514KV18. Therefore, only 22 address inputs are needed to access the entire memory array of CY7C1510KV18 and CY7C1525KV18, 21 address inputs for CY7C1512KV18, and 20 address inputs for CY7C1514KV18. These , CY7C1514KV18. Read Operations The CY7C1512KV18 is organized internally as two arrays of 2M x 18. Accesses , CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 ® 72-Mbit QDR II SRAM 2-Word Burst , x 18 2-word Burst on all Accesses CY7C1514KV18 ­ 2M x 36 Double Data Rate (DDR


Original
PDF CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit CY7C1510KV18 CY7C1512KV18
2012 - Not Available

Abstract: No abstract text available
Text: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 兆2-Mb典t唯Q当R 唯存存唯止RAMå , • 408-943-2600 Revised May 4, 2012 CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 , , CY7C1514KV18 当[1兆:0公 1片 21 Aæ ·20:0æ ¸ 21 RPæ­¢ 唯 唯 2Må , , CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 唯. å , CY7C1512KV18, CY7C1514KV18 归Y兆归1510Kæ­¥1片 归Y兆归1525Kæ­¥1片 归Y兆å


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PDF CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 1510Kæ 1512Kæ 1514Kæ 1525Kæ
2009 - CY7C1512KV18-250BZXI

Abstract: CY7C1514KV18-300BZI CY7C1525KV18-167BZC
Text: 18) for CY7C1512KV18, and 2M x 36 (2 arrays each of 1M x 36) for CY7C1514KV18. Therefore, only 22 , inputs for CY7C1512KV18, and 20 address inputs for CY7C1514KV18. These inputs are ignored when the , following sections. The same basic descriptions apply to CY7C1510KV18, CY7C1525KV18, and CY7C1514KV18. , CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDRTM-II SRAM 2-Word Burst , x 18 2-word Burst on all Accesses CY7C1514KV18 ­ 2M x 36 Double Data Rate (DDR


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PDF CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit CY7C1510KV18 CY7C1512KV18 CY7C1512KV18-250BZXI CY7C1514KV18-300BZI CY7C1525KV18-167BZC
2012 - Not Available

Abstract: No abstract text available
Text: arrays each of 2 M × 18) for CY7C1512KV18, and 2 M × 36 (2 arrays each of 1 M × 36) for CY7C1514KV18. , inputs for CY7C1512KV18, and 20 address inputs for CY7C1514KV18. These inputs are ignored when the , following sections. The same basic descriptions apply to CY7C1525KV18, and CY7C1514KV18. Functional , CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR® II SRAM Two-Word Burst Architecture 72 , CY7C1512KV18 ­ 4 M × 18 CY7C1514KV18 ­ 2 M × 36 Separate independent read and write data ports Supports


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PDF CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit CY7C1525KV18 CY7C1512KV18
2012 - Not Available

Abstract: No abstract text available
Text: controls D[17:9]. CY7C1514KV18ï€ ï€­ BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18 , arrays each of 1 M × 36) for CY7C1514KV18. Therefore, only 22 address inputs are needed to access the , CY7C1514KV18. These inputs are ignored when the appropriate port is deselected. Q[x:0] OutputData output , CY7C1514KV18. Read Operations The CY7C1512KV18 is organized internally as two arrays of 2 M × 18 , CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR® II SRAM Two-Word Burst Architecture 72


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PDF CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit
2011 - CY7C1512KV18-250BZXI

Abstract: No abstract text available
Text: each of 2 M × 18) for CY7C1512KV18, and 2 M × 36 (2 arrays each of 1 M × 36) for CY7C1514KV18. , CY7C1525KV18, 21 address inputs for CY7C1512KV18, and 20 address inputs for CY7C1514KV18. These inputs are , to CY7C1510KV18, CY7C1525KV18, and CY7C1514KV18. lower 18-bit write data register, provided BWS[1:0 , CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 ® Features Configurations CY7C1510KV18 ­ 8 M × 8 CY7C1525KV18 ­ 8 M × 9 CY7C1512KV18 ­ 4 M × 18 CY7C1514KV18 ­ 2 M × 36 Separate independent read and write


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PDF 72-Mbit CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1512KV18-250BZXI
2014 - Not Available

Abstract: No abstract text available
Text: €­ BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1514KV18ï€ ï€­ BWS0 controls D[8:0], BWS1 , ) for CY7C1512KV18, and 2 M × 36 (2 arrays each of 1 M × 36) for CY7C1514KV18. Therefore, only 22 , CY7C1512KV18, and 20 address inputs for CY7C1514KV18. These inputs are ignored when the appropriate port is , CY7C1514KV18. Read Operations The CY7C1512KV18 is organized internally as two arrays of 2 M × 18 , CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR® II SRAM Two-Word Burst Architecture 72


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PDF CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit
2011 - CY7C1514KV18-333BZI

Abstract: CY7C1512KV18-300BZC
Text: each of 2 M × 18) for CY7C1512KV18, and 2 M × 36 (2 arrays each of 1 M × 36) for CY7C1514KV18. , CY7C1525KV18, 21 address inputs for CY7C1512KV18, and 20 address inputs for CY7C1514KV18. These inputs are , to CY7C1510KV18, CY7C1525KV18, and CY7C1514KV18. Write Operations Write operations are initiated , CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 ® Features Configurations CY7C1510KV18 ­ 8 M × 8 CY7C1525KV18 ­ 8 M × 9 CY7C1512KV18 ­ 4 M × 18 CY7C1514KV18 ­ 2 M × 36 Separate independent read and write


Original
PDF 72-Mbit CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1514KV18-333BZI CY7C1512KV18-300BZC
2009 - Not Available

Abstract: No abstract text available
Text: 2M x 36 (2 arrays each of 1M x 36) for CY7C1514KV18. Therefore, only 22 address inputs are needed to , 20 address inputs for CY7C1514KV18. These inputs are ignored when the appropriate port is deselected , to CY7C1510KV18, CY7C1525KV18, and CY7C1514KV18. lower 18-bit write data register, provided BWS[1:0 , CY7C1512KV18, CY7C1514KV18 ® Configurations CY7C1510KV18 ­ 8M x 8 CY7C1525KV18 ­ 8M x 9 CY7C1512KV18 ­ 4M x 18 CY7C1514KV18 ­ 2M x 36 Separate Independent Read and Write Data Ports Supports concurrent


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PDF 72-Mbit CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 CY7C1510KV18 CY7C1525KV18 CY7C1512KV18
2010 - CY7C1512KV18-250BZXC

Abstract: CY7C1512KV18-250BZI
Text: CY7C1514KV18. Therefore, only 22 address inputs are needed to access the entire memory array of CY7C1510KV18 and CY7C1525KV18, 21 address inputs for CY7C1512KV18, and 20 address inputs for CY7C1514KV18. These , CY7C1514KV18. The CY7C1512KV18 is used with a single clock that controls both the input and output , CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 ® 72-Mbit QDR II SRAM 2-Word Burst , x 18 2-word Burst on all Accesses CY7C1514KV18 ­ 2M x 36 Double Data Rate (DDR


Original
PDF CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit CY7C1510KV18 CY7C1512KV18 CY7C1512KV18-250BZXC CY7C1512KV18-250BZI
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