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CSR31900-0001-00000 (ZPF000000000114685) TE Connectivity (ZPF000000000114685) FIXED FEMALE BLOCK 2POLES + CTS - CSR
CAT-R131-C8908A TE Connectivity (CAT-R131-C8908A) CSR 31000 - RACK POWER SUPPLY - FEMALE
CAT-R131-C8908B TE Connectivity (CAT-R131-C8908B) CSR 31000 - RACK POWER SUPPLY - MALE

CSR BC212 Datasheets Context Search

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1997 - 6116 static ram

Abstract:
Text: during power-up. Software initialization of the CSR (Control Status Register) is not required. A dummy , turn on transients on the bus of the host processor. On reset, the CSR of the 83C451 is programmed to , contents of the CSR is output on port 6 when the port is read by the host. If AFLAG is low, then the , function is being controlled by the address line A0, the CSR contents can be read by the host processor at address 8001H. By testing the CSR contents in this way, the host processor can tell if new data


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PDF AN408 80C451 80C51 6116 static ram 82S163 74HCT373 83C451 87C451 AN408
6116 static ram

Abstract:
Text: host processor during power-up. Software initialization of the CSR (Control Status Register) is not , be set by turn on transients on the bus of the host processor. On reset, the CSR of the 83C451 is , high, the contents of the CSR is output on port 6 when the port is read by the host. If AFLAG is low , 8000H. Since the port select function is being controlled by the address line A0, the CSR contents can be read by the host processor at address 8001H. By testing the CSR contents in this way, the host


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PDF 80C451 AN408 80C51 6116 static ram 82s163 74HCT373 83C451 87C451 AN408
80C451

Abstract:
Text: being controlled by the address line AO, the CSR contents can be read by the host pro cessor at address 6001H. By testing the CSR contents in this way, the host processor can tell if new data has been written , the host wrote to the port. Con versely, the 80C451 can poll the flags in its CSR to see if the host , during powerup. Software initialization of the CSR (Control Status Register) is not required. A dummy , on transients on the bus of the host processor. On reset, the CSR of the 83C451 is programmed to


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PDF AN408 80C451 80C51 80C451, 83C451, 87C451.
1996 - 6116 static ram

Abstract:
Text: during power-up. Software initialization of the CSR (Control Status Register) is not required. A dummy , turn on transients on the bus of the host processor. On reset, the CSR of the 83C451 is programmed to , contents of the CSR is output on port 6 when the port is read by the host. If AFLAG is low, then the , function is being controlled by the address line A0, the CSR contents can be read by the host processor at address 8001H. By testing the CSR contents in this way, the host processor can tell if new data


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PDF 80C451 AN408 80C51 6116 static ram 74HCT373 82S163 83C451 87C451 AN408
1997 - 56-PIN

Abstract:
Text: /O LOGIC BYTE CSR OUTPUT MULTIPLEXER REGISTER ESRs CE OE CUI WE RP DATA , LH28F400SU-NC The LH28F400SU-NC contains a Compatible Status Register ( CSR ) which is 100% compatible with , operation will abort) and the CSR register is cleared. A CMOS Standby mode of operation is enabled when CE , 3 DATA AD = Array Data CSRD = CSR Data ID = Identifier Data WD = Write Data NOTES: 1 , signature codes. 2. The CSR is automatically available after device enters Data Write, Erase or Suspend


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PDF LH28F400SU-NC J63428 SMT96116 56-PIN LH28F400SU-NC NC6016
2012 - Not Available

Abstract:
Text: CSR 2 HS Clock Sourced M /N Pixel Clock PLL B_Y0P B_Y0N B_Y1P B_Y1N B_Y2P B_Y2N B_CLKP B_CLKN B_Y3P B_Y3N LOCAL I C CSR READ SDA IRQ CSR WRITE ADDR Clock Dividers Reset , MIN TYP (1) MAX CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00; 100Ω near end termination 180 245 313 CSR 0x19.3:2=01 and/or CSR 0x19.1:0=01; 100Ω near end termination 215 293 372 CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10; 100Ω near end termination 250 341 430


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PDF SN65DSI84 RGB666 RGB888
2012 - Not Available

Abstract:
Text: DACN CLK LANE LPRX PLL Lock LVDSPLL HSRX CLOCK CIRCUITS PIXEL CLOCK CSR HS Clock Sourced M /N Pixel Clock PLL LOCAL I C CSR READ CSR WRITE 2 Clock Dividers Reset REFCLK EN RSVD1 , OUTPUT CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00; 100 near end termination CSR 0x19.3:2=01 and/or CSR 0x19.1:0=01; 100 near end termination CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10; 100 near end termination CSR 0x19.3:2=11 and/or CSR 0x19.1:0=11; 100 near end termination CSR 0x19.3:2=00 and, or CSR 0x19.1


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PDF SN65DSI84 64-pin
1997 - LH28F400SUB-Z0

Abstract:
Text: CSR OUTPUT MULTIPLEXER REGISTER ESRs CE OE CUI WE RP DATA COMPARATOR ADDRESS , Compatible Status Register ( CSR ) which is 100% compatible with the LH28F008SA Flash memory's Status , reset (any current operation will abort) and the CSR register is cleared. A CMOS Standby mode of , Write Address X = Don't Care 3 DATA AD = Array Data CSRD = CSR Data ID = Identifier Data WD = , manufacturer and device signature codes. 2. The CSR is automatically available after device enters Data Write


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PDF LH28F400SUB-Z0 49-PIN DQ15/ J63428 SMT96108 LH28F400SUB-Z0
2006 - BC358* CSR

Abstract:
Text: Support BC358239A contains 8Mbit of internal Flash memory. When used with the CSR Bluetooth software , BlueCore3-Multimedia System Architecture CS-101560-DSP1 (BC358239A-ds-001P) Production Information © CSR plc 2006 This material is subject to CSR 's non-disclosure agreement. Page 1 of 108 Contents , . 32 CS-101560-DSP1 (BC358239A-ds-001P) Production Information © CSR plc 2006 This material is subject to CSR 's non-disclosure agreement. Page 2 of 108 _äìÉ`çêÉ»PJjìäíáãÉÇá~ Product Data Sheet


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PDF BC358239A 96-ball 16-bit CS-101560-DSP1 BC358239A-ds-001P) BC358239A-ds-001Pc BC358* CSR Qualcomm, MSM 8916 BC358239A BC358239 pm 8921 qualcomm 8921 kalimba dsp BC358 CSR BlueCore 5 Multimedia csr pskey
2006 - CSR 8510

Abstract:
Text: contains 6Mbit of internal Flash memory. When used with the CSR Bluetooth software stack, it provides a , -001Pp Production Information © CSR plc 2006 This material is subject to CSR 's non-disclosure agreement. Page 1 , . 34 BC31A223A-ds-001Pp Production Information © CSR plc 2006 This material is subject to CSR 's non-disclosure agreement. Page 2 of 99 _äìÉ`çêÉTM PJ^ìÇáç=cä~ëÜ Product Data Sheet 3.1 , . 44 7.9 CSR Development Systems


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PDF BC31A223A BC31A223B 96-ball 15-bit BC31A223B BC31A223A-ds-001Pp CSR 8510 CSR 8510 hardware MDR771F CSR BLUECORE VIRTUAL MACHINE csr pskey AUTHENTICATION COPROCESSOR 2.0C CSR 8510 bluetooth BC31A223A CSR USB SPI converter csr schematic usb to spi
2010 - Not Available

Abstract:
Text: CSR / CSRN Series Thick Film Current Sensing Resistors Features: · · · · · · Stackpole , sizes available with narrow terminations (CSRN) Electrical Specifications Type / Code CSR 1/8S CSR 1/8 CSR 1/4 CSR 1/2 CSRN 1S CSR 1 CSRN 1 CSR 2 CSRN 2 CSR 3 Package Type 0402 0603 0805 1206 0815 2010 , % 1M How to Order SEI Type Code Nominal Resistance Tolerance Packaging CSR Type CSR CSRN , marketing@seielect.com CSR / CSRN Series Thick Film Current Sensing Resistors Stackpole Electronics, Inc


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2009 - Not Available

Abstract:
Text: CSR / CSRN Series Thick Film Current Sensing Resistors Features: 9 9 9 9 9 9 Stackpole , sizes available with narrow terminations (CSRN) Electrical Specifications Type / Code CSR 1/8S CSR 1/8 CSR 1/4 CSR 1/2 CSRN 1S CSR 1 CSRN 1S CSR 2 CSRN 2 CSR 3 Package Type 0402 0603 0805 1206 0815 , Resistance Tolerance Packaging CSR Type CSR CSF CSRN CSFN Description Standard Standard RoHS Narrow , marketing@seielect.com CSR / CSRN Series Thick Film Current Sensing Resistors Stackpole Electronics, Inc


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2013 - e5070

Abstract:
Text: Supports ISS and CSR calibration standards Compatible with most industry standard network analyzers , powerful Location Manager function WinCalXE www.cascademicrotech.com 3 CSR SUPPORT Part Number CSR -4 Description GSG (300-500 µm) CSR -5 GS/SG (250-500 µm) CSR -6 GS/SG (50-250 µm) CSR -8 GSG (100-250 µm) CSR -15 GSG (550-1250 µm) CSR -16 GS/SG (500-1250 µm) CSR -30 GSGSG (100 µm) CSR -31 GSGSG (150 µm) CSR -32 GSGSG (200 µm) CSR -33 GSGSG (250 µm


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PDF WinCalXE-DS-1213 e5070
1997 - 28F400

Abstract:
Text: /O LOGIC BYTE CSR OUTPUT MULTIPLEXER REGISTER ESRs CE OE CUI WE RP , Erase can be used. The LH28F400SU-LC contains a Compatible Status Register ( CSR ) which is 100 , operation will abort) and the CSR register is cleared. A CMOS Standby mode of operation is enabled when CE , Care 3 DATA AD = Array Data CSRD = CSR Data ID = Identifier Data WD = Write Data NOTES: 1 , signature codes. 2. The CSR is automatically available after device enters Data Write, Erase or Suspend


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PDF LH28F400SU-LC J63428 SMT96102 28F400 48-pin TSOP 56-PIN CSR application LH28F400SU-LC
2012 - LVDS to mipi bridge

Abstract:
Text: CSR LOCAL I C CSR READ CSR WRITE 2 8 Channel B (Circuit same as Channel A) 8 Clock , otherwise noted) PARAMETER FLATLINK LVDS OUTPUT CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 100 near end termination CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 100 near end termination CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10 100 near end termination CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11 100 near end termination CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 200 near end termination CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 200


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PDF SN65DSI85 64-pin LVDS to mipi bridge RGB MIPI dsi MARKING 3D SOT-32 RGB TO MIPI DSI MHz MIPI
1997 - 28f040

Abstract:
Text: REGISTER ID REGISTER I/O LOGIC CSR OUTPUT MULTIPLEXER REGISTER BE1 BE0 OE CUI WE , to accomplish various functions: · A Compatible Status Register ( CSR ) which is 100% compatible , aborted, the internal control circuit is reset and CSR register is cleared. When the device power up , 3 DATA AD = Array Data CSRD = CSR Data ID = Identifier Data WD = Write Data NOTES: 1 , signature codes. 2. The CSR is automatically available after device enters Data Write, Erase or Suspend


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PDF LH28F040SUTD-Z4 40-PIN J63428 SMT96117 28f040 LH28F008SA LH28F040SUTD-Z4
2012 - Not Available

Abstract:
Text: Clock Sourced M /N Pixel Clock PLL CSR LOCAL I C CSR READ CSR WRITE 2 8 Channel B (Circuit , operating free-air temperature range (unless otherwise noted) PARAMETER FLATLINK LVDS OUTPUT CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 100 near end termination CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 100 near end termination CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10 100 near end termination CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11 100 near end termination CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 200 near end


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PDF SN65DSI85 64-pin
2007 - bcore-an-008P

Abstract:
Text: rates (EDR) to 3-Mbits/s. With the on-chip CSR Bluetooth software stack, it provides a fully , -114838-DSP2 Advance Information © CSR plc 2007 Page 1 of 16 _äìÉ`çêÉ»SJ^ìÇáç=olj Product Data Sheet , CS-114838-DSP2 Advance Information © CSR plc 2007 Page 2 of 16 Status Information Status Information The status of this Product Data Sheet is Advance Information. CSR Product Data Sheets progress according to the following format: Advance Information Information for designers concerning CSR product in


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PDF -90dBm 16-bit BC63C159A 2002/95/EC) CS-114838-DSP2 bcore-an-008P BlueCore6 Selection of i2c eeproms for use with bluecore BC63C159A CS-112584-SP CS-112584-SPP CS-116434-ANP CS-116434-An bcore-an-066P bcore
1997 - 40TSOP

Abstract:
Text: DATA QUEUE REGISTERS ID REGISTER I/O LOGIC CSR OUTPUT MULTIPLEXER REGISTER ESRs , ( CSR ) which is 100% compatible with the LH28F008SA Flash memory's Status Register. This register , (any current operations will abort) and the CSR register is cleared. LH28F004SU-LC MEMORY MAP , Address X = Don't Care 3 DATA AD = Array Data CSRD = CSR Data ID = Identifier Data WD = Write , manufacturer and device signature codes. 2. The CSR is automatically available after device enters Data Write


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PDF LH28F004SU-LC 40-PIN J63428 SMT96110 40TSOP LH28F004SU-LC LH28F008SA
2012 - Not Available

Abstract:
Text: CIRCUITS CLK LANE PIXEL CLOCK SCL CSR 2 HS Clock Sourced M /N Pixel Clock PLL B_Y0P B_Y0N B_Y1P B_Y1N B_Y2P B_Y2N B_CLKP B_CLKN B_Y3P B_Y3N LOCAL I C CSR READ SDA IRQ CSR WRITE ADDR Clock Dividers Reset SN65DSI84 2 Submit Documentation Feedback , CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00; 100 near end termination 180 245 313 CSR 0x19.3:2=01 and/or CSR 0x19.1:0=01; 100 near end termination 215 293 372 CSR 0x19.3:2=10 and, or


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PDF SN65DSI84 64-pin SN65DSI84
2006 - BC41315

Abstract:
Text: the CSR Bluetooth software stack, it provides a fully compliant Bluetooth system to v2.0 + EDR of , i2006BC413159A-db-001P This Material is Subject to CSR 's Non-Disclosure Agreement © 2006 CSR plc BC413159A-db-001Pi This Material is Subject to CSR 's Non-Disclosure Agreement Production Information © CSR plc 2006 , 4 6 BC413159A-db-001Pi This Material is Subject to CSR 's Non-Disclosure Agreement Production Information © CSR plc 2006 Page 2 of 148 _äìÉ`çêÉ»QJ^ìÇáç=olj= Product Data Book 5


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PDF BC413159A 96-ball 15-bit BC413159A-db-001Pi BC41315 BC413159A BC413159 csr plc universal laptop schematic power supply 19v circuit diagram pure tin recommended reflow profile D8PSK Quadrature Phase Shift Keying Modulator Demodulator BlueCore HID CSR BlueCore 4 csr bc413
2012 - LVDS to mipi bridge

Abstract:
Text: CSR LOCAL I C CSR READ CSR WRITE 2 8 Channel B (Circuit same as Channel A) 8 Clock , otherwise noted) PARAMETER FLATLINK LVDS OUTPUT CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 100 near end termination CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 100 near end termination CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10 100 near end termination CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11 100 near end termination CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 200 near end termination CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 200


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PDF SN65DSI85 64-pin LVDS to mipi bridge LVDS to MIPI DSI MIPI bridge pin diagram of IC 1408 RGB666
1997 - 42-PIN

Abstract:
Text: CSR OUTPUT MULTIPLEXER REGISTER ESRs CE OE CUI WE RP DATA COMPARATOR , Compatible Status Register ( CSR ) which is 100% compatible with the LH28F008SA Flash memory's Status , Power-Down state, the WSM is reset (any current operation will abort) and the CSR register is cleared. The , Care 3 DATA AD = Array Data CSRD = CSR Data ID = Identifier Data WD = Write Data NOTES: 1 , signature codes. 2. The CSR is automatically available after device enters Data Write, Erase or Suspend


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PDF LH28F004SU-Z9 42-PIN J63428 SMT96118 LH28F004SU LH28F004SU-Z9
1994 - Not Available

Abstract:
Text: .111 Table 44 CSR 0 Table 45 CSR 1 Table 46 CSR 2 Table 47 CSR 3 Table 48 CSR 4 Table 49 CSR 5 Table 50 CSR 6 Table 51 CSR 7 Table 52 CSR 8 Table 53 CSR 9 Table 54 CSR 10 Table 55 CSR 11 Table 56 CSR 12 Table 57 CSR 13 Table 58 CSR 14 Table 59 CSR 15 Table 60 CSR 16 Table 61 CSR 17 Table 62 CSR 18 Table 63 CSR 19 Table 64 CSR 20 Table 65 CSR 21 Table 66 CSR 22 Table 67 CSR 23 Table 68 CSR 24 Table 69 CSR 25 Table 70 CSR 26 Control


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PDF TC35854F TC35854F. 125oC/20hours
2005 - JESD82-7A

Abstract:
Text: Features The device monitors both DCS# and CSR # inputs and will gate the Qn outputs from changing states when both DCS# and CSR # inputs are high. If either DCS# or CSR # input is low, the Qn outputs will function normally. The RESET input has priority over the DCS# and CSR # control and will force the outputs low. If the DCS#-control functionality is not desired, the CSR # input can be hardwired to ground , D10 D11 D12 D13 D14 1 D17 D18 RST# DCS# CSR # D19 D20 D21 D22 D23 D24 D25 2 VDD


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PDF CY2SSTU32864 25-bit 14-bit CY2SSTU32864 JESD82-7A BA96A DCS complete notes delta v dcs Q11A Q13A t4 a4
Supplyframe Tracking Pixel