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LT1017MJ8/883 Linear Technology LT1017 - Micropower Dual Comparator; Package: CERDIP; Pins: 8; Temperature: Military
LT1018MJ8/883 Linear Technology LT1018 - Micropower Dual Comparator; Package: CERDIP; Pins: 8; Temperature: Military
LM108AJ8 Linear Technology LM108A - Operational Amplifiers; Package: CERDIP; Pins: 8; Temperature: Military
LT1175CDWF#MILDWF Linear Technology LT1175 - 500mA Negative Low Dropout Micropower Regulator; Pins: 5
LTC1041MJ8/883 Linear Technology LTC1041 - BANG-BANG Controller; Package: CERDIP; Pins: 8; Temperature: Military
LTC2904CDDB#TRMPBF Linear Technology LTC2904 - Precision Dual Supply Monitor with Pin-Selectable Thresholds; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C

CRC-16 pin Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2003 - 30291FA

Abstract: BOSCH 0 281 002 018 engine control module bosch CRC-16 pin M30291MAT-XXXHP M30290FCHP M30291FCVHP CRC-16 M30290F8HP 16-MHz
Text: . M16C/29 Group 1. Overview 1.6 Pin Description Table 1.6.1 and 1.6.2 describes the available pins , M16C/29 Group SINGLE-CHIP 16 -BIT CMOS MICROCOMPUTER REJ03B0072-0030Z Rev.0.30 2004.06.15 1 , CMOS process using a M16C/60 Series CPU core and is packaged in a 64- pin and 80- pin plastic molded QFP , of M16C/29 group 80- pin device. Table 1.2.2 lists performance outline of M16C/29 group 64- pin device. Table 1.2.1. Performance outline of M16C/29 group (80- pin device) Item Performance CPU Number of


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PDF M16C/29 16-BIT REJ03B0072-0030Z M16C/60 64-pin 80-pin 30291FA BOSCH 0 281 002 018 engine control module bosch CRC-16 pin M30291MAT-XXXHP M30290FCHP M30291FCVHP CRC-16 M30290F8HP 16-MHz
2010 - EP2AGX125

Abstract: EP2AGX190 EP2AGX260 EP2AGX45 EP2AGX65
Text: use by the CRC_ERROR pin . This is the 16 -bit CRC that is embedded in every configuration data , Pin Description" on page 10­4 "Error Detection Block" on page 10­5 "Error Detection , engine generates 16 CRC check bits per frame and then stores them into the configuration random access memory (CRAM). The CRAM chain used for storing CRC check bits is 16 -bits wide; its length is equal to , software. A single 16 -bit CRC calculation is done on a per-frame basis. After it has finished the CRC


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PDF AIIGX51010-3 EP2AGX125 EP2AGX190 EP2AGX260 EP2AGX45 EP2AGX65
2010 - crc 16 verilog

Abstract: EP4SE820 EP4SE230 EP4SE360 EP4SGX180 EP4SGX290 EP4SGX360 EP4SGX70
Text: ability ( 16 -bit CRC), which occurs during user mode to be used by the CRC_ERROR pin . If an error , Detection Pin Description" on page 11­5 "Error Detection Block" on page 11­6 "Error Detection , CRC engine generates 16 CRC check bits per frame and then stores them in CRAM. The CRAM chain used for storing the CRC check bits is 16 bits wide and its length is equal to the number of frames in the , Chapter 11: SEU Mitigation in Stratix IV Devices User Mode Error Detection 11­3 A single 16 -bit CRC


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PDF SIV51011-3 crc 16 verilog EP4SE820 EP4SE230 EP4SE360 EP4SGX180 EP4SGX290 EP4SGX360 EP4SGX70
CRC16

Abstract: CRC-16 CRC-16 pin A001 ST01 modbus RS485
Text: supply 1.6 . I/O 1.7. Serial interface 1.8. Integrated protection 2. CONNECTION AND MECHANICAL DATA , PROTOCOL 7.1 Error check (CRC- 16 ) 7.2 Master to one slave communication frame 7.3 Broadcast , protected against inverted polarity connection. PINS FUNCTIONS Pin Name In2,In4,In5 In1 In3 InEn , OUT1 (drive ok) = active if drive is OK. OUT2 (Motor Status) = active if motor is stopped. 1.6 , J1 Pin Nr. Clock and direction ( Standard mode ) Pin Name Serial mode 1 + AT Vdc


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PDF ST57-01C-xx CRC-16) CRC-16 CRC16 CRC-16 CRC-16 pin A001 ST01 modbus RS485
EP3SE50

Abstract: implement 16-bit CRC in transmitter and receiver 2N50
Text: ( 16 -bit CRC) during user mode, for use by the CRC_ERROR pin . The second type , the configuration stage. A parallel CRC engine generates 16 CRC check bits per frame and then stores , bits is 16 bits in width and its length is equal to the frame length of the device. User Mode Error , process. You set the clock divide factor in the option setting in the Quartus II software. A single 16 , , the resulting 16 -bit signature is hex 0000 if there are no detected CRAM bit errors in a frame by the


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PDF SIII51015-1 EP3SE50 implement 16-bit CRC in transmitter and receiver 2N50
2010 - EP3SE50

Abstract: implement 16-bit CRC in transmitter and receiver "Error Detection" error detection codes EP3SL260
Text: checking ability ( 16 -bit CRC) during user mode, for use by the CRC_ERROR pin . If an error occurs , CRC engine generates 16 CRC check bits per frame and stores them into CRAM. The CRAM chain used for storing CRC check bits is 16 bits wide; its length is equal to the number of frames in the device , Stratix III Devices User Mode Error Detection 15­3 A single 16 -bit CRC calculation is done on a per-frame basis. Once it has finished the CRC calculation for a frame, the resulting 16 -bit signature is


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PDF SIII51015-1 EP3SE50 implement 16-bit CRC in transmitter and receiver "Error Detection" error detection codes EP3SL260
BR2477a

Abstract: BR1220 FIPS-197 implement 16-bit CRC in transmitter and receiver
Text: ( 16 -bit CRC) during user mode, for use by the CRC_ERROR pin . The second type , . A parallel CRC engine generates 16 CRC check bits per frame and then stores them into registers. The configuration random access memory (CRAM) chain used for storing CRC check bits is 16 bits in , process. You set the clock divide factor in the option setting in the Quartus II software. A single 16 , , the resulting 16 -bit signature is hex 0000 if there are no detected CRAM bit errors in a frame by the


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PDF SIII51 BR2477a BR1220 FIPS-197 implement 16-bit CRC in transmitter and receiver
2003 - Not Available

Abstract: No abstract text available
Text: generated from the incoming data stream on the D input pin . CCITT Recommendation G. 704 defines the 16 frame , ) Symbol Pin No. DP48 MFQ3 16 HP44 15 Mode name (see note 1) RX Pin name and description HDB3 Decoder , this input during timeslot 16 . This pin is unused since the D input of the Timeslot 16 Receiver is , timeslot 16 is input on this pin . Digital ground,OV. (Note 2) MODE CLK STM P CRC 27 28 29 30 31 25 , pin during timeslot 16 . This output is low at all other times. Timeslot Zero Receiver (RXTSZ


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PDF MV1403 DS3046-2 MV1403 CLA60000 MV1403. TXTS16
2001 - rx2 208

Abstract: No abstract text available
Text: generated from the incoming data stream on the D input pin . CCITT Recommendation G. 704 defines the 16 frame , ) Symbol Pin No. DP48 MFQ3 16 HP44 15 Mode name (see note 1) RX Pin name and description HDB3 Decoder , this input during timeslot 16 . This pin is unused since the D input of the Timeslot 16 Receiver is , timeslot 16 is input on this pin . Digital ground,OV. (Note 2) MODE CLK STM P CRC 27 28 29 30 31 25 , pin during timeslot 16 . This output is low at all other times. Timeslot Zero Receiver (RXTSZ


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PDF MV1403 DS3046-2 MV1403 CLA60000 MV1403. TXTS16 rx2 208
1993 - HDB3 to nrz

Abstract: HDB3 Hp TX2 MV1403 FRS15 nrz to hdb3 CLA60000 HDB-3 FRS13 FRS Receiver
Text: 24 _ 16 17 18 19 20 21 22 23 Pin name and description 11 MV1403 , This pin is unused since the D input of the Timeslot 16 Receiver is connected intermally to the , is high only during timeslot 16 . MFQ7 MFQ8 Pin No. 39 40 36 37 Pin name and , bursts produced by this macrocell are output at 2.048MHz on this pin during timeslot 16 . This output is , MFD6 LIA 15 34 TZS MFQ3 16 33 FRS MFQ4 17 32 MFD5 MFQ5 18


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PDF MV1403 DS3046-2 MV1403 CLA60000 MV1403. HDB3 to nrz HDB3 Hp TX2 FRS15 nrz to hdb3 HDB-3 FRS13 FRS Receiver
2011 - crc 64

Abstract: CRC32-C CRC-15-CAN CRC32C CRC-8 ccitt
Text: standard polynomial is given in the tool tip. The default is CRC- 16 . Polynomial Name Custom CRC-1 CRC , ) PSoC CreatorTM Component Datasheet ® Polynomial Name CRC-8 CRC-8-SAE CRC-10 CRC-12 CRC-15-CAN CRC- 16 -CCITT 8 8 7 4 6 3 4 2 2 Polynomial x +x +x +x +x +1 x +x +x +x +1 x x x x 10 12 15 16 Use General , , CRCCCITT USB +x +1 CRC- 16 CRC-24-Radix64 CRC-32-IEEE802.3 CRC-32C CRC-32K CRC-64-ISO CRC-64-ECMA x 16 24 +x 15 23 +x +1 18 2 x +x +x +x+1 x +x +x 2 +x +x+1 32 28 32 26 +x +x 17


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PDF
2002 - G703

Abstract: No abstract text available
Text: generated from the incoming data stream on the D input pin . CCITT Recommendation G. 704 defines the 16 frame , ) Symbol Pin No. DP48 MFQ3 16 HP44 15 Mode name (see note 1) RX Pin name and description HDB3 Decoder , this input during timeslot 16 . This pin is unused since the D input of the Timeslot 16 Receiver is , timeslot 16 is input on this pin . Digital ground,OV. (Note 2) MODE CLK STM P CRC 27 28 29 30 31 25 , pin during timeslot 16 . This output is low at all other times. Timeslot Zero Receiver (RXTSZ


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PDF MV1403 DS3046-2 MV1403 CLA60000 MV1403. TXTS16 G703
2004 - Not Available

Abstract: No abstract text available
Text: generated from the incoming data stream on the D input pin . CCITT Recommendation G. 704 defines the 16 frame , ) Symbol Pin No. DP48 MFQ3 16 HP44 15 Mode name (see note 1) RX Pin name and description HDB3 Decoder , this input during timeslot 16 . This pin is unused since the D input of the Timeslot 16 Receiver is , timeslot 16 is input on this pin . Digital ground,OV. (Note 2) MODE CLK STM P CRC 27 28 29 30 31 25 , pin during timeslot 16 . This output is low at all other times. Timeslot Zero Receiver (RXTSZ


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PDF MV1403 DS3046-2 MV1403 CLA60000 MV1403. TXTS16
2001 - Not Available

Abstract: No abstract text available
Text: generated from the incoming data stream on the D input pin . CCITT Recommendation G. 704 defines the 16 frame , ) Symbol Pin No. DP48 MFQ3 16 HP44 15 Mode name (see note 1) RX Pin name and description HDB3 Decoder , this input during timeslot 16 . This pin is unused since the D input of the Timeslot 16 Receiver is , timeslot 16 is input on this pin . Digital ground,OV. (Note 2) MODE CLK STM P CRC 27 28 29 30 31 25 , pin during timeslot 16 . This output is low at all other times. Timeslot Zero Receiver (RXTSZ


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PDF MV1403 DS3046-2 MV1403 CLA60000 MV1403. TXTS16
2006 - Not Available

Abstract: No abstract text available
Text: ) Symbol Pin No. DP48 MFQ3 16 HP44 15 Mode name (see note 1) RX Pin name and description HDB3 Decoder , this input during timeslot 16 . This pin is unused since the D input of the Timeslot 16 Receiver is , timeslot 16 is input on this pin . Digital ground,OV. (Note 2) MODE CLK STM P CRC 27 28 29 30 31 25 , pin during timeslot 16 . This output is low at all other times. Timeslot Zero Receiver (RXTSZ , 13 14 15 16 17 18 19 20 21 22 23 24 37 36 35 34 33 32 31 30 29 28 27 26 25 DP48 13 GND1 17


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PDF MV1403 DS3046-2 MV1403 CLA60000
2002 - transponder chip

Abstract: EM4056 EM4056B6CB2RC EM4056B6CI2LC EM4056B6WP11 EM4056B6WW11E marin transponder EM4056B
Text: Safety (Incl. PIN Code) Laser ROM 3 x 16 bit Adder Write/Read Protection (OTP) Modulator , organised in 125 words of 16 bits, each word can be irreversibly protected against reading or/and writing , . Features · · · 2 kBits EEPROM organized in 125 words of 16 bits 3 words of 16 Bits Laser ROM for , · · · · · · · · · · · Programmable PIN coverage of the memory (0, 25, 50, 75 or 100 % , tags) PIN Code identification linked with counter of false attempts On chip arithmetic operation


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PDF EM4056 EM4056 D/438 transponder chip EM4056B6CB2RC EM4056B6CI2LC EM4056B6WP11 EM4056B6WW11E marin transponder EM4056B
1994 - 2RD6

Abstract: RB35 TDNB0
Text: selectable CRC polynomials: CRC- 16 and CRC-32 · 36-bit bus interface · Supports normal packet termination , performed using a choice of CCITT CRC- 16 or CRC-32 polynomials. On the bus interface side, 36-bit (32 , -05101C TABLE OF CONTENTS SECTION PAGE Block Diagram Block Diagram Description Pin Diagram Schematic Symbol Pin Descriptions Absolute Maximum Ratings Thermal Characteristics Power Requirements Input and , 16 16 16 17-18 19-37 38-48 38 43 49 50 50 50 51 -2- TXC-05101C-MB Ed. 1A, April 1995


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PDF TXC-05101C CRC-16 CRC-32 36-bit TXC-05101C-MB 2RD6 RB35 TDNB0
2010 - BR1220

Abstract: BR2477A FIPS-197
Text: is calculated during the configuration stage. A parallel CRC engine generates 16 CRC check bits per frame and stores them into CRAM. The CRAM chain used for storing CRC check bits is 16 bits wide; its , Detection 15­3 A single 16 -bit CRC calculation is done on a per-frame basis. Once it has finished the CRC calculation for a frame, the resulting 16 -bit signature is hex 0000 if there are no detected CRAM , Stratix III devices calculates CRC check bits for each frame and pulls the CRC_ERROR pin high when it


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PDF 20dated BR1220 BR2477A FIPS-197
1993 - BT806

Abstract: bt8070 Bt8069 BT8069B HDB3 BROOKTREE bt8 l8075
Text: D 24- Pin Plastic DIP 16 INCHES MIN. MAX. 1.230 1.260 0.530 0.550 0.140 0.160 0.015 , Options ­ 24- Pin Plastic DIP ­ 28- Pin PLCC RPOS RNEG RX RPOS RNRZ RCLK RNEG RX , . The Bt8075 interface signals are listed by pin number Table 1. This table alsi details pin assignments. Interface signal definitions are given in Table 2. Graphic representation of the pin assignments , Transceiver 24 23 22 21 20 19 18 17 16 15 14 13 TMASYN RMASYN RSP1 TMAX TCLK VSS TSP2


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PDF Bt8075 24-Pin 28-Pin BT806 bt8070 Bt8069 BT8069B HDB3 BROOKTREE bt8 l8075
1993 - Not Available

Abstract: No abstract text available
Text: generated from the incoming data stream on the D input pin . CCITT Recommendation G. 704 defines the 16 frame , ) Symbol Pin No. DP48 MFQ3 16 HP44 15 Mode name (see note 1) RX Pin name and description HDB3 Decoder , this input during timeslot 16 . This pin is unused since the D input of the Timeslot 16 Receiver is , timeslot 16 is input on this pin . Digital ground,OV. (Note 2) MODE CLK STM P CRC 27 28 29 30 31 25 , pin during timeslot 16 . This output is low at all other times. Timeslot Zero Receiver (RXTSZ


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PDF MV1403 DS3046-2 MV1403 CLA60000 MV1403. TXTS16
2008 - cyclic redundancy check verilog source

Abstract: vhdl code CRC 32 JTAG error detection code in vhdl AN25 EP1S60 crc 16 verilog
Text: page 8 "Software Support" on page 11 "Recovering from CRC Errors" on page 16 "Conclusion" on page 16 , the operation of the error detection CRC circuitry at the CRC_ERROR pin . Stratix II and Stratix II , register. Table 2 describes the CRC_ERROR pin . Tables 3 and 4 show the CRC_ERROR pin locations for the Stratix and Stratix GX device families. CRC_ERROR Pin-Outs Table 2. CRC_ERROR Pin Description Pin Name Description CRC_ERROR 4 Pin Type I/O, output Active high signal that indicates


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PDF
2005 - em marin

Abstract: RF pcb antenna 125khz marin transponder ta1p EM4056B6WW11E EM4056B6WP11 EM4056B6CI2LC EM4056B6CB2RC EM4056 programmable read write transponder
Text: Transponder trp Ega nEga 8 bits X8 CRC Fig. 15 Login Compares a 16 bit data word with the PIN , organised in 125 words of 16 bits, each word can be irreversibly protected against reading or/and writing , . Features · · · 2 kBits EEPROM organized in 125 words of 16 bits 3 words of 16 Bits Laser ROM for , · · · · · · · · · · · Programmable PIN coverage of the memory (0, 25, 50, 75 or 100 % , tags) PIN Code identification linked with counter of false attempts On chip arithmetic operation


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PDF EM4056 EM4056 em marin RF pcb antenna 125khz marin transponder ta1p EM4056B6WW11E EM4056B6WP11 EM4056B6CI2LC EM4056B6CB2RC programmable read write transponder
2010 - error detection codes

Abstract: M20K "Error Detection" error detection 5SGX
Text: Error Detection and Correction" on page 10­2 "Error Detection Pin Description" on page 10­5 , Detection Configuration Error Detection In configuration mode, a frame-based 16 -bit configuration CRC is , , the Stratix V device calculates the 16 -bit configuration CRC value based on the frame of data that is received and compares it against the pre-calculated 16 -bit configuration CRC value in the data stream. If the 16 -bit configuration CRC values do not match, nSTATUS is set low. Configuration continues until


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PDF SV51011-1 error detection codes M20K "Error Detection" error detection 5SGX
2009 - AN-539 APPLICATION NOTE

Abstract: AN357 AN-539-1
Text: Detection Block Diagram 16 -Bit CRC Calculation and Error Readback bit stream with expected CRC , 30 16 Error Message CRC_ERROR Register 46 Error Injection Block Fault Injection , pre-computed 16 -bit frame-based CRC is stored in every configuration data frame. This CRC data contains the , pre-computed CRC shifts into the CRC circuitry. Meanwhile, a parallel CRC engine in the FPGA calculates 16 CRC , Memory (CRAM). The CRAM chain used for storing CRC check bits is 16 -bits wide and its length is equal


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PDF AN-539-1 AN-539 APPLICATION NOTE AN357
2012 - Not Available

Abstract: No abstract text available
Text: =10μA(Typ) - Power down mode : Power down current =10nA(Typ) - Package: 16-pin TSSOP (FPT-16P-M08) â , Serial Serial Clock pin 16 SI Serial Serial Data Input pin 2 SO Serial Serial , rising edge. SO is output synchronously to a falling edge. 16 SI Serial Data Input pin This is , Direction of Feed) DS411-00003-1v0-E MB97R803A/B, MB97R804A/B ■PACKAGE DIMENSION 16-pin plastic , -16P-M08) 16-pin plastic TSSOP (FPT-16P-M08) Note 1) Pins width and pins thickness include plating


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PDF DS411-00003-1v0-E MB97R803A/B, MB97R804A/B MB97R804A/
Supplyframe Tracking Pixel