The Datasheet Archive

CLK48 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1997 - CLK48

Abstract: No abstract text available
Text: only those FFs clocked by CLK48 USB DEMO ­ 6 Defining Fast Setup for CLK48 Input 15 ns input delay (setup) constraint now applied to CLK48 input pin USB DEMO ­ 7 FPGA Express Writes


Original
PDF CLK48 CLK48
LAD1 5V

Abstract: LAD1 12v IT8761E GPIO20 IN4001 GPIO-12 IT8701F LAD2 12V GPIO14 CLK48
Text: CLOCK Lines Layout/Routing Guidelines.(Pin2: CLK48 & Pin11:LCLK) 1)If possible, please avoid using any , remove the pull-up resistor of pin18 GPIO12/LDRQ#. VCC RXD1 TO ICH VCC CLK48 V33 PCIRST# LAD0 LAD1 LAD2 LAD3 LFRAME# V33 PCICLK SERIRQ CLK48 V33 1 2 3 4 5 6 7 8 9 10 11 , /FSIDE1# GPIO21/FINDEX# GND VCC CLK48 V33 LRESET# LAD0 LAD1 LAD2 LAD3 LFRAME# V33 LCLK


Original
PDF IT8761E ITSA-CG-99602 IT8701F 220PF GPIO10/MSDAT GPIO11/MSCLK LAD1 5V LAD1 12v GPIO20 IN4001 GPIO-12 LAD2 12V GPIO14 CLK48
2000 - TUSB2140B

Abstract: m93c46 HC49U TPS2041 TPS2044 TUSB2036 TUSB2077A CLK48 TUSB2043
Text: ) EXTMEM V CC DP0PUR GND XTAL2 XTAL1/ CLK48 SUSPND MODE VF PACKAGE (TOP VIEW) 32 , OFFICE BOX 655303 · DALLAS, TEXAS 75265 SUSPND XTAL1/ CLK48 29 26 SIE Interface Logic , MODE is high, the clock on XTAL1/ CLK48 is selected as the clock source and 48-MHz oscillator or other , 3, 25 NAME PWRON1 ­ PWRON3 VF 3.3-V supply voltage XTAL1/ CLK48 30 I Crystal 1/48-MHz Clock Input. When MODE is low, XTAL1/ CLK48 is a 6-MHz crystal input with 50% duty cycle. An


Original
PDF TUSB2036 SLLS372 TUSB2140B m93c46 HC49U TPS2041 TPS2044 TUSB2036 TUSB2077A CLK48 TUSB2043
2000 - TUSB2140B

Abstract: CLK48 TUSB2043 TUSB2140
Text: Flat Pack) D D D D D D VF PACKAGE (TOP VIEW) XTAL1/ CLK48 EXTMEM SUSPND MODE DP0PUR , XTAL1/ CLK48 XTAL2 MODE RESET EXTMEM SIE Interface Logic 6 Serial EEPROM Interface 5 EEDATA , XTAL1/ CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source can be , (see Table 1) 3.3-V supply voltage I Crystal 1/48-MHz Clock Input. When MODE is low, XTAL1/ CLK48 is a 6 , by the ASIC logic. When MODE is high, XTAL1/ CLK48 acts as the input of the 48 MHz clock and the


Original
PDF TUSB2036 SLLS372 TUSB2140B CLK48 TUSB2043 TUSB2140
2002 - Z0100

Abstract: Z0122 CRC-16 and verilog CLK48
Text: PORT INTERFACE Clk12 Clk48 Test_PLLCLK Figure 2: Logic Symbol for USB 1.1 Host Controller 8


Original
PDF Z0122 Z0100 Z0100 Z0122 CRC-16 and verilog CLK48
2000 - TUSB2140B

Abstract: TUSB2043
Text: Pack) D D D D D D VF PACKAGE (TOP VIEW) XTAL1/ CLK48 EXTMEM SUSPND MODE DP0PUR , SIE M 1 U X 0 30 OSC/PLL 29 31 4 26 XTAL1/ CLK48 XTAL2 MODE RESET EXTMEM SIE Interface , or oscillator can be used. When MODE is high, the clock on XTAL1/ CLK48 is selected as the clock , I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/ CLK48 is a 6-MHz crystal input with 50% duty , MODE is high, XTAL1/ CLK48 acts as the input of the 48-MHz clock and the internal APLL logic is bypassed


Original
PDF TUSB2036 SLLS372C TUSB2140B TUSB2043
2000 - TUSB2140B

Abstract: HC49U M93C46 SLLS372C TPS2044 TUSB2036 TUSB2077A TUSB2043
Text: XTAL2 XTAL1/ CLK48 SUSPND MODE VF PACKAGE (TOP VIEW) 32 31 30 29 28 27 26 25 DP0 DM0 , 655303 · DALLAS, TEXAS 75265 SUSPND XTAL1/ CLK48 29 26 SIE Interface Logic DP0PUR , MODE is high, the clock on XTAL1/ CLK48 is selected as the clock source and 48-MHz oscillator or other , 3, 25 3.3-V supply voltage XTAL1/ CLK48 30 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/ CLK48 is a 6-MHz crystal input with 50% duty cycle. An internal APLL generates the 48


Original
PDF TUSB2036 SLLS372C TUSB2140B HC49U M93C46 TPS2044 TUSB2036 TUSB2077A TUSB2043
2000 - TUSB2140B

Abstract: TUSB2043 TUSB2036 TPS2044 TPS2041 SLLS372A M93C46 HC49U CLK48 amplifier with port USB diagram
Text: S-PQFP-G For Low-Profile Quad Flat Pack) EXTMEM V CC DP0PUR GND XTAL2 XTAL1/ CLK48 , 655303 · DALLAS, TEXAS 75265 SUSPND XTAL1/ CLK48 29 26 SIE Interface Logic DP0PUR , oscillator can be used. When MODE is high, the clock on XTAL1/ CLK48 is selected as the clock source and 48 , Table 1) VCC 3, 25 NAME PWRON1 - PWRON3 VF 3.3-V supply voltage XTAL1/ CLK48 30 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/ CLK48 is a 6-MHz crystal input with 50


Original
PDF TUSB2036 SLLS372A TUSB2140B TUSB2043 TUSB2036 TPS2044 TPS2041 M93C46 HC49U CLK48 amplifier with port USB diagram
2000 - TUSB2140B

Abstract: TUSB2043
Text: Low-Profile Quad Flat Pack) VF PACKAGE (TOP VIEW) XTAL1/ CLK48 EXTMEM SUSPND MODE DP0PUR XTAL2 , XTAL1/ CLK48 XTAL2 MODE RESET EXTMEM SIE Interface Logic 6 Serial EEPROM Interface 5 EEDATA , XTAL1/ CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source can be , (see Table 1) 3.3-V supply voltage I Crystal 1/48-MHz Clock Input. When MODE is low, XTAL1/ CLK48 is a 6 , by the ASIC logic. When MODE is high, XTAL1/ CLK48 acts as the input of the 48 MHz clock and the


Original
PDF TUSB2036 SLLS372 TUSB2036VF TUSB2036VFR TUSB2036, TUSB2140B TUSB2043
2000 - m93c46

Abstract: TUSB2140B SLLS372C tusb2036vfg4 HC49U TPS2044 TUSB2036 TUSB2077A TUSB2043
Text: XTAL2 XTAL1/ CLK48 SUSPND MODE VF PACKAGE (TOP VIEW) 32 31 30 29 28 27 26 25 DP0 DM0 , 655303 · DALLAS, TEXAS 75265 SUSPND XTAL1/ CLK48 29 26 SIE Interface Logic DP0PUR , MODE is high, the clock on XTAL1/ CLK48 is selected as the clock source and 48-MHz oscillator or other , 3, 25 3.3-V supply voltage XTAL1/ CLK48 30 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/ CLK48 is a 6-MHz crystal input with 50% duty cycle. An internal APLL generates the 48


Original
PDF TUSB2036 SLLS372C m93c46 TUSB2140B tusb2036vfg4 HC49U TPS2044 TUSB2036 TUSB2077A TUSB2043
2002 - b 57828

Abstract: AD27 USS-344 8259 Interrupt Controller CLK48
Text: DPLS2 VSST VDDT DMNS1 DPLS1 DMNS0 DPLS0 VSST VDDT RREF VDDA XHI XLO/ CLK48 VSSA CLK48STOP , PRTPWR0 PWRFLT0N PRTPWR1 PWRFLT1N VDD CLK48STOP VSSA XLO/ CLK48 XHI VDDA RREF VDDT VSST DPLS0 , Symbol* Type 77 79 102 104 75 81 PWRFLT0N PWRFLT1N PWRFLT2N PWRFLT3N CLK48 CLK48STOP , CLK48 48 MHz OSC PRTPWR0 PWRFLT0N CLK48STOP 5 Vdc-5 Vdc SWITCHED REGULATOR VBUS = 5 Vdc , ROOT HUB AND HOST SIE RX DPLL LEGACY SUPPORT POWER MNGMNT LOGIC CLK48STOP PMEN


Original
PDF USS-344 32-bit, PB01-114CMPR-2 PB01-114CMPR-1) b 57828 AD27 8259 Interrupt Controller CLK48
2000 - TUSB2140

Abstract: TUSB2036 TUSB2140B TUSB2043
Text: Low-Profile Quad Flat Pack) VF PACKAGE (TOP VIEW) XTAL1/ CLK48 EXTMEM SUSPND MODE DP0PUR XTAL2 , XTAL1/ CLK48 XTAL2 MODE RESET EXTMEM SIE Interface Logic 6 Serial EEPROM Interface 5 EEDATA , XTAL1/ CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source can be , (see Table 1) 3.3-V supply voltage I Crystal 1/48-MHz Clock Input. When MODE is low, XTAL1/ CLK48 is a 6 , by the ASIC logic. When MODE is high, XTAL1/ CLK48 acts as the input of the 48 MHz clock and the


Original
PDF TUSB2036 SLLS372 TUSB2036VF TUSB2036, TUSB2036VFR TUSB2140 TUSB2140B TUSB2043
2000 - CLK48

Abstract: TUSB2140B TUSB2043 TUSB2140
Text: Pack) D D D D D D VF PACKAGE (TOP VIEW) XTAL1/ CLK48 EXTMEM SUSPND MODE DP0PUR , SIE M 1 U X 0 30 OSC/PLL 29 31 4 26 XTAL1/ CLK48 XTAL2 MODE RESET EXTMEM SIE Interface , or oscillator can be used. When MODE is high, the clock on XTAL1/ CLK48 is selected as the clock , I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/ CLK48 is a 6-MHz crystal input with 50% duty , MODE is high, XTAL1/ CLK48 acts as the input of the 48-MHz clock and the internal APLL logic is bypassed


Original
PDF TUSB2036 SLLS372C CLK48 TUSB2140B TUSB2043 TUSB2140
2000 - Not Available

Abstract: No abstract text available
Text: Flat Pack) VF PACKAGE (TOP VIEW) XTAL1/ CLK48 EXTMEM SUSPND MODE DP0PUR 32 31 3029 2827 , XTAL1/ CLK48 XTAL2 MODE RESET EXTMEM SIE Interface Logic 6 Serial EEPROM Interface 5 EEDATA , . When MODE is high, the clock on XTAL1/ CLK48 is selected as the clock source and 48-MHz oscillator or , TERMINAL FUNCTIONS (continued) TERMINAL NAME VCC XTAL1/ CLK48 XTAL2 NO. 3, 25 30 29 I O I/O DESCRIPTION 3.3-V supply voltage Crystal 1/48-MHz clock input. When MODE is low, XTAL1/ CLK48 is a 6-MHz crystal input with


Original
PDF TUSB2036 SLLS372F
2000 - TUSB2140B

Abstract: TUSB2043
Text: ) XTAL1/ CLK48 EXTMEM SUSPND MODE DP0PUR XTAL2 GND 32 31 30 29 28 27 26 25 DP0 DM0 VCC , / CLK48 XTAL2 MODE RESET EXTMEM SIE Interface Logic 6 Serial EEPROM Interface 5 EEDATA/GANGED , or oscillator can be used. When MODE is high, the clock on XTAL1/ CLK48 is selected as the clock , I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/ CLK48 is a 6-MHz crystal input with 50% duty , MODE is high, XTAL1/ CLK48 acts as the input of the 48-MHz clock and the internal APLL logic is bypassed


Original
PDF TUSB2036 SLLS372B TUSB2140B TUSB2043
2000 - USB TRANSCEIVER

Abstract: No abstract text available
Text: Low-Profile Quad Flat Pack) VF PACKAGE (TOP VIEW) XTAL1/ CLK48 EXTMEM SUSPND MODE GND 32 31 , /Resume Logic and Frame Timer SIE M 1 U X 0 30 OSC/PLL 29 31 4 26 XTAL1/ CLK48 XTAL2 MODE RESET , XTAL1/ CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source can be , XTAL1/ CLK48 XTAL2 NO. 3, 25 30 29 I O I/O DESCRIPTION 3.3-V supply voltage Crystal 1/48-MHz clock input. When MODE is low, XTAL1/ CLK48 is a 6-MHz crystal input with 50% duty cycle. An internal APLL generates


Original
PDF TUSB2036 SLLS372E USB TRANSCEIVER
2001 - PB-0111

Abstract: 8259 Interrupt Controller CLK48
Text: VDDT RREF VDDA XHI XLO/ CLK48 VSSA CLK48STOP VDD PWRFLT1N PRTPWR1 PWRFLT0N PRTPWR0 SMIN VSS VDD IRQ12 , PWRFLT3N CLK48 CLK48STOP VDDT VSST RREF VDDA VSSA XHI XLO/ CLK48 Type Input Input Input Input Input Output , designer if not desired. 3.3 Vdc CLK48 CLK48STOP 5 Vdc 48 MHz OSC PRTPWR0 PWRFLT0N 5 Vdc-5 Vdc , PROCESSOR BLOCK HSIE S/M FIFO DPLL RX MIRQ121 KIRQ1I A20I IRQ1 IRQ12 A20MN SMIN CLK48STOP PMEN LEGACY , MIRQ12I KIRQ1I A20I A20MN IRQ1 IRQ12 VDD VSS SMIN PRTPWR0 PWRFLT0N PRTPWR1 PWRFLT1N VDD CLK48STOP VSSA XLO


Original
PDF USS-344 32-bit, PB01-114CMPR-2 PB01-114CMPR-1) PB-0111 8259 Interrupt Controller CLK48
2000 - CLK48

Abstract: TUSB2140B TUSB2043 TUSB2140
Text: Pack) D D D D D D VF PACKAGE (TOP VIEW) XTAL1/ CLK48 EXTMEM SUSPND MODE DP0PUR , SIE M 1 U X 0 30 OSC/PLL 29 31 4 26 XTAL1/ CLK48 XTAL2 MODE RESET EXTMEM SIE Interface , or oscillator can be used. When MODE is high, the clock on XTAL1/ CLK48 is selected as the clock , I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/ CLK48 is a 6-MHz crystal input with 50% duty , MODE is high, XTAL1/ CLK48 acts as the input of the 48-MHz clock and the internal APLL logic is bypassed


Original
PDF TUSB2036 SLLS372C CLK48 TUSB2140B TUSB2043 TUSB2140
2000 - TUSB2036

Abstract: TUSB2140B tusb2036vfg4 TPS2041 TPS2044 M93C46 TUSB2077A HC49U CLK48 TUSB2043
Text: S-PQFP-G For Low-Profile Quad Flat Pack) EXTMEM V CC DP0PUR GND XTAL2 XTAL1/ CLK48 , DALLAS, TEXAS 75265 SUSPND XTAL1/ CLK48 29 26 SIE Interface Logic DP0PUR XTAL2 MODE , device and 6-MHz crystal or oscillator can be used. When MODE is high, the clock on XTAL1/ CLK48 is , XTAL1/ CLK48 30 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/ CLK48 is a 6-MHz crystal , the ASIC logic. When MODE is high, XTAL1/ CLK48 acts as the input of the 48-MHz clock and the internal


Original
PDF TUSB2036 SLLS372B TUSB2036 TUSB2140B tusb2036vfg4 TPS2041 TPS2044 M93C46 TUSB2077A HC49U CLK48 TUSB2043
2000 - Not Available

Abstract: No abstract text available
Text: XTAL1/ CLK48 XTAL2 3 22 4 21 5 20 6 19 7 18 17 8 NP3 NPINT1 , DP0PUR SUSPND XTAL1/ CLK48 XTAL2 MODE RESET EXTMEM EEDATA/GANGED EECLK NP3 NPINT(1- 0 , -MHz crystal or oscillator can be used. When MODE is high, the clock on XTAL1/ CLK48 is selected as the clock , DESCRIPTION 3.3-V supply voltage XTAL1/ CLK48 30 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/ CLK48 is a 6-MHz crystal input with 50% duty cycle. An internal APLL generates the 48-MHz and 12


Original
PDF TUSB2036 SLLS372E XTAL1/CLK48
2000 - SLLS372E

Abstract: No abstract text available
Text: Low-Profile Quad Flat Pack) VF PACKAGE (TOP VIEW) XTAL1/ CLK48 EXTMEM SUSPND MODE GND 32 31 , /Resume Logic and Frame Timer SIE M 1 U X 0 30 OSC/PLL 29 31 4 26 XTAL1/ CLK48 XTAL2 MODE RESET , XTAL1/ CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source can be , XTAL1/ CLK48 XTAL2 NO. 3, 25 30 29 I O I/O DESCRIPTION 3.3-V supply voltage Crystal 1/48-MHz clock input. When MODE is low, XTAL1/ CLK48 is a 6-MHz crystal input with 50% duty cycle. An internal APLL generates


Original
PDF TUSB2036 SLLS372E SLLS372E
2000 - TUSB2140B

Abstract: TUSB2043
Text: ) XTAL1/ CLK48 EXTMEM SUSPND MODE DP0PUR XTAL2 GND 32 31 30 29 28 27 26 25 DP0 DM0 VCC , / CLK48 XTAL2 MODE RESET EXTMEM SIE Interface Logic 6 Serial EEPROM Interface 5 EEDATA/GANGED , or oscillator can be used. When MODE is high, the clock on XTAL1/ CLK48 is selected as the clock , I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/ CLK48 is a 6-MHz crystal input with 50% duty , MODE is high, XTAL1/ CLK48 acts as the input of the 48-MHz clock and the internal APLL logic is bypassed


Original
PDF TUSB2036 SLLS372B TUSB2140B TUSB2043
2002 - Transdimension

Abstract: itron SH OS pci 32 bit 5 v AD10 AD11 AD12 AD14 UHP112
Text: AD26 AD25 VDD VSS AD24 C/BEN3 IDSEL A20MN AD2 AD1 AD0 VSS CLK48 VDD PMEN PRTPWR1 , 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A20MN AD2 AD1 AD0 VSS CLK48 , CLK48 VDD PMEN PRTPWR1 Output/Open Drain Bidir Bidir Bidir Power Input Power Output/Open


Original
PDF UHP112 32-bit, 100-pin Transdimension itron SH OS pci 32 bit 5 v AD10 AD11 AD12 AD14 UHP112
2002 - PID microcontroller

Abstract: 1766B "USB" peripheral
Text: txd rxdm txoen rxd USB Physical Transceiver eopn send_resume clk48 USB , Reset System Input Low clk48 48 MHz USB V1.1 1.1 Clock Reference Input ­ cpu_clk , Diagram cpu_clk clk_48 user_data_in user_data_in madd interupt U s e r I n t e r f a , 4. Connecting the USB V1.1 to an AVR-based Microcontroller O S C P L L clk48 USB V1 , interrupt signal is synchronous to the clk48 MHz. Therefore, it can be asynchronous to the cpu_clk clock


Original
PDF 1-Compliant/12 1766B 01/02/0M PID microcontroller "USB" peripheral
2002 - USB V1.1 Device

Abstract: "USB" peripheral
Text: USB Physical Transceiver eopn send_resume clk48 USB Physical Transceiver suspend , Type Active Level Comments Functional reset Reset System Input Low clk48 48 , Description Figure 2. USB V1.1 Block Diagram U s e r cpu_clk clk_48 user_data_in user_data_in , O S C P L L clk48 USB V1.1 Device send_resume 0 Interrupt Controller interrupt , clk48 MHz. Therefore, it can be asynchronous to the cpu_clk clock signal. To control asynchronization


Original
PDF Compliant/12 32-bit 1765B 01/02/0M USB V1.1 Device "USB" peripheral
Supplyframe Tracking Pixel