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VSC8073

Abstract: STM-64 STS-192
Text: + DOUT­ CLKI/16 CLK16O+ CLK16O­ CLK16I+ CLK16I­ Phase Detector PU G52279-0, Rev. 4.0 , + D1­ VEE D14+ CLK16I­ D0­ D15+ D15­ 5 VEE CLK16I+ CLK16O+ 43 19 D10­ VEE , D0 - D15± Frame Processor Q0 - Q15± DI± VSC8073 CLK16I± DOUT± E/O O/E CLKI , parallel data inputs (D0-D15±) and parallel data rate clock ( CLK16I± ) are provided with on-chip 50 , Output tDS D0± - D15± Parallel Data Inputs tDH Valid Data (1) Valid Data (2) tPE CLK16I±


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PDF 10Gb/s 16-Bit STS-192 STM-64 VSC8073 622Mb/s 10Gbs/High-Speed 80-Pin CLK16I± VSC8073
1999 - Not Available

Abstract: No abstract text available
Text: Multiplexer DOUT+ DOUT­ · · · · · · CLKI/16 CLK16O+ CLK16O­ CLK16I+ CLK16I­ Phase Detector Timing , 77 75 73 71 69 67 65 VEE NC NC PU PD VEE CLK16I+ CLK16I­ D0­ D0+ D1­ D1+ VEE D2 , Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 Pin Name VEE NC NC PU PD VEE CLK16I+ CLK16I­ D0­ D0+ D1 , ± Frame Processor CLK16I± CLKI VSC8073 DOUT± CLK16O± E/O O/E PD DI± CLKI VSC8074 CLK16O± Q0 - Q15± Frame , Interface The ECL-compatible parallel data inputs (D0-D15±) and parallel data rate clock ( CLK16I± ) are


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PDF VSC8073 622Mb/s 10Gbs/High-Speed 10Gb/s 16-Bit STS-192 STM-64 80-Pin CLK16I± VSC8073
6 to 64 demux

Abstract: G5214
Text: clock. The ECL compatible parallel data inputs (D0.X>15) and parallel data rate clocks ( CLK16I / CLK16IN , : VSC8071 Functional Block Diagram DOO D01 D1S CLK160 CLK160N CLK16I CLK16IN Figure 6 , (typ. -1,32V) CLK16I , CLK16IN DO, DON, CLKI 60, CLK160N PU, PD VCC VEE V'rr Vbb Table 8 , lDOR. lDOF tCLK16R> · CLK16I Description Serial data rise and fall time CLK160 rise and fall times Data setup to CLKI 60 Data hold from CLK160 CLK16I to CLKI60 delay CLKI


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PDF VSC8071/B072 16-Bit STS-192 STM-64 8071isal6 VSC8072 and8071/8072 G52147-0 6 to 64 demux G5214
2000 - STM-16

Abstract: VSC8169 VSC9210 FEC Encoder
Text: the VSC8169 without a heat sink under most thermal conditions. VSC8169 Block Diagram CLK16I+ CLK16I- CLK32O+ CLK32O- Divide by 2 16x5 FIFO D15+ D15- Input Register D0+ D0 , data. The VSC8169 will latch D[15:0]± on the rising edge of CLK16I+. The data must meet setup and hold , amount of delay between CLK16O and CLK16I. Once RESET is asserted and the FIFO initialized, the delay , be changed to -3.3V. AC Characteristics Figure 8: Timing Waveforms CLK16PER CLK16I+ Parallel


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PDF SC8169 488Gb/s OC-48 STM-16 14x20 VSC8169 76MHz 38MHz- 52MHz STM-16 VSC9210 FEC Encoder
1999 - 622-MHz

Abstract: No abstract text available
Text: Multiplexer DOUT+ DOUT­ · · · · · · CLKI/16 CLK16O+ CLK16O­ CLK16I+ CLK16I­ Phase Detector Timing , 77 75 73 71 69 67 65 VEE NC NC PU PD VEE CLK16I+ CLK16I­ D0­ D0+ D1­ D1+ VEE D2 , Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 Pin Name VEE NC NC PU PD VEE CLK16I+ CLK16I­ D0­ D0+ D1 , ± Frame Processor CLK16I± CLKI VSC8073 DOUT± CLK16O± E/O O/E PD DI± CLKI VSC8074 CLK16O± Q0 - Q15± Frame , Interface The ECL-compatible parallel data inputs (D0-D15±) and parallel data rate clock ( CLK16I± ) are


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PDF VSC8073 622Mb/s 10Gbs/High-Speed 10Gb/s 16-Bit STS-192 STM-64 80-Pin CLK16I± VSC8073 622-MHz
1999 - Not Available

Abstract: No abstract text available
Text: heat sink under most thermal conditions. VSC8163 Block Diagram CLK16I+ CLK16ID0+ D0Write Pointer , CLK16I phase aligned with the data. The VSC8163 will latch D[15:0]± on the rising edge of CLK16I+. The , system designer to tolerate an arbitrary amount of delay between CLK16O and CLK16I. Once RESET is , Figure 8: Timing Waveforms CLK16PER CLK16I+ Parallel data clock input tDSU tDH D(0.15)+ , Preliminary Datasheet VSC8163 Description Data Setup time to the rising edge of CLK16I+ Data hold time


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PDF VSC8163 488Gb/s OC-48 STM-16 14x20 VSC8163 76MHz 52MHz 488GHz
2001 - Not Available

Abstract: No abstract text available
Text: . VSC8163 Block Diagram CLK16I+ CLK16I- REFCLKO+ REFCLKO- 16x5 FIFO D15+ D15- Input Register , ± on the rising edge of CLK16I+. The data must meet setup and hold times with respect to CLK16I (see , system designer to tolerate an arbitrary amount of delay between CLK16O and CLK16I. Once RESET is , ELECTRICAL SPECIFICATIONS CLK16I+ Parallel Data Clock Input tTXDSU D[0.15]+ Parallel Data Inputs , edge of CLK16I+ 0.75 — — ns TDH Data hold time after the rising edge of CLK16


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PDF VSC8163 488Gb/s OC-48 STM-16 VSC8163 48832Gb/s 76MHz 52MHz 48832GHz 16-bit
1999 - STM-16

Abstract: VSC8163 low pass filter circuit 741
Text: without a heat sink under most thermal conditions. VSC8163 Block Diagram CLK16I+ CLK16I- CLK32O , will latch D[15:0]± on the rising edge of CLK16I+. The data must meet setup and hold times with , amount of delay between CLK16O and CLK16I. Once RESET is asserted and the FIFO initialized, the delay , VSC8163 AC Characteristics Figure 8: Timing Waveforms CLK16PER CLK16I+ Parallel data clock , rising edge of CLK16I+ 0.75 - - ns. TDH Data hold time after the rising edge of


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PDF VSC8163 488Gb/s OC-48 STM-16 14x20 VSC8163 76MHz 52MHz 488GHz STM-16 low pass filter circuit 741
2001 - STM-16

Abstract: VSC8169 VSC9210 FEC Encoder
Text: a heat sink under most thermal conditions. VSC8169 Block Diagram CLK16I+ CLK16I- REFCLKO , phase aligned with the data. The VSC8169 will latch D[15:0] ± on the rising edge of CLK16I+. The data , delay between CLK16O and CLK16I. Once RESET is asserted and the FIFO initialized, the delay between , VSC8169 AC Characteristics Figure 9: Parallel Input Data and Clock Timing Waveform CLK16PER CLK16I+ , rising edge of CLK16I+ 0.75 - - ns tDH Data hold time after the rising edge of


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PDF OC-48 VSC8169 OC-48 STM-16 128-Pin 14x20mm VSC8169 48832Gb/s 76MHz 38MHz-FEC) STM-16 VSC9210 FEC Encoder
2004 - Not Available

Abstract: No abstract text available
Text: stable system reference connected to CLK16R and the CMOS ASIC clock signal connected to CLK16I. Due to , connected to CLK16I , which configures PFD2 to support either a 622 MHz or 311 MHz clock input automatically , ) Low Speed Data and Clock Inputs (D0-D15, CLK16I ) Clock/16 and Data Valid Outputs (CLK16O, QV , ) Input Impedance Setup Time (Data to CLK16I ) Hold Time (Data from CLK16I ) Std. 10 GbE Frequency G , Disable Enable Disable Timing Diagram tCLK16I ts th CLK16I D0-D15, DP DATA D0-D15


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PDF VSC1233 100-pin VMDS-10093 VSC1233
Not Available

Abstract: No abstract text available
Text: the rising edge of CLK16I+. The data must meet setup and hold times with respect to CLK16I (see Table , the system designer to tolerate an arbitrary amount of delay between C LK 160 and CLK16I. Once RESET , CLK16I+ A Parallel data clock input - 4 1d s u D(0.15)+ Parallel data inputs >■— 4 , Units Conditions T dsu Data Setup time to the rising edge of CLK16I+ 0.75 — ns , CLK160+ duty cycle c l k id CLK16I+ duty cycle 30 70 % rckd Reference Clock duty


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PDF VSC8163 488Gb/s OC-48 14x20 VSC8163 76MHz 488GHz G52216-0,
1999 - PQFP 128 14x20

Abstract: No abstract text available
Text: heat sink under most thermal conditions. VSC8169 Block Diagram CLK16I+ CLK16ID0+ D0Write Pointer , generate a CLK16I phase aligned with the data. The VSC8169 will latch D[15:0]± on the rising edge of CLK16I+. , designer to tolerate an arbitrary amount of delay between CLK16O and CLK16I. Once RESET is asserted and the , Characteristics Figure 8: Timing Waveforms CLK16PER CLK16I+ Parallel data clock input tDSU tDH D(0.15)+ , VSC8169 Description Data Setup time to the rising edge of CLK16I+ Data hold time after the rising edge


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PDF VSC8169 488Gb/s OC-48 STM-16 14x20 VSC8169 76MHz 38MHz- 52MHz PQFP 128 14x20
MTC5585D

Abstract: MTC5615 C5585 APD 1300 2,5 GHz
Text: Input Return Loss Reference Clock Inputs ( CLK16I , NCLK16I) C IN(pn) 12.5 GHz 1000 , SEL2 C/8 NCLKIN CLK16O UP Phase/ Frequency Detector NCLK16O CLK16I DN NCLK16I Figure 2: Block Diagram tCLK16O ts th CLK16O D0-D15 D0-D15 D0-D15 CLK16I DATA , MTC1207S, this pin becomes 'TUNE2') 40 ND0 CLK16I 16 20 8 12 4 1 128 60 124 , CLK16I , NCLK16I 106 104 48 50 SEL1 60 SEL2 D0, ND0 D1, ND1 D2, ND2 D3, ND3 D4, ND4


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PDF MTC1215 16-Bit OC-192 STM-64 MTC1215 OC-192, STM-64, combi93 10-04-00L MTC5585D MTC5615 C5585 APD 1300 2,5 GHz
1999 - 8438M

Abstract: No abstract text available
Text: heat sink under most thermal conditions. VSC8169 Block Diagram CLK16I+ CLK16I­ D0+ D0­ Write , of CLK16I+. The data must meet setup and hold times with respect to CLK16I (see Table 2). A FIFO , Characteristics Figure 8: Timing Waveforms CLK16PER CLK16I+ Parallel data clock input tDSU tDH D(0.15)+ , Differential Swing Description Data Setup time to the rising edge of CLK16I+ Data hold time after the rising edge of CLK16+ DO± rise and fall time CLK16O± rise and fall times CLK16O± duty cycle CLK16I± duty


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PDF VSC8169 488Gb/s OC-48 STM-16 14x20 VSC8169 76MHz 38MHz- 52MHz 8438M
1999 - STM-64

Abstract: STS-192
Text: compatible parallel data inputs (D0.D15) and parallel data rate clocks ( CLK16I / CLK16IN ) are provided with , CLK16I DETECTOR CLK16IN PU Page 2 PD © VITESSE SEMICONDUCTOR CORPORATION 741 Calle , CLKI inputs. (Typically grounded) VC CLK16I , CLK16IN INPUT- DIFFERENTIAL ECL Parallel data rate , tPE CLK16I to CLK16O delay 50 pS Single ended CLK16I , PU/PD = zero on-chip phase error CLKI period 100 pS See figure 4. nS See figure 4. tCLKI tCLK16I 1.6 CLK16I


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PDF 16-Bit STS-192 STM-64 VSC8071/VSC8072 10Gb/s 622Mb/s VSC8071 VSC8072
2001 - uA 741

Abstract: STM-16 VSC8163
Text: the VSC8163 without a heat sink under most thermal conditions. VSC8163 Block Diagram CLK16I+ CLK16I- REFCLKO+ REFCLKO- 16x5 FIFO D15+ D15- Input Register D0+ D0- Write Pointer , CLK16I+. The data must meet setup and hold times with respect to CLK16I (see Table 2). In addition to , tolerate an arbitrary amount of delay between CLK16O and CLK16I. Once RESET is asserted and the FIFO , Figure 9: Parallel Input Data and Clock Timing Waveforms CLK16I+ Parallel Data Clock Input tTXDSU D


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PDF OC-48 VSC8163 488Gb/s STM-16 14x20mm VSC8163 48832Gb/s 76MHz 52MHz uA 741 STM-16
Not Available

Abstract: No abstract text available
Text: Figure 1). The Upstream Device should then generate a CLK16I phase aligned with the data. The VSC8163 will latch D[15:0]± on the rising edge of CLK16I+. The data must meet setup and hold times with respect , permits the system designer to tolerate an arbitrary amount of delay between CLK160 and CLK16I. Once RESET , Setup time to the rising edge of CLK16I+ Data hold time after the rising edge of CLK16+ Min 0.75 2.0 , CLK160± rise and fall lCLKR' lCLKF times clkod CLK160± duty cycle c l k id CLK16I± duty cycle rckd


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PDF VSC8163 488Gb/s OC-48 14x20 VSC8163 76MHz 488GHz G52216-0,
Not Available

Abstract: No abstract text available
Text: inputs (D0.D15) and parallel data rate clocks ( CLK16I / CLK16IN ) are provided with on chip 50 ohm , D01 D15 CLK160 CLK160N CLK16I CLK16IN Figure 6: VSC8072 Functional Block Diagram Page , Description D00:15 CLKI vc CLK16I , CLK16IN DO, DON, CLK160, CLK160N PU, PD V CC v EE VTT , on-chip phase error 100 pS - 1 .6 nS •CLKI * CLK16I CLKI period CLKI 61 period


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PDF VSC8071/B072 16-Bit STS-192 STM-64 VSC8071 VSC8072 000240L. G52147-0
G5214

Abstract: No abstract text available
Text: ( CLK16I / CLK16IN ) are provided with on chip 50 ohm terminations to V-j-j-. The bit rate clock (CLKI) input , fall time Data setup to CLK160 Data hold from CLK160 tpE CLK16I to CLK 160 delay 50 pS CLKI period CLK16I period Threshold Margin Phase Margin Phase Detector Gain 100 1.6 pS nS , Timing Waveforms CLK160 Low speed clock output D(0.15) Parallel data inputs CLK16I , Description D00:15 CLKI vc CLKI 61, CLK16IN DO, DON, CLKI 60, CLK160N PU, PD Vcc V EE Vrl'rl


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PDF VSC8071/VSC8072 STS-192 STM-64 622Mb/s VSC8071 VSC8072 G52147-0, G5214
1996 - YL 69 moisture

Abstract: Z624 PIP VIDEO ENCODER CLK16 z336 1/4N7 y838 Z335 SAA4997H SAA4996H QFP100
Text: TEST 33 CLK_16 98, 75, 35 3 CLK_16i SNERT INTERFACE 58 1996 Oct 28 SEL , _32 CLK_16 64 MacpOn CLK_16I 2 LD = 1 FilmOn 2 InvO/E PC1 Mpip Control 3 , CLK_16I CLK_16I CLK_16I LD = 2 CLK 11 Mpip FilmOn HlpM0,1 TDI TMS TCK , LOGIC line2_every_field TEST AND BST 22Valid 2 CLAMP 6 H_RE / WE CLK_32I CLK_16I , -2 7 36 WE_MA GENERATION CLK_16I VA_AI DELAY (1/2 LINE) FIELD DETECTION, FIELD


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PDF SAA4996H YL 69 moisture Z624 PIP VIDEO ENCODER CLK16 z336 1/4N7 y838 Z335 SAA4997H SAA4996H QFP100
1996 - YL 69 moisture

Abstract: Z624 colour television block diagram z621 Z335 colour tv circuit diagram z316 16b3 Z312 z336
Text: TEST 33 CLK_16 98, 75, 35 3 CLK_16i SNERT INTERFACE 58 1996 Oct 28 SEL , _32 CLK_16 64 MacpOn CLK_16I 2 LD = 1 FilmOn 2 InvO/E PC1 Mpip Control 3 , CLK_16I CLK_16I CLK_16I LD = 2 CLK 11 Mpip FilmOn HlpM0,1 TDI TMS TCK , LOGIC line2_every_field TEST AND BST 22Valid 2 CLAMP 6 H_RE / WE CLK_32I CLK_16I , -2 7 36 WE_MA GENERATION CLK_16I VA_AI DELAY (1/2 LINE) FIELD DETECTION, FIELD


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PDF SAA4996H SCA52 537021/1200/01/pp60 YL 69 moisture Z624 colour television block diagram z621 Z335 colour tv circuit diagram z316 16b3 Z312 z336
6 to 64 demux

Abstract: 741 PIN DIAGRAM
Text: ± .D15±) and parallel data rate clocks ( CLK16I± ) are pro vided with on chip 50Q terminations to V-j-j


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PDF VSC8073/VSC8074 STS-192 STM-64 622Mb/s VSC8073 VSC8074 80-pin 10GHz G52168-0, 6 to 64 demux 741 PIN DIAGRAM
1 into 16 demultiplexer circuit diagram using 1 i

Abstract: Q0-Q15 STM-64 STS-192 VSC8073
Text: Diagram PU PD D0 - D15± Frame Processor Q0 - Q15± DI± VSC8073 CLK16I± DOUT± E/O


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PDF 10Gb/s 16-Bit STS-192 STM-64 VSC8074 622Mb/s 80-Pin VSC8073 1 into 16 demultiplexer circuit diagram using 1 i Q0-Q15 VSC8073
1999 - 622-MHz

Abstract: 10046
Text: Block Diagram PU D0 - D15± Frame Processor CLK16I± CLKI VSC8073 DOUT± CLK16O± E/O O/E PD DI± CLKI


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PDF VSC8074 10Gb/s 622Mb/s 16-Bit STS-192 STM-64 80-Pin CLK16I± 622-MHz 10046
V3836

Abstract: Q1104 SAA4997H SAA4996H QFP100 16B1 V30B TT 2222 Horizontal Output voltage motion DETECTOR CIRCUIT DIAGRAM colour television block diagram
Text: IVericN 91, 92, _4r 89, 90 CONTROL 99 100 94 95 93 79 80 28 76 77 78 control CLK_16i -«-CLK


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PDF SAA4996H 0110S20 V3836 Q1104 SAA4997H SAA4996H QFP100 16B1 V30B TT 2222 Horizontal Output voltage motion DETECTOR CIRCUIT DIAGRAM colour television block diagram
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