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ECLK1-2 Siemens Allied Electronics & Automation 10 $8.17 $7.88
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Not Available

Abstract: No abstract text available
Text: Jitter Performance - Period Jitter: 25 psec (Typ.) at CLK1-2 The AK8146A is a low power multi clock , IDD Conditions MIN Pin: CLK1-2 ,REFO TYP MAX V 0.8VDD IOH=-4mA Pin: CLK1-2 , Symbol Conditions MIN (1) Crystal Clock Frequency Pin: CLK1-2 Output Clock Duty Cycle , CLK1-2 Output Clock Fall Time Unit 24.0 Pin: XI 500mVp-p or more Duty:30%-70% @0.5 , TYP 50 60 % (2) 1.5 4.0 ns (2) 1.5 4.0 ns Pin: CLK1-2 ,REFO Pin


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PDF 000MHz 48MHz AK8146A 24MHz August-08 MS0992-E-00
2002 - Z0100

Abstract: Z0122 CRC-16 and verilog CLK48
Text: should be sampled by the application on the rising edge of Clk12. This signal also qualifies HCIM_RdWr , internal to the Host Controller. APP_SAdr should meet setup time to Clk12. HCI Register Write Data Valid , signal asserted on the rising edge of Clk12. HCI Register Write Data: Data to be written into the Host , pointed to by the HCF_WrPtr[5:0] pins when HCF_WriteN is sampled asserted on the rising edge of Clk12. , PORT INTERFACE Clk12 Clk48 Test_PLLCLK Figure 2: Logic Symbol for USB 1.1 Host Controller 8


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PDF Z0122 Z0100 Z0100 Z0122 CRC-16 and verilog CLK48
2009 - CLK12

Abstract: No abstract text available
Text: Period Jitter: 25 psec (Typ.) at CLK1-2 Low Current Consumption: 5.0mA (Typ.) at 3.3V Supply Voltage: 3.0 , Consumption Symbol VOH VOL IDD -20 to +85, 24MHz Crystal, unless otherwise noted Conditions Pin: CLK1-2 ,REFO IOH=-4mA Pin: CLK1-2 ,REFO IOL=+4mA No load Ta=25 5.0 MIN 0.8VDD 0.2VDD TYP MAX Unit V V mA AC , Conditions Pin: XI 500mVp-p or more Duty:30%-70% @0.5*(Input Swing) CLK1-2 Pin: CLK1-2 Pin: REFO MIN , trise tfall Pin: CLK1-2 ,REFO Pin: CLK1-2 ,REFO Pin: CLK1-2 (2) (1) AT cut, Fundamental mode


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PDF AK8146A 000MHz 48MHz AK8146A 24MHz August-08 MS0992-E-00 CLK12
2011 - AK8128MV

Abstract: No abstract text available
Text: CLK2 □ □ □ å‡ºåŠ›è² è· CLK1-2 長 : : : 3.0V – 3.6V 8 mA , /off : 15pF 低ジッタ出力 Period Jitter CLK1-2 Long term Jitter CLK1-2 ï , Table 1: CLK1-2 Clock Output Frequency Selection Pin Clock Input Frequency (MHz) Clock Output , CLK1 GND Figure 1: Typical Connection Diagram C1-2 : 0.1μF 程度 SW0 : CLK1-2 の周波æ , €‚ SW1 : CLK1-2 の周波数設定テーブルに応じて設定して下さいã


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PDF AK8128MV] AK8128MV AK8128MVã MS1291-J-00 AK8128MV
1994 - PC MOTHERBOARD CIRCUIT diagram

Abstract: PC MOTHERBOARD CIRCUIT diagram download free free circuit diagram of motherboard CDC9841 CLK12 ALL MOTHERBOARD CIRCUIT DIAGRAM
Text: 11 18 12 17 13 16 14 15 REF0 REF1 VCC CLK12 CLK24 GND BCLK2 BCLK3 VCC , (CLK24), a 12-MHz clock ( CLK12 ), and two buffered copies of the 14.318-MHz input reference (REF0, REF1). , CLK12 X X 14.31818 MHz Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H L L 14.31818 MHz , 27 24 ÷2 REF1 CLK24 ÷2 ÷2 25 6 CLK12 PCLK0 24-MHZ PLL 7 9 10 , BCLKn CLK24, CLK12 12 REF1 Low-level output current p L l l ­4 REF0 IOL 8 PCLKn


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PDF CDC9841 SCAS458D 24-MHz 12-MHz 318-MHz 31818-MHz PC MOTHERBOARD CIRCUIT diagram PC MOTHERBOARD CIRCUIT diagram download free free circuit diagram of motherboard CDC9841 CLK12 ALL MOTHERBOARD CIRCUIT DIAGRAM
2011 - AK8128ME

Abstract: No abstract text available
Text: CLK2 □ □ □ å‡ºåŠ›è² è· CLK1-2 長 : : : 3.0V – 3.6V 8 mA , /off : 15pF 低ジッタ出力 Period Jitter CLK1-2 Long term Jitter CLK1-2 ï , Table 1: CLK1-2 Clock Output Frequency Selection Pin Clock Input Frequency (MHz) Clock Output , CLK1 GND Figure 1: Typical Connection Diagram C1-2 : 0.1μF 程度 SW0 : CLK1-2 の周波æ , €‚ SW1 : CLK1-2 の周波数設定テーブルに応じて設定して下さいã


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PDF AK8128ME] AK8128ME AK8128MEã MS1293-J-00 AK8128ME
2011 - AK8128ME

Abstract: No abstract text available
Text: Period Jitter (1): 20 psec (Typ.) at CLK1-2 - Long Term Jitter (1000 cycle, 1): 40 psec (Typ.) at CLK1-2 , of 0.1F for power supply line should be installed close to each VDD pin. Symbol Ta VDD Cpl Pin: CLK1-2 , : S0 Pin: S0 Pin: S0 Pin: CLKIN Pin: S1 Pin: S0 Pin: TEST VIL=GND Pin: CLK1-2 IOH=-4mA Pin: CLK1-2 IOL , : CLK1-2 trise tfall (2) (1) MIN TYP 2.8224 3.072 11.2896 12.288 27.000 MAX Unit MHz MHz MHz , ). The selectable frequency is shown in Table1. Table 1: CLK1-2 Clock output Frequency Selection


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PDF AK8128ME 000MHz 40625MHz 2896MHz/off 10-pin AK8128ME MS1293-E-01 May-11
1994 - PC MOTHERBOARD CIRCUIT diagram

Abstract: CDC9841 CLK12
Text: 11 18 12 17 13 16 14 15 REF0 REF1 VCC CLK12 CLK24 GND BCLK2 BCLK3 VCC , (CLK24), a 12-MHz clock ( CLK12 ), and two buffered copies of the 14.318-MHz input reference (REF0, REF1). , CLK12 X X 14.31818 MHz Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H L L 14.31818 MHz , 27 24 ÷2 REF1 CLK24 ÷2 ÷2 25 6 CLK12 PCLK0 24-MHZ PLL 7 9 10 , , CLK12 12 REF1 Low-level output current ­4 REF0 IOL 8 PCLKn 6 BCLKn 4


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PDF CDC9841 SCAS458D 24-MHz 12-MHz 318-MHz 31818-MHz PC MOTHERBOARD CIRCUIT diagram CDC9841 CLK12
1994 - PC MOTHERBOARD CIRCUIT diagram

Abstract: CDC9841 ALL MOTHERBOARD CIRCUIT DIAGRAM CLK12
Text: 11 18 12 17 13 16 14 15 REF0 REF1 VCC CLK12 CLK24 GND BCLK2 BCLK3 VCC , (CLK24), a 12-MHz clock ( CLK12 ), and two buffered copies of the 14.318-MHz input reference (REF0, REF1). , CLK12 X X 14.31818 MHz Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H L L 14.31818 MHz , 27 24 ÷2 REF1 CLK24 ÷2 ÷2 25 6 CLK12 PCLK0 24-MHZ PLL 7 9 10 , , CLK12 12 REF1 Low-level output current ­4 REF0 IOL 8 PCLKn 6 BCLKn 4


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PDF CDC9841 SCAS458D 24-MHz 12-MHz 318-MHz 31818-MHz PC MOTHERBOARD CIRCUIT diagram CDC9841 ALL MOTHERBOARD CIRCUIT DIAGRAM CLK12
Not Available

Abstract: No abstract text available
Text: .) at CLK1-2 - Long Term Jitter (1000 cycle, 1σ): 40 psec (Typ.) at CLK1-2 Low Current Consumption , VDD Cpl Min 3.3 Max Unit 85 -20 3.0 Pin: CLK1-2 Typ °C 3.6 V 15 , Current consumption IDD Pin: TEST VIL=GND Pin: CLK1-2 IOH=-4mA Pin: CLK1-2 IOL=+4mA Ta=25 , No , Term jitter (3) (2) Output Clock Duty Cycle 45 Pin: CLK1-2 50 55 % Output clock , (Pin7). The selectable frequency is shown in Table1. Table 1: CLK1-2 Clock output Frequency


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PDF AK8128ME AK8128ME 10-pin 000MHz MS1293-E-00 April-11
2011 - AK8128mv

Abstract: No abstract text available
Text: Period Jitter (1): 20 psec (Typ.) at CLK1-2 - Long Term Jitter (1000 cycle, 1): 40 psec (Typ.) at CLK1-2 , of 0.1F for power supply line should be installed close to each VDD pin. Symbol Ta VDD Cpl Pin: CLK1-2 , , S1 Pin: S0 Pin: S0 Pin: S0 Pin: CLKIN Pin: S1 Pin: S0 Pin: TEST VIL=GND Pin: CLK1-2 IOH=-4mA Pin: CLK1-2 IOL=+4mA Ta=25, No load S[0:1] = All Setting -1 -20 -20 -1 0.8VDD 0.2VDD 8.0 0.7VDD 0.45VDD , : CLK1(2) S[0:1] = "HL", "HH" 1000cycles Pin: CLK1-2 trise tfall (2) (1) MIN TYP 2.8224 3.072


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PDF AK8128MV 000MHz 40625MHz 2896MHz/off 10-pin AK8128MV AK81r MS1291-E-00 April-11
Not Available

Abstract: No abstract text available
Text: .) at CLK1-2 - Long Term Jitter (1000 cycle, 1σ): 40 psec (Typ.) at CLK1-2 Low Current Consumption , VDD Cpl Min 3.3 Max Unit 85 -40 3.0 Pin: CLK1-2 Typ °C 3.6 V 15 , Current consumption IDD Pin: TEST VIL=GND Pin: CLK1-2 IOH=-4mA Pin: CLK1-2 IOL=+4mA Ta=25 , No , Term jitter (3) (2) Output Clock Duty Cycle 45 Pin: CLK1-2 50 55 % Output clock , (Pin7). The selectable frequency is shown in Table1. Table 1: CLK1-2 Clock output Frequency


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PDF AK8128MV AK8128MV 10-pin 000MHz MS1291-E-00 April-11
2011 - AK8128MV

Abstract: MS1291-E-01
Text: Period Jitter (1): 20 psec (Typ.) at CLK1-2 - Long Term Jitter (1000 cycle, 1): 40 psec (Typ.) at CLK1-2 , of 0.1F for power supply line should be installed close to each VDD pin. Symbol Ta VDD Cpl Pin: CLK1-2 , : S0 Pin: S0 Pin: S0 Pin: CLKIN Pin: S1 Pin: S0 Pin: TEST VIL=GND Pin: CLK1-2 IOH=-4mA Pin: CLK1-2 IOL , : CLK1-2 trise tfall (2) (1) MIN TYP 2.8224 3.072 11.2896 12.288 27.000 MAX Unit MHz MHz MHz , ). The selectable frequency is shown in Table1. Table 1: CLK1-2 Clock output Frequency Selection


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PDF AK8128MV 000MHz 40625MHz 2896MHz/off 10-pin AK8128MV MS1291-E-01 May-11
2011 - AK8128

Abstract: No abstract text available
Text: Period Jitter (1): 20 psec (Typ.) at CLK1-2 - Long Term Jitter (1000 cycle, 1): 40 psec (Typ.) at CLK1-2 , of 0.1F for power supply line should be installed close to each VDD pin. Symbol Ta VDD Cpl Pin: CLK1-2 , , S1 Pin: S0 Pin: S0 Pin: S0 Pin: CLKIN Pin: S1 Pin: S0 Pin: TEST VIL=GND Pin: CLK1-2 IOH=-4mA Pin: CLK1-2 IOL=+4mA Ta=25, No load S[0:1] = All Setting -1 -20 -20 -1 0.8VDD 0.2VDD 8.0 0.7VDD 0.45VDD , : CLK1(2) S[0:1] = "HL", "HH" 1000cycles Pin: CLK1-2 trise tfall (2) (1) MIN TYP 2.8224 3.072


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PDF AK8128ME 000MHz 40625MHz 2896MHz/off 10-pin AK8128ME AK81r MS1293-E-00 April-11 AK8128
CDC9841

Abstract: No abstract text available
Text: ) * * * * * * * Vc c [ X1[ X2[ GND[ 1 u 2 3 28 27 ] REFO ] REF1 4 26 ] V CC 25 ] CLK12 OE[ 5 , CLK24 Hi-Z 24 MHz 24 MHz 24 MHz T C LK /4 CLK12 Hi-Z 12M H z 1 2 MHz 12M H z T C LK /8 tT C L K is a , High-level output current PCLKn BCLKn CLK24, CLK12 REF0 REF1 Iq l Low-level output current PCLKn BCLKn CLK24, CLK12 T /\ NOTE 3: O perating free-air temperature Unused inputs m ust be held high or low to prevent , , CLK12 REFO REF1 PCLKn BCLKn CLK24, CLK12 2.5 2.5 2.5 2.5 2.5 l0 H = - 1 2 m A IO H = - 8 m A v OH VCC


OCR Scan
PDF CDC9841
1994 - circuit diagram of motherboard

Abstract: free circuit diagram of motherboard CDC9841 PC MOTHERBOARD CIRCUIT diagram free CDC9841DW CDC9841DWR CLK12
Text: 11 18 12 17 13 16 14 15 REF0 REF1 VCC CLK12 CLK24 GND BCLK2 BCLK3 VCC , (CLK24), a 12-MHz clock ( CLK12 ), and two buffered copies of the 14.318-MHz input reference (REF0, REF1). , CLK12 X X 14.31818 MHz Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H L L 14.31818 MHz , 27 24 ÷2 REF1 CLK24 ÷2 ÷2 25 6 CLK12 PCLK0 24-MHZ PLL 7 9 10 , , CLK12 12 REF1 Low-level output current ­4 REF0 IOL 8 PCLKn 6 BCLKn 4


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PDF CDC9841 SCAS458D 24-MHz 12-MHz 318-MHz 31818-MHz circuit diagram of motherboard free circuit diagram of motherboard CDC9841 PC MOTHERBOARD CIRCUIT diagram free CDC9841DW CDC9841DWR CLK12
1994 - CDC9841

Abstract: No abstract text available
Text: 20 19 18 17 16 15 REF0 REF1 VCC CLK12 CLK24 GND BCLK2 BCLK3 VCC BCLK4 BCLK5 GND BCLK1 BCLK0 , fixed-frequency outputs provide a 24-MHz clock (CLK24), a 12-MHz clock ( CLK12 ), and two buffered copies of the , CLK24 Hi-Z 24 MHz 24 MHz 24 MHz TCLK /4 CLK12 Hi-Z 12 MHz 12 MHz 12 MHz TCLK /8 H H H TCLK /2 TCLK , 2 27 REF1 24 ÷2 ÷2 ÷2 25 CLK24 CLK12 6 24-MHZ PLL 7 PCLK0 PCLK1 9 , High-level output current PCLKn BCLKn CLK24, CLK12 REF0 REF1 IOL Low-level output current PCLKn BCLKn CLK24


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PDF CDC9841 SCAS458D 24-MHz 12-MHz 318-MHz 31818-MHz
1998 - CLK12

Abstract: ICS9158-03 ICS9158-03CW24 fs216
Text: input.) VDD=5V±10% or 3.3V±10%, TEMP=0-70°C FS2 FS1 FS0 CLK2A (MHz) CLK12 (A-C) (MHZ , OE CLK2A CLK12 (A-C) CLK12 (A-D) 40MHz (Pin 6) 24MHz (Pin 7) REF (Pin 18) 1 , ANALOG GROUND 10 OE 11 CLK12B OUT 12 GND PW R Digital GROUND 13 CLK1C , R 17 CLK12A OUT CLK12A clock output 18 REF OUT 14.31818 M Hz clock output Digital GROUND IN IN OUTPUT ENABLE. Tristates all outputs when low. CLK12B clock output CPU


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PDF ICS9158-03 ICS9158-03 250ps. 250ps ICS9158-03CW24 300mil CLK12 ICS9158-03CW24 fs216
2006 - Not Available

Abstract: No abstract text available
Text: Symbol VM VCC VIN fchop fCLK fPWM 1ch, 2ch, 3ch, 4ch, 5ch, 6ch CLK12 , CLK34, CLK56 PWM5, PWM6 Conditions , on-resistance ID = -400mA VIN = 0 V (ST, CLK12 , CLK34) VIN = 5 V (ST, CLK12 , CLK34) ST, CLK12 , CLK34 ST, CLK12 , temperature, Ta - °C 20 40 60 80 100 ILV00179 No.7944-4/24 LV8041FN PGND1 VREF7 CLK12 , VM56 OUT5B SEN5 OUT5A CLK12 51 MO12 CPH1 CPH2 CPL2 LIM7 VGH IN71 IN72 , SEN3 STB OUT1A OUT3B CLK12 OUT2A OUT4B OUT2B SEN1 TSD LVS TSD LVS VGH 5 Bridge


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PDF ENN7944 LV8041FN LV8041FN
1998 - Not Available

Abstract: No abstract text available
Text: 20 21 22 23 24 PIN NAM E CLK1A X2 X1 VDD GND 40 M Hz 24 M Hz CLK1B AGND OE CLK12B GND CLK1C CLK1D FS2 AVDD CLK12A REF GND VDD CLK12C CLK2A FS1 FS0 TYPE OUT OUT IN PW R PW R OUT OUT OUT PW R IN OUT PW R OUT , 32 32 50 50 66.67 60 CLK12 (A-C) (MHZ) 16 32 16 32 25 50 33.33 60 CLK1(A-D) (MHz) 16 16 16 16 25 25 33.33 30 Peripheral Clocks OE 1 0 CLK2A Runs Tristate CLK12 (A-C) Runs Tristate CLK12 (A-D) Runs , output CLK1B clock output ANALOG GROUND OUTPUT ENABLE. Tristates all outputs when low. CLK12B clock


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PDF ICS9158-03 ICS9158-03 250ps. 250ps ICS9158-03CW24 300mil
2009 - Not Available

Abstract: No abstract text available
Text: ps VIN at over 0 to VDD V GVCXO VIN range at 1.5V±1.0V CLK1-2 REFOUT at 27.000MHz 1000 cycle delay Pin: CLK1-2 (1) (1) (2) ±100 130 120 150 45 40 50 50 1.5 2.5 1.8 2.5 5 55 60 Long term Jitter r , Time tfall Pin: REFOUT Pin: CLK1-2 (1)()() (1) Measured with load capacitance of 15pF (2


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PDF AK8131C 27MHz 000MHz 100ppm 16-pin AK8131C
2004 - 4-Phase Stepping Motor Driver

Abstract: mO34 vgh vgl CLK12 ENN7944 sanyo motor 3 phase LV8041FN MO56 basic single phase motor reverse forward electric ILV00179
Text: CLK12 , CLK34, CLK56 PWM frequency fPWM 50 to 200 PWM5, PWM6 V KHz Up to 64 KHz , 5 V (ST, CLK12 , CLK34) Logic high-level input voltage VINH ST, CLK12 , CLK34 Logic low-level input voltage VINL A 1.2 V A 0 V (ST, CLK12 , CLK34) IINH 50 0.9 1.0 0.6 ST, CLK12 , CLK34 Logic pin input current 50 70 3.5 A V 1.5 V 0.2 , VREF7 LIM7 FC7 VGH CPH2 CPH1 VGL CPL2 52 Pin Assignment CLK12 LV8041FN


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PDF ENN7944 LV8041FN LV8041FN 4-Phase Stepping Motor Driver mO34 vgh vgl CLK12 ENN7944 sanyo motor 3 phase MO56 basic single phase motor reverse forward electric ILV00179
2007 - CLK12

Abstract: LV8042LG LV-S61 stepping motor 35 st-25
Text: 50 to 200 to 64 Clock frequency fCLK fPWM kHz to 100 kHz CLK12 , CLK34 PWM , , CLK12 ) IINH1 VIN=3.3V (ST, CLK12 ) 20 Logic input "H" level voltage VINH1 ST, CLK12 VINL1 ST, CLK12 µA 2.5 Logic input "L" level voltage 0.7 1.0 IOleak1 0.6 0.9 , STP 2ch OUTB Output pin 7 SEN2 68 PGND12 STP 1ch/2ch Power GND 67 CLK12 STP , ) 1 67 68 16 14 12 10 8 6 4 2 (NC) OUT4A OUT3B OUT3A OUT2B OUT2A OUT1B OUT1A CLK12 PGND12


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PDF ENA0004A LV8042LG LV8042LG A0004-29/29 CLK12 LV-S61 stepping motor 35 st-25
2007 - R20K

Abstract: No abstract text available
Text: frequency PWM frequency Symbol VM VCC VIN fchop fCLK fPWM 1ch, 2ch, 3ch, 4ch CLK12 , CLK34 PWM3, PWM4, PWM5 , , CLK12 ) VIN=3.3V (ST, CLK12 ) ST, CLK12 ST, CLK12 20 2.5 1.0 33 0.6 0.9 IO=400mA, upper IO=400mA, lower , OUT2B SEN2 PGND12 CLK12 MO SCLK DATA STP 1ch/2ch Motor power connection pin STP 1ch OUTA Output pin STP , ) OUT4A OUT3B OUT3A OUT2B OUT2A OUT1B OUT1A CLK12 PGND12 65 IN72 63 (NC) 61 (NC) 66 MO 64 IN71 62 VREF 60 , CLK12 OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A (NC) 66 MO 64 IN71 65 IN72 63 (NC) 3 19 20 (NC


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PDF ENA0004 LV8042LG LV8042LG A0004-29/29 R20K
1998 - CLK12

Abstract: ICS9158 ICS9158-07 ICS9158-07M rom 24pin Motorola 143X1
Text: CLK2 (Mhz) CLK1(0:3) CLK12 (0:2) (Mhz) (MHz) 1 0 0 29/13 X1 31.9 16 31.9 1 , reference frequency. OE equals Low, tristates CLK2, CLK12 (0:2), CLK1(0:3), the REF, 24 MHz and 48 MHz , /combination I/O clock output. 9 AGND PWR 10 OE 11, 17, 21, 22 CLK12 IN OUT IN


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PDF ICS9158-07 ICS9158-07 250ps. 24-Pin ICS9158-07M CLK12 ICS9158 ICS9158-07M rom 24pin Motorola 143X1
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