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CLK1000S-240-B Harvard Engineering PLC Schukat electronic - €12.36 €7.82
CLK1000S-240-C Harvard Engineering PLC Schukat electronic - €12.36 €7.82
CLK1000S-240-C HARVARD ENGINEERING PLC New Advantage Corporation 37 $24.12 $17.82

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2003 - crc verilog code 16 bit

Abstract: 00ff0000 XC2V1000-FG256 hypertransport CLK-100 XC2V1000FG256-4 XC2V3000 XC2V1000 XAPP639 XC2V1000FG256-6
Text: a 200 MHz core clock. The link layer divides the LDT_RX_CLKI clock by two to generate clock CLK100 for the CRC checker circuitry. The transmit CRC circuit uses CLK100 and it is multiplied by two for , The phase adjusted version of receive clock is called LDT_CLK200. Receive CLK100 As the internal data path is 32-bits wide, it can be processed at half the speed of LDT_RX_CLKI. CLK100 is the name of , FIFO input as well as the NOP latch and the othercommands latch. Transmit Clocks Transmit CLK100 A


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PDF XAPP639 32-bit XAPP639 XC2V1000 crc verilog code 16 bit 00ff0000 XC2V1000-FG256 hypertransport CLK-100 XC2V1000FG256-4 XC2V3000 XC2V1000FG256-6
hf electret microphone siemens

Abstract: philips dect BML STL DECT G.721
Text: CLK100 [ X T^ENABLE [ T T_PW R_RMP [ X T_DATA [ X T.GMSK F T VCO_BND.SW [ X SYNTH_LOCK [ X S_ENABLE QF , C/3 c/3 CLK100 P ~ T .ENABLE [ ] T T_PWR_RMP [ H I T_DATA [ X T_GMSK [ j T VCO_BND_SW [ T , external ADPCM codec ANT_SW1 ANT_SW0 CLK100 T_ENABLE T_PWR_RMP T_DATA T_GMSK VCO_BND_SW SYNTH_LOCK


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PDF PCD5091 80C51 MG0797 MBH94S MGD795 PCX509x. hf electret microphone siemens philips dect BML STL DECT G.721
2003 - XC2V1000FG256-4

Abstract: XAPP639 XC2V1000 XC2V3000 flood v10 crc verilog code 16 bit XC2V1000-FG256
Text: a 200 MHz core clock. The link layer divides the LDT_RX_CLKI clock by two to generate clock CLK100 for the CRC checker circuitry. The transmit CRC circuit uses CLK100 and it is multiplied by two for , The phase adjusted version of receive clock is called LDT_CLK200. Receive CLK100 As the internal data path is 32-bits wide, it can be processed at half the speed of LDT_RX_CLKI. CLK100 is the name of , FIFO input as well as the NOP latch and the othercommands latch. Transmit Clocks Transmit CLK100 A


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PDF XAPP639 32-bit XAPP639 XC2V1000 XC2V1000FG256-4 XC2V3000 flood v10 crc verilog code 16 bit XC2V1000-FG256
crystal oscillator 13.824 mhz

Abstract: CLK100 CLK-100 PROGRAMMABLE SYNTHESIZER 8051 microcontroller block diagram MLA927 PCD5041 PCD5040 PCD5032 QFP64
Text: initiate wait states in the microcontroller INT 24 interrupt output; active LOW CLK100 25 , VSS CLK100 38 INT 24 14 RDY 23 REF_CLK WR 22 39 RD 21 13 RESERVED 20


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PDF PCD5040; PCD5041 80C51-type 68000-type PCD5040/PCD5041 CLK100 MLA926 crystal oscillator 13.824 mhz CLK100 CLK-100 PROGRAMMABLE SYNTHESIZER 8051 microcontroller block diagram MLA927 PCD5041 PCD5040 PCD5032 QFP64
TSB11C01

Abstract: No abstract text available
Text: CC 32 j CLK100 31 ] ENCLK100 30 ] DGND 29 ] C/LKON description The TSB11C01 provides the analog , TPB2 TPB2 TPA3 TRÄ3 TPB3 TPB3 XI XO PDOUT VCOIN CLK100 ENCLK100 V Te xa s In s t r u m e n t s , . I/O DESCRIPTION AGND AVCC CLK100 C/LKON CPS CTL[0:1] D[0:1] DGND DVCC ENCLK100 ISO LPS LREQ PDOUT , Digital circuit supply voltage Disable crystal oscillator and PLL, enable CLK100 input Physical (phy) link , ( CLK100 ): When this terminal is asserted high (enabled), an external 98.304-MHz oscillator can drive the


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PDF TSB11C01
2000 - handsfree chip IC

Abstract: DIGITAL RADIO ECHO CANCELLER CIRCUIT DIAGRAM ad 190 SC14425 TQFP 100 PACKAGE DECT/DSP GROUP DECT Transceiver sc144 VJG100A TQFP-100
Text: CS1 TONE READY CS2 AD19 CLK100 P10_INT INTn0 SCK INTn1 SEN INTn2 SDI INTn3 SDO INTn4 STR0 , ICU SBI CR16B VSS1,2,3 VDD1,2,3 . CLK100 ACSN RCSN WRN RDN SCLK CS0,1,2


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PDF SC14425 152MHz, 576MHz 288MHz SC14425 handsfree chip IC DIGITAL RADIO ECHO CANCELLER CIRCUIT DIAGRAM ad 190 TQFP 100 PACKAGE DECT/DSP GROUP DECT Transceiver sc144 VJG100A TQFP-100
1997 - philips dect

Abstract: LQFP100 footprint footprint jedec QFP100 SIEMENS AVR GENERATOR LQFP100 PCD5032 80C51 PCD5091H PCD5091HZ QFP100
Text: 1997 Jul 21 4 CLK100 XTAL1 XTAL2 GP_CLK7 DPLL_DATA T_GMSK R_SLICED SLICE_CTR , TST1 CLK100 3 78 VSS4 T_ENABLE 4 77 VDD5V_2 T_PWR_RMP 5 76 A16 , handbook, full pagewidth 99 ANT_SW1 100 ANT_SW0 DECT baseband controller CLK100 1 75 , switch 0 output CLK100 3 1 O H ISP2DPES 100 Hz signal related to DECT frame timing


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PDF PCD5091 SCA55 437027/00/02/pp16 philips dect LQFP100 footprint footprint jedec QFP100 SIEMENS AVR GENERATOR LQFP100 PCD5032 80C51 PCD5091H PCD5091HZ QFP100
1996 - SIEMENS AVR GENERATOR

Abstract: IC 80C51 microcontroller PCD5090HZ PCD5090H PCD5090 PCD5032 PCA5097H PCA5097 80C51 GMSK dect
Text: package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1 3 1996 Oct 17 4 CLK100 XTAL1 XTAL2 , 13 6 T_DATA S_PWR 5 T_PWR_RMP 11 4 T_ENABLE 12 3 CLK100 S_CLK , ANT_SW1 1 80 WEN ANT_SW0 2 79 SDI CLK100 3 78 SC T_ENABLE 4 77 , 99 ANT_SW1 100 ANT_SW0 DECT baseband controllers CLK100 1 75 OEN T_ENABLE 2


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PDF PCD5090; PCA5097 PCD5090/xxx; PCA5097/xxx; PCx509x SIEMENS AVR GENERATOR IC 80C51 microcontroller PCD5090HZ PCD5090H PCD5090 PCD5032 PCA5097H PCA5097 80C51 GMSK dect
philips dect

Abstract: PCD509x
Text: ' t co i i i i i â ANT.SW1 i~ T ANT_SWO [ T CLK100 [ T T^ENABLE R ~ TJ>WR_RMP Q 3 T_DATA [ X , PCD5093 Table 1 SYMBOL ANT_SW1 ANT_SW0 CLK100 T_ENABLE T_PWR_RMP T_DATA T_GMSK VCO_BND_SW SYNTHJ-OCK


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PDF PCD5093 PCD5091 MBH942 PCD5093 PCD5096) PCD5093) PCX509x. philips dect PCD509x
1994 - TSB11C01

Abstract: SLLS167A TSB11C01DL TSB11C01DLR TSB12C01A
Text: AGND AGND AGND R0 R1 PC2 TPBIAS PC1 PC0 DVCC CLK100 ENCLK100 DGND C/ LKON description , , TEXAS 75265 XI XO PDOUT VCOIN CLK100 ENCLK100 3 TSB11C01 IEEE 1394-1995 TRIPLE-CABLE , I/O NO. 13 ­17, 40 ­ 44 Analog circuit ground AVCC CLK100 2, 3, 6, 7 32 I C , supply voltage ENCLK100 31 I Disable crystal oscillator and PLL, enable CLK100 input ISO , . External clock input ( CLK100 ): When this terminal is asserted high (enabled), an external 98.304


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PDF TSB11C01 SLLS167A TSB11C01 SLLS167A TSB11C01DL TSB11C01DLR TSB12C01A
1997 - SIEMENS AVR GENERATOR

Abstract: philips dect pin diagram of 7430 PCD5092 QFP100 PCD5092H PCD5032 80C51 philips rf manual analog ECHO microphone mixing circuit
Text: -2 1997 Jul 21 4 CLK100 XTAL1 XTAL2 GP_CLK7 DPLL_DATA T_GMSK R_SLICED SLICE_CTR , TST1 CLK100 3 78 VSS4 T_ENABLE 4 77 VDD5V_2 T_PWR_RMP 5 76 A16 , antenna switch 0 output CLK100 3 O H ISP2DPES 100 Hz signal related to DECT frame timing


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PDF PCD5092 SCA55 437027/00/02/pp16 SIEMENS AVR GENERATOR philips dect pin diagram of 7430 PCD5092 QFP100 PCD5092H PCD5032 80C51 philips rf manual analog ECHO microphone mixing circuit
Z/G711

Abstract: No abstract text available
Text: vi e v i C O w P~ · M TST2 ANT^SWO [ T CLK100 [ X T_ENABLE [ T T_PWR_RMP [ I T T , ANT_SW0 CLK100 TJENABLE T_PWR_RMP TDATA T_GMSK VCO_BND_SW SYNTH_LOCK S_ENABLE S_DATA S_CLK S_PWR REF_CLK


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PDF PCD5094 QFP100 GD797 MBH945 PCD5094) PCX509x. Z/G711
philips dect

Abstract: PCD5032
Text: [ ills l| s llil( £ ) [ i] f s ] [ s i[ s | ( ii[ £ l ANT_SW1 f T ANT_SWO Q I CLK100 [ j T T,ENABLE , ANT_SW0 CLK100 T_ENABLE T_PWR_RMP T_DATA T_GMSK VCO_BND_SW SYNTH_LOCK S_ENABLE S_DATA S_CLK S_PWR


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PDF PCD5095 80C51 PCD5095 PCD5091) philips dect PCD5032
gd79

Abstract: p2274 GMSK dect philips dect CCITT recommendation G.721 80C51 keyboard
Text: < lo? Sí ¿ (O in V ¿ n ANT_SW1 [ X ANT^SWO [ X CLK100 [ X T_ENABLE F T T_PWR_RMP [ T i TJJÄ TA , 1 SYMBOL ANT_SW1 ANT_SWO CLK100 T_ENABLE T_PWR_RMP T_DATA T_GMSK VCO_BND_SW SYNTH_LOCK S_ENABLE


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PDF PCD5092 PCD5091 PCD5092) PCX509x. gd79 p2274 GMSK dect philips dect CCITT recommendation G.721 80C51 keyboard
Pin Configuration of IC 78141

Abstract: TSB11C01
Text: ] 38 R 1 PC2 TPBIAS PC1 PC0 33 ] DVCC 32 j CLK100 31 ] ENCLK100 30 ] DGND 29 ] C/LKON , O scillator PLL System and Transm it Clock Generator XO _8 _9 32 31 PDOUT VCOIN CLK100 ENCLK100 , Terminal Functions TERMINAL NAME AGND AVq c CLK100 C/LKON CPS CTL[0:1] D[0:1] DGND DVq c ENCLK100 is o LPS , PLL, enable CLK100 input Phy-link interface isolation status Link power status Link request from , disabled and the external clock input can be used. External clock input ( CLK100 ): when enabled, an external


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PDF TSB11C01 P1394 SLLS167-MARCH 25nstruments CH-8953 A0294 Pin Configuration of IC 78141
1996 - SIEMENS AVR GENERATOR

Abstract: philips dect 80c51 manual siemens PABX pabx systems philips gmsk 80C51 PCD5032 PCD5091 PCD5095
Text: 1.95 mm); body 14 × 20 × 2.8 mm 3 VERSION SOT317-2 1997 Nov 19 4 CLK100 XTAL1 , ANT_SW1 1 80 TST2 ANT_SW0 2 79 TST1 CLK100 3 78 VSS4 T_ENABLE 4 , ANT_SW0 2 O H ISP2DRF3 antenna switch 0 output CLK100 3 O H ISP2DPES 100


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PDF PCD5095 Philips31 SCA52 437027/1200/01/pp16 SIEMENS AVR GENERATOR philips dect 80c51 manual siemens PABX pabx systems philips gmsk 80C51 PCD5032 PCD5091 PCD5095
1994 - TSB11C01

Abstract: SLLS167A TSB12C01A arbiter decoder -1996
Text: AGND AGND AGND R0 R1 PC2 TPBIAS PC1 PC0 DVCC CLK100 ENCLK100 DGND C/ LKON description , , TEXAS 75265 XI XO PDOUT VCOIN CLK100 ENCLK100 3 TSB11C01 IEEE 1394-1995 TRIPLE-CABLE , I/O NO. 13 ­17, 40 ­ 44 Analog circuit ground AVCC CLK100 2, 3, 6, 7 32 I C , supply voltage ENCLK100 31 I Disable crystal oscillator and PLL, enable CLK100 input ISO , . External clock input ( CLK100 ): When this terminal is asserted high (enabled), an external 98.304


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PDF TSB11C01 SLLS167A TSB11C01 SLLS167A TSB12C01A arbiter decoder -1996
1994 - TSB11C01

Abstract: SLLS167A TSB12C01A
Text: AGND AGND AGND R0 R1 PC2 TPBIAS PC1 PC0 DVCC CLK100 ENCLK100 DGND C/ LKON description , , TEXAS 75265 XI XO PDOUT VCOIN CLK100 ENCLK100 3 TSB11C01 IEEE 1394-1995 TRIPLE-CABLE , I/O NO. 13 ­17, 40 ­ 44 Analog circuit ground AVCC CLK100 2, 3, 6, 7 32 I C , supply voltage ENCLK100 31 I Disable crystal oscillator and PLL, enable CLK100 input ISO , . External clock input ( CLK100 ): When this terminal is asserted high (enabled), an external 98.304


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PDF TSB11C01 SLLS167A TSB11C01 SLLS167A TSB12C01A
1997 - SIEMENS AVR GENERATOR

Abstract: philips dect Siemens metro brazil philips gmsk QFP100 PCD5096 PCD5093H PCD5093 PCD5032 80C51
Text: length 1.95 mm); body 14 × 20 × 2.8 mm 3 VERSION SOT317-2 1997 Jul 21 4 CLK100 XTAL1 , 100 RESET_OUT 5 PCD5093 ANT_SW1 1 80 TST2 ANT_SW0 2 79 TST1 CLK100 , antenna switch 0 output CLK100 3 O H ISP2DPES 100 Hz signal related to DECT frame timing


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PDF PCD5093 SCA55 437027/00/01/pp16 SIEMENS AVR GENERATOR philips dect Siemens metro brazil philips gmsk QFP100 PCD5096 PCD5093H PCD5093 PCD5032 80C51
1994 - TSB11C01

Abstract: monitor cable diagram arbiter decoder -1996 characteristics of twisted pair cable IEEE 1394 cable 4 to 4 SLLS167A TSB12C01A
Text: AGND AGND AGND R0 R1 PC2 TPBIAS PC1 PC0 DVCC CLK100 ENCLK100 DGND C/ LKON description , , TEXAS 75265 XI XO PDOUT VCOIN CLK100 ENCLK100 3 TSB11C01 IEEE 1394-1995 TRIPLE-CABLE , I/O NO. 13 ­17, 40 ­ 44 Analog circuit ground AVCC CLK100 2, 3, 6, 7 32 I C , supply voltage ENCLK100 31 I Disable crystal oscillator and PLL, enable CLK100 input ISO , . External clock input ( CLK100 ): When this terminal is asserted high (enabled), an external 98.304


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PDF TSB11C01 SLLS167A TSB11C01 monitor cable diagram arbiter decoder -1996 characteristics of twisted pair cable IEEE 1394 cable 4 to 4 SLLS167A TSB12C01A
SIEMENS AVR GENERATOR

Abstract: philips dect QFP100 PCD5090HZ PCD5090H PCD5090 PCD5032 PCA5097H PCA5097 80C51
Text: output CLK100 3 1 0 H ISP2DPES 100 Hz signal related to DECT frame timing output T_ENABLE 4 2 0 H , ^^loooooooo QtO|<_i t/3cNÌcJcsicjoj ant_sw1 œ • ~8ö1 wen ant_swo cz h] sdì clk100 œ sc t_enable , ‡>OM|<-J C/5c\iojcvi Û-Q-CL>>]LU<|Q.Q.CLD. . v i 111 £ a 5 o o w in CLK100 T_ENABLE T_PWR_RMP


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PDF PCD5090; PCA5097 PCD5090/xxx; PCA5097/xxx; PCx509x 80C51 711DfiEb SIEMENS AVR GENERATOR philips dect QFP100 PCD5090HZ PCD5090H PCD5090 PCD5032 PCA5097H PCA5097
1997 - SIEMENS AVR GENERATOR

Abstract: 80CL51 QFP100 PCD5094H PCD5094 PCD5032 80C51 philips rf manual analog ECHO microphone mixing circuit philips dect
Text: -2 1997 Jul 21 4 CLK100 XTAL1 XTAL2 GP_CLK7 DPLL_DATA T_GMSK R_SLICED SLICE_CTR , TST1 CLK100 3 78 VSS4 T_ENABLE 4 77 VDD5V_2 T_PWR_RMP 5 76 A16 , antenna switch 0 output CLK100 3 O H ISP2DPES 100 Hz signal related to DECT frame timing


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PDF PCD5094 SCA55 437027/00/01/pp16 SIEMENS AVR GENERATOR 80CL51 QFP100 PCD5094H PCD5094 PCD5032 80C51 philips rf manual analog ECHO microphone mixing circuit philips dect
8051 ADC

Abstract: crystal oscillator 13.824 mhz 8051 adpcm DECT mac PCD5032
Text: Vss XTAL1 XTAL2 Vss RESERVED RD WR RDY INT CLK100 Vss DO FS1 FS2 Dl DCLK CLK3 ANT_SW T_ENABLE


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PDF PCD5040/PCD5041 8051 ADC crystal oscillator 13.824 mhz 8051 adpcm DECT mac PCD5032
philips dect

Abstract: PCD5040 crystal oscillator 13.824 mhz philips 8051 microcontroller PCD5032 PCD5041 .47j
Text: 24 interrupt output; active LOW CLK100 25 100 Hz frame timer output Vss 26 negative supply voltage


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PDF PCD5040/PCD5041 philips dect PCD5040 crystal oscillator 13.824 mhz philips 8051 microcontroller PCD5032 PCD5041 .47j
PCD5040

Abstract: PCD5032 PCD5041 crystal oscillator 13.824 mhz 8051 microcontroller OSCILLATOR AND CLOCK 13.824 CRYSTAL
Text: microcontroller INT 24 interrupt output; active LOW CLK100 25 100 Hz frame timer output Vss 26 negative supply


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PDF PCD5040/PCD5041 PCD5040 PCD5032 PCD5041 crystal oscillator 13.824 mhz 8051 microcontroller OSCILLATOR AND CLOCK 13.824 CRYSTAL
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