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Part Manufacturer Description Datasheet Download Buy Part
TPS6508700RSKR Texas Instruments PMIC for AMD™ Family 17h Models 10h-1Fh Processors 64-VQFN -40 to 85
TPS6508700RSKT Texas Instruments PMIC for AMD™ Family 17h Models 10h-1Fh Processors 64-VQFN -40 to 85

CI VIPER 17H Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1995 - VIPER 27

Abstract: VIPer 32 VIPER 22 VIPER 56 OPTi viper VIPer 73 VIPER 55 Viper 15 viper 12 VIPER 06
Text: IDT7MPV6214/15/16/17 256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PENTIUM CPU/OPTi VIPER CORE , SECONDARY CACHE MODULES FOR THE INTEL PENTIUMTM CPU AND OPTiTM VIPER CORE LOGIC CHIPSET FEATURES · For Intel 3.3V Pentium-based systems using the OPTi Viper core logic chipset · Asynchronous and , CPU and the OPTi Viper core logic chipset. The IDT7MPV6214/15 use IDT's 71V256 32K x 8 static RAMs , OPTi Viper chipset. Four PD (presence detect) input pins allow the system to determine if cache is


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PDF IDT7MPV6214/15/16/17 256KB/512KB 256KB 512KB CELP2X80SC3Z48 66MHz 7MPV6214 7MPV6215 7MPV6216 7MPV6217 VIPER 27 VIPer 32 VIPER 22 VIPER 56 OPTi viper VIPer 73 VIPER 55 Viper 15 viper 12 VIPER 06
1995 - VIPER 27

Abstract: VIPER 22 VIPER 06 viper 32 VIPER 300 VIPER 27 application notes viper 53 "32K x 32" SRAM Viper 15 viper 17
Text: IDT7MPV6214/15/16/17 256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PENTIUM CPU/OPTi VIPER CORE , SECONDARY CACHE MODULES FOR THE INTEL PENTIUMTM CPU AND OPTiTM VIPER CORE LOGIC CHIPSET FEATURES · For Intel 3.3V Pentium-based systems using the OPTi Viper core logic chipset · Asynchronous and , CPU and the OPTi Viper core logic chipset. The IDT7MPV6214/15 use IDT's 71V256 32K x 8 static RAMs , OPTi Viper chipset. Four PD (presence detect) input pins allow the system to determine if cache is


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PDF IDT7MPV6214/15/16/17 256KB/512KB 256KB 512KB CELP2X80SC3Z48 66MHz 7MPV6214 7MPV6215 VIPER 27 VIPER 22 VIPER 06 viper 32 VIPER 300 VIPER 27 application notes viper 53 "32K x 32" SRAM Viper 15 viper 17
Not Available

Abstract: No abstract text available
Text: i l l a t o r i np u t · L o w C P U and P CI c l oc k jitter < 250 ps c y c l e - t o - c y c l e in s y n c h r o n o u s P CI m o d e · L o w s ke w o ut puts - < . 2 00 p s b e t w e e n C P U c , using the OPTi Viper chipset. The CY2256 has low-skew outputs (< 200 ps between the CPU Clocks, 200 ps , Intel Corporation. OPTi Viper is a registered trademark of OPTi Corporation. Pentium is a trademark of , 14.318 MHz 14.318 MHz 14.318 MHz High-Z P CI M o d e 0 0 0 0 1 1 1 1 N otes: 0 0 1 1 0 0 1 1


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PDF CY2256
PS2303

Abstract: VIPer Design Software DA1A23 viper gate control circuits VIPER IC MV7011 Viper MIPS VIPER 51 Self-checking circuit
Text: RSRE VIPER * 1A specification. The use of formal mathematical techniques in the design of the VIPER 1A , design is its ability to operate with another VIPER 1A in a self-checking pair with facilities for , DA I A COMPARI PARI IV Gl N/CMK ±_±. j Kl CISUR StLI CI , t t t t X V p , Processor for Enhanced Reliability ( VIPER ) has been developed by the Royal Signals and Radar Establishment , the device is a true implementation of its specification The MV7011 meets the specification for VIPER


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PDF MV7011 32-BIT MV7011 PS2303 VIPer Design Software DA1A23 viper gate control circuits VIPER IC Viper MIPS VIPER 51 Self-checking circuit
1997 - c548 transistor

Abstract: DVB-T modulator viper lcd front panel display DSP TMS320C32 equivalent of transistor C6000 C6201 C6000 AVC fans argos transmitter acpm750
Text: Gateway Control Interface SkyWare 98 PSTN CALL CONTROL G.723 G.729a VIPER -12 features s , TI DSP: TMS320C548 s Third-party product: VIPER -12 board by DSP Research (DSPR) s Success achieved , Internet. At the heart of the SkyGate 98 system is the VIPER -12 board from DSP IP CALL MANAGEMENT , , VIPER -12 offers the processing power needed to meet the demands of a highdensity VoIP gateway. The VIPER -12 delivers up to 60 channels of voice data, allowing each SkyGate 98 to deliver up to 960


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PDF TPA005D02 C6000 com/sc/9810. c548 transistor DVB-T modulator viper lcd front panel display DSP TMS320C32 equivalent of transistor C6000 C6201 AVC fans argos transmitter acpm750
2003 - STI5519

Abstract: viper32 STI5518 sti5516 STI5518B STV0700 sti5519 DATASHEETS STI5528 STV0499 STI5517
Text: digital solutions. These are fully supported by common interface ( CI ) and smartcard products, providing , Digital cable CI /POD OMEGA 100Hz TV TV switch TV Digital satellite DVD R/W , features Part number Dolby, CSS descrambler Multi-CA, embedded dual CI Dual decode, Dolby/AAC/MP3 , Standard logics PCMCIA ( CI ) VFD controller/driver Modem return channel ST also offers an 8/16 , CPU overhead. ST's standard products include a broad range of devices, as common interface ( CI


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2002 - V17H

Abstract: No abstract text available
Text: /8/02; v. 1.7H Alliance Semiconductor 1 of 12 Copyright © Alliance Semiconductor. All rights , VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC 1& 2/8/02; v. 1.7H Alliance , -ball 14×20 mm BGA package. Capacitance Parameter Input capacitance I/O capacitance Symbol CIN CI /O , ; v. 1.7H Alliance Semiconductor 3 of 12 AS7C33512NTD16A AS7C33512NTD18A ® Signal , maximum rating conditions may affect reliability. 2/8/02; v. 1.7H Alliance Semiconductor 4 of 12


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PDF AS7C33512NTD16A AS7C33512NTD18A in100-pin 119-ball V17H
2003 - 2408NL

Abstract: 2410ML 2N3904 LM87 LM87CIMT LM87CIMT1 LM87CIMTX
Text: is also an internal open-drain output on this line, controlled by Bit 7 of the CI Clear Register (46h), to provide a minimum 20 ms pulse. FAN1/AIN1FAN2/AIN2 CI www.national.com Type , (SMBData, RESET#, CI , INT#, THERM#) VOUT(0) Logical "0" Output Voltage (SMBData) IOUT = -755 µA , ) Pulse Width DIGITAL INPUTS: VID0­VID4, NTEST_IN, ADD/NTEST_OUT, Chassis Intrusion ( CI ) VIN(1 , # x x x 0 100k 1M CI x x x 0 FAN1­FAN2 x x x 0


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2001 - 2408NL

Abstract: 2410ML 2N3904 LM87 LM87CIMT LM87CIMT1 LM87CIMTX
Text: CI Clear Register (46h), to provide a minimum 20 ms reset pulse. FAN1/AIN1FAN2/AIN2 CI , (SMBData, RESET#, CI , INT#, THERM#) VOUT(0) Logical "0" Output Voltage (SMBData) VOUT(0) Logical , ) Pulse Width DIGITAL INPUTS: VID0­VID4, NTEST_IN, ADD/NTEST_OUT, Chassis Intrusion ( CI ) VIN(1 , # x x x 0 100k 1M CI x x x 0 FAN1­FAN2 x x x 0 , each of the two hardware Interrupt outputs. · CI Clear Register: Allows transmitting a 20 ms low


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2010 - Dallas Texas Transistor Book

Abstract: No abstract text available
Text: internal open-drain output on this line, controlled by Bit 7 of the CI Clear Register (46h), to provide a , the VID4 Register. These inputs have on-chip 100 k pullup resistors. CI 7 1 Digital I/O , ) V (max) 8800 4400 2200 1100 ±10 ±15 ±20 255 OPEN- DRAIN DIGITAL OUTPUTS (SMBData, RESET#, CI , INT , , ADD/NTEST_OUT, Chassis Intrusion ( CI ) VIN(1) VIN(0) VIN(1) VIN(0) VHYST VIN(1) VIN(0) IIN(1) IIN(0 , INT# CI FAN1­FAN2 SMBCLK SMBData RESET# ADD/NTEST_OUT D1 x x x x x x x D2 x x x x x x x D3 x


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PDF SNAS034I Dallas Texas Transistor Book
2001 - 2N3904

Abstract: LM87 LM87CIMT LM87CIMT1 LM87CIMTX
Text: output. SMBCLK FAN1/AIN1FAN2/AIN2 CI www.national.com Type Description 4 1 Digital , open-drain output on this line, controlled by Bit 7 of the CI Clear Register (46h), to provide a minimum 20 , DIGITAL OUTPUTS (SMBData, RESET#, CI , INT#, THERM#) VOUT(0) Logical "0" Output Voltage (SMBData , Intrusion ( CI ) VIN(1) Logical "1" Input Voltage 2.0 V (min) VIN(0) Logical "0" Input Voltage , 0 100k 1M +12Vin x x R1+R2 130k CI x x x 0 1M


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FEP30JP

Abstract: No abstract text available
Text: resistance Low power loss, high efficiency High temperature soldering guaranteed: 250*C,. 17H , 4.3mm from case for 10 seconds _ MECHANICAL DATA Case: TO-3P POSITIVE CI NE6ATIVE Cl SUFFIX


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PDF FEP30AP FEP30JP MIL-STD-202, FEP30JP
2010 - 2408NL

Abstract: 2410ML 2N3904 LM87 LM87CIMT LM87CIMT1 LM87CIMTX2 SM21 2n390
Text: digital Schmitt Trigger fan tachometer inputs. FAN1/AIN1FAN2/AIN2 www.national.com 2 CI , internal open-drain output on this line, controlled by Bit 7 of the CI Clear Register (46h), to provide a , (SMBData, RESET#, CI , INT#, THERM#) VOUT(0) Logical "0" Output Voltage (SMBData) IOUT = -755 A , ms (min) DIGITAL INPUTS: VID0­VID4, NTEST_IN, ADD/NTEST_OUT, Chassis Intrusion ( CI ) VIN(1 , INT# x x x 0 100k 1M +12Vin x x R1+R2 CI x x x 0


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PCL-80K

Abstract: constant speed plc-80k pcl80 ramps 1.4
Text: reset is provided. D 7 D6 D5 D 4 D 3 D 2 D 1 DO CI CO -Command- CI CO 0 0 Operating mode , , high-place 8 bits For FH1 Command buffer «- 00010101 (15H) For FH2 Command buffer <- 00010111 ( 17H ) i , (48H) For FH1 Command buffer <- 00010101 (15H) For FH2 Command buffer «- 00010111 ( 17H ) Enter the , (15H) 00010111 ( 17H ) When the SD signal of the same direction as the preset direction is low level (ON , data. Command buffer «- 00010101 (15H) Command buffer «- 00010111 ( 17H ) Note: If the start command


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PDF PCL-80K PCL-80K 24-bit constant speed plc-80k pcl80 ramps 1.4
SDA5241

Abstract: SDA-2083 IC A5162 K28H sda 5241 teletext 114H 125L CONDENSATOR sda 20160
Text: 114H 10 mA Output current F6 - / 17H 10 mA Output current sync. /1 5 mA Thermal resistance , data processing Input current for low2) for high 2> Voltage Ii = - 25 to - 1000 |uA /7L 17H V? - 175 - , Optimized PLL Behaviour Ci l nF 10 nF C2 47 nF 1 |uF Cs 220 nF 330 nF Ca 47 nF 33 nF 1 k£2 500 Q R2 , Application Circuit LC-Tank-Circuit Loop Filter Components Standard Application Optimized PLL Behaviour Ci


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PDF P-DIP-28-1 67000-A5162 UED00035 UES00037 UES00038 SDA5241 SDA-2083 IC A5162 K28H sda 5241 teletext 114H 125L CONDENSATOR sda 20160
lora

Abstract: marking lora
Text: o o o o o o o o o o o o o o o p o o o o o o oo oo o l o o o o o o o o o ci o - H -*2 49 , o rt co nn ecto r, 17H se rie s FOR MATERIALS AMD FINISH* 'DRAWING FILE : SEE NOTES REMOVE SHARP


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PDF 08/rs/n L17H16E2130 lora marking lora
LM87CIMTX2

Abstract: 2N3904 LM81 LM87 LM87CIMT LM87CIMT1
Text: €” Vccpl CI — 7 18 — +2.5Vin/D2+ GND — 8 17 — Vccp2/D2- V4" — 9 16 — +5.0Vin INT#/ALERT# â , fan tachometer inputs. CI 7 1 Digital I/O An active high input from an external circuit which latches , of the CI Clear Register (46h), to provide a minimum 20 ms reset pulse. www.national.com 2 Pin , *, CI , INT#, THERM*) ^out(o) Logical "0" Output Voltage (SMBData) lOUT = -755 nA 0.4 V (min , INPUTS: VID0-VID4, NTESTJN, ADD/NTEST OUT, Chassis Intrusion ( CI ) v|n(1) Logical "1" Input Voltage


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1999 - Not Available

Abstract: No abstract text available
Text: of the LM87. There is also an internal open-drain output on this line, controlled by Bit 7 of the CI , SMBData SMBCLK FAN1/AIN1FAN2/AIN2 CI 3 4 5-6 7 1 1 2 1 Digital I/O Digital Input Analog/Digital , OPEN- DRAIN DIGITAL OUTPUTS (SMBData, RESET#, CI , INT#, THERM#) Logical "0" Output Voltage (SMBData , Intrusion Pulse Width DIGITAL INPUTS: VID0­VID4, NTEST_IN, ADD/NTEST_OUT, Chassis Intrusion ( CI ) VIN(1) VIN , temperature or voltage measurement. Pin Name INT# CI FAN1­FAN2 SMBCLK SMBData RESET# ADD/NTEST_OUT D1 x


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2000 - Not Available

Abstract: No abstract text available
Text: of the LM87. There is also an internal open-drain output on this line, controlled by Bit 7 of the CI , SMBData SMBCLK FAN1/AIN1FAN2/AIN2 CI 3 4 5-6 7 1 1 2 1 Digital I/O Digital Input Analog/Digital , (Limits) OPEN- DRAIN DIGITAL OUTPUTS (SMBData, RESET#, CI , INT#, THERM#) VOUT(0) Logical "0" Output , Intrusion ( CI ) VIN(1) VIN(0) VIN(1) VIN(0) VHYST VIN(1) VIN(0) IIN(1) IIN(0) CIN Logical "1" Input Voltage , 50 mV may corrupt a temperature or voltage measurement. Pin Name INT# CI FAN1­FAN2 SMBCLK SMBData


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2000 - 2N3904

Abstract: LM87 LM87CIMT LM87CIMT1 LM87CIMTX marking code 1317 surface mount diode
Text: is also an internal open-drain output on this line, controlled by Bit 7 of the CI Clear Register (46h), to provide a minimum 20 ms reset pulse. FAN1/AIN1FAN2/AIN2 CI www.national.com Type , 3.0 mA at V+ = +3.8 V 0.4 V (max) OPEN- DRAIN DIGITAL OUTPUTS (SMBData, RESET#, CI , INT , Width DIGITAL INPUTS: VID0­VID4, NTEST_IN, ADD/NTEST_OUT, Chassis Intrusion ( CI ) VIN(1) Logical "1" , D3 R1 INT# x x x CI x x FAN1­FAN2 x x R3 R4 0 100k


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2000 - sanyo denki stepping

Abstract: 2N3904 LM87 LM87CIMT LM87CIMT1 LM87CIMTX structure of computer
Text: the CI Clear Register (46h), to provide a minimum 20 ms reset pulse. FAN1/AIN1FAN2/AIN2 CI , 3.0 mA at V+ = +3.8 V 0.4 V (max) OPEN- DRAIN DIGITAL OUTPUTS (SMBData, RESET#, CI , INT , Width DIGITAL INPUTS: VID0­VID4, NTEST_IN, ADD/NTEST_OUT, Chassis Intrusion ( CI ) VIN(1) Logical "1" , D3 R1 INT# x x x CI x x FAN1­FAN2 x x R3 R4 0 100k , Interrupt outputs. · CI Clear Register: Allows transmitting a 20 ms low pulse on the chassis


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2013 - Not Available

Abstract: No abstract text available
Text: the DS1624. The command set for the DS1624 as shown in Table 3 is as follows. Access Memory [ 17h , -byte 17h EEPROM memory. Reads or writes configuration data ACh to , Memory TX RX 17h command protocol. RX TX ACK DS1624 generates acknowledge bit. Bus master sets , Access Memory TX RX 17h command protocol. RX TX ACK DS1624 generates acknowledge bit. Bus master , 0 0.4 0.6 V V 1 1 -1 +1 µA 2 10 pF CI /O ICC 10 Â


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PDF DS1624 12-Bit 200ms
2002 - DS1624S

Abstract: DS1624
Text: follows: 8 of 16 DS1624 Access Memory [ 17h ] This command instructs the DS1624 to access its E 2 , Reads or writes to 256-byte 17h EEPROM memory. Reads or writes configuration data ACh , ACK DS1624 generates acknowledge bit. TX RX 17h Bus Master sends Access Memory command protocol , Master sends DS1624 address; R/ W =0; RX TX ACK DS1624 generates acknowledge bit. TX RX 17h Bus , each I/O pin I/O Capacitance Active Supply Current Standby Supply Current CI /O ICC MAX


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PDF DS1624 13-bit DS1624 DS1624S
Not Available

Abstract: No abstract text available
Text: Access Memory [ 17h ] This command instructs the DS1624 to access its E2 memory. After issuing this , -byte 17h EEPROM memory. Reads or writes configuration data ACh to , bit. TX RX 17h Bus Master sends Access Memory command protocol. RX TX ACK DS1624 generates , DS1624 generates acknowledge bit. TX RX 17h Bus Master sends Access Memory command protocol. RX TX , 3, 4 CI /O ICC 0.7VDD NOTES 1 VDD+ 0.5 50 VOL2 Input Current each I/O pin I/O


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PDF DS1624 13-bit
2013 - Not Available

Abstract: No abstract text available
Text: the DS1624. The command set for the DS1624 as shown in Table 3 is as follows. Access Memory [ 17h , -byte 17h EEPROM memory. Reads or writes configuration data ACh to , Memory TX RX 17h command protocol. RX TX ACK DS1624 generates acknowledge bit. Bus master sets , Access Memory TX RX 17h command protocol. RX TX ACK DS1624 generates acknowledge bit. Bus master , Standby Supply Current tSP VOL1 VOL2 CI /O ICC UNITS NOTES °C 10 °C 0.3VDD VDD +


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PDF DS1624 12-Bit 200ms
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