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Part Manufacturer Description Datasheet Download Buy Part
LT1103CY Linear Technology IC SWITCHING CONTROLLER, Switching Regulator or Controller
LT3524S Linear Technology IC SWITCHING CONTROLLER, PDSO, Switching Regulator or Controller
LT1945IMS Linear Technology IC 0.4 A DUAL SWITCHING CONTROLLER, PDSO8, PLASTIC, MSOP-10, Switching Regulator or Controller
LTC3830DWF Linear Technology IC SWITCHING CONTROLLER, 250 kHz SWITCHING FREQ-MAX, UUC, DIE, Switching Regulator or Controller
LTC1735CS8 Linear Technology IC SWITCHING CONTROLLER, PDSO8, SO-8, Switching Regulator or Controller
LT3524CS Linear Technology IC SWITCHING CONTROLLER, PDSO, Switching Regulator or Controller

CDI Controller Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1993 - motorola 68000 pin diagram

Abstract: an1063 motorola 68000 block diagram MC68341V MC68341 MC68340 M68300 MICROPROCESSOR 68000 MC6805 motorola MC68000
Text: CD-I 's specific needs. The MC68341 contains a 68020-based CPU32, a two channel DMA controller , two , MC68341V Product Brief Integrated CD-I Engine The MC68341 is a member of the M68300 family of integrated processors designed specifically for the compact disc-interactive ( CD-I ) market. It improves on , MC68341. SYSTEM INTEGRATION MODULE (SIM41) TIMER TWO-CHANNEL DMA CONTROLLER SYSTEM , Chip-Select, Wait State Generation, Bus Watchdog - Interrupt Controller - IEEE 1149.1 Boundary Scan (JTAG


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PDF MC68341/D MC68341 MC68341V MC68341 M68300 MC68340 68020-based CPU32, SIM41) motorola 68000 pin diagram an1063 motorola 68000 block diagram MC68341V MICROPROCESSOR 68000 MC6805 motorola MC68000
1993 - MC68000

Abstract: Motorola MC6805 pin diagram M68300 MC68340 MC68341 MC68341V MC6805 motorola an1063
Text: CD-I 's specific needs. The MC68341 contains a 68020-based CPU32, a two channel DMA controller , two , MC68341V Product Brief Integrated CD-I Engine The MC68341 is a member of the M68300 family of integrated processors designed specifically for the compact disc-interactive ( CD-I ) market. It improves on , MC68341. SYSTEM INTEGRATION MODULE (SIM41) TIMER TWO-CHANNEL DMA CONTROLLER SYSTEM , Chip-Select, Wait State Generation, Bus Watchdog - Interrupt Controller - IEEE 1149.1 Boundary Scan (JTAG


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PDF MC68341/D MC68341 MC68341V MC68341 M68300 MC68340 68020-based CPU32, SIM41) MC68000 Motorola MC6805 pin diagram MC68341V MC6805 motorola an1063
1993 - AN1063

Abstract: cdi reference design MC68341 MC6805 pin configuration mc68000 68020-BASED motorola mc6805 development board Motorola MC6805 pin diagram Motorola MC6805 MC68340
Text: CD-I 's specific needs. The MC68341 contains a 68020-based CPU32, a two channel DMA controller , two , MC68341V Product Brief Integrated CD-I Engine The MC68341 is a member of the M68300 family of integrated processors designed specifically for the compact disc-interactive ( CD-I ) market. It improves on , MC68341. SYSTEM INTEGRATION MODULE (SIM41) TIMER TWO-CHANNEL DMA CONTROLLER SYSTEM , Chip-Select, Wait State Generation, Bus Watchdog - Interrupt Controller - IEEE 1149.1 Boundary Scan (JTAG


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PDF MC68341/D MC68341 MC68341V MC68341 M68300 MC68340 68020-based CPU32, SIM41) AN1063 cdi reference design MC6805 pin configuration mc68000 motorola mc6805 development board Motorola MC6805 pin diagram Motorola MC6805
motorola mc6805 manual

Abstract: motorola CDI motorola 68020 manual MICROPROCESSOR 68000 manual MC6805 digital count up and countdown timer MC68000 cdi diagram Motorola MC6805 pin diagram MICROPROCESSOR MC68000 manual
Text: designed specifically for the compact disc-interactive ( CD-I ) market. It improves on the feature set of the MC68340 for a more complete and cost effective integrated system solution to CD-I 's specific needs. The MC68341 contains a 68020-based CPU32, a two channel DMA controller , two serial channels, a timer, and a , €” Chip-Select, Wait State Generation, Bus Watchdog — Interrupt Controller — IEEE 1149.1 Boundary Scan (JTAG , DMA controller , a serial module, a queued serial peripheral interface, and a timer. The IMB is the


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PDF MC68341 M68300 MC68340 68020-based CPU32, SIM41) MC68000 motorola mc6805 manual motorola CDI motorola 68020 manual MICROPROCESSOR 68000 manual MC6805 digital count up and countdown timer cdi diagram Motorola MC6805 pin diagram MICROPROCESSOR MC68000 manual
1993 - an1063

Abstract: MC6805 motorola Motorola MC6805 pin diagram Motorola MC6805 MC6805 MC6805 motorola microprocessor interfaces motorola mc6805 development board cdi circuit diagram MC68000 AN1063/D
Text: Semiconductor, Inc. Integrated CD-I Engine The MC68341 is a member of the M68300 family of integrated processors designed specifically for the compact disc-interactive ( CD-I ) market. It improves on the feature set of the MC68340 for a more complete and cost effective integrated system solution to CD-I 's specific needs. The MC68341 contains a 68020-based CPU32, a two channel DMA controller , two serial , MC68341. SYSTEM INTEGRATION MODULE (SIM41) TIMER TWO-CHANNEL DMA CONTROLLER SYSTEM


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PDF MC68341/D MC68341 MC68341V MC68341 M68300 MC68340 an1063 MC6805 motorola Motorola MC6805 pin diagram Motorola MC6805 MC6805 MC6805 motorola microprocessor interfaces motorola mc6805 development board cdi circuit diagram MC68000 AN1063/D
2010 - cdi unit

Abstract: cdi circuit diagram LC7940KD LC7941KDR LC7942KD QIP100D 6 pin cdi lc7942k
Text: ···· ···· M ···· ···· FLM ···· ···· Controller LOAD CP SDI CDI , read 4-bit parallel or serial input, display data from a controller into an 80-bit latch, and then , DISPOFF P/S VSS VEE V4 V3 NC VDD V1 M DI1 DI2 DI3 SDI LOAD CDI CP O30 O26 O27 O28 , O75 O74 O73 1 2 3 4 5 6 O80 O79 O78 O77 CP CDI LOAD SDI DI3 DI2 DI1 M V1 VDD NC , (7bits) DI1 P/S 20 SER/PAR Control Chip Disable & Latch Control CDO CDI CP LOAD


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PDF ENA0573 LC7940KD LC7941KDR LC7940KD LC7941KDR 80-bit LC7942KD QIP80D) cdi unit cdi circuit diagram LC7942KD QIP100D 6 pin cdi lc7942k
1999 - 240-PIXEL

Abstract: 6 pin cdi la5311 128Display LCD 07 064 060
Text: displays. They read 4­ bit parallel or serial input, display data from a controller into an 80­bit latch , VIL CP, CDI , Dl1 to DI3, M, SDl, P/S,DISPOFF and LOAD ­ ­ 0.2VDD V CP shift clock , max HIGH­level input current IIH VIN =VDD; LOAD, CP, CDI , P/S, DI1 to DI3, SDl, M, and , Conditions Unit min typ max IST CDI = VDD, VDD ­ VEE = 18 V, fCP = 3.3 MHz, no output load , 98 33 033 CDI 99 32 032 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19


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PDF LC7940YD 7941YD LC7941YD QIP100D LC7940YD, LC7941YD] 45max l/128display 240-PIXEL 6 pin cdi la5311 128Display LCD 07 064 060
1999 - transistor C 2240

Abstract: cdi unit c 2240 DIO64
Text: parallel or serial input, display data from a controller into an 80­bit latch, and then generate LCD drive , , DISPOFF and LOAD 0.8VDD ­ ­ V LOW­level inpvt voltage VIL CP, CDI , Dl1 to DI3, M , HIGH­level input current IIH VIN =VDD; LOAD, CP, CDI , P/S, DI1 to DI3, SDl, M, and DISPOFF ­ ­ , typ max IST CDI = VDD, VDD ­ VEE = 18 V, fCP = 3.3 MHz, no output load ; VSS ­ ­ , O29 O30 V1 CP CDI LOAD SDI DI3 DI2 DI1 M Pad Layout (Top view) M DI1 DI2 DI3


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PDF LC7940YC 7941YC LC7941YC LC7942YC l/128 transistor C 2240 cdi unit c 2240 DIO64
2010 - n2206

Abstract: b8852 LC7942KD QIP100D 6 pin cdi LC7941KDR lc7940 LC7942K cdi circuit diagram LC7940KD
Text: ···· ···· M ···· ···· FLM ···· ···· Controller LOAD CP SDI CDI , read 4-bit parallel or serial input, display data from a controller into an 80-bit latch, and then , DISPOFF P/S VSS VEE V4 V3 NC VDD V1 M DI1 DI2 DI3 SDI LOAD CDI CP O30 O26 O27 O28 , O75 O74 O73 1 2 3 4 5 6 O80 O79 O78 O77 CP CDI LOAD SDI DI3 DI2 DI1 M V1 VDD NC , (7bits) DI1 P/S 20 SER/PAR Control Chip Disable & Latch Control CDO CDI CP LOAD


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PDF ENA0573 LC7940KD LC7941KDR LC7940KD LC7941KDR 80-bit LC7942KD QIP80D) n2206 b8852 LC7942KD QIP100D 6 pin cdi lc7940 LC7942K cdi circuit diagram
mc6809 Application note

Abstract: MK48T08 an618 real time MC6809
Text: Acquisition System Application Figure 3. CDI ROM System Application MC6809 MPu Access Controller Video Sub System Video RAM DMA Controller Input Device MK48T18 RTC + 8K X 8 SRAM Audio Sub System ROM RAM CD-I Interface CD - DA Controller Interface Unit CD Player 2/3 , CDI ROM System The TIMEKEEPER products provide one of the best solutions to both these needs. They , Real TIME CLOCK is the Compact Disk Interactive system. In the CDI system the SRAM stores the system


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2006 - EN6158

Abstract: 240-PIXEL LC7941YD 6 pin cdi QIP100D QFP100D LC7942YD LC7940YD LA5311M DI01
Text: controller into an 80­bit latch, and then generate LCD drive signals corresponding to that data. unit , LOAD 0.8VDD ­ ­ V LOW­level inpvt voltage VIL CP, CDI , Dl1 to DI3, M, SDl, P/S , VIN =VDD; LOAD, CP, CDI , P/S, DI1 to DI3, SDl, M, and DISPOFF ­ ­ 1 µA LOW­level , LC7940YD, LC7941YD Ratings Parameter Symbol Conditions Unit min typ max IST CDI = , DI3 96 35 035 SDI 97 34 034 LOAD 98 33 033 CDI 99 32 032


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PDF EN6158 LC7940YD, 7941YD LC7940YD LC7941YD QIP100D LC7941YD] EN6158 240-PIXEL 6 pin cdi QIP100D QFP100D LC7942YD LA5311M DI01
MC68000

Abstract: MC68340 space qualified synthesizer, 48 bits M68300 MC68010 MC68020 MC68302 MC68340V space qualified synthesizer mil
Text: - 68020- BASED CHANNEL PROCESSOR SERIAL I/O INTERMODULE BUS TWO-CHANNEL DMA CONTROLLER TIMER TIMER , Controller for High-Speed Memory Transfers — Single- or Dual-Address Transfers — 32-Bit Addresses and , controller , a serial module, and two timers. The processor communicates with these modules over the on-chip , between the internal CPU32 or DMA controller and memory, peripherals, or other processing elements in the , controller , used to quickly move large blocks of data between internal peripherals, external peripherals, or


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PDF MC68340 32-bit M68000-compatible CPU32 16-bit MC68340. MC68000 space qualified synthesizer, 48 bits M68300 MC68010 MC68020 MC68302 MC68340V space qualified synthesizer mil
SDN0080G

Abstract: cdi dc/dc dc dc for CDI Circuit cdi schematics dc cdi schematic diagram SDN8000G QFP100 LQFP100 cdi unit SEG339
Text: interfacing with a controller . · Can be cascaded to expand segment number. · Operating voltage range (for , bits) Chip Disable & Latch Control CDO CDI CP LOAD Fig.1 Functional Block Diagram , 52 51 CDI V1 V3 V4 VEE M LOAD VSS DISPOFF VDD R/L NC NC NC DI4 DI3 DI2 DI1 CP CDO , O1~O80 Output Please refer to Table 3 for output voltage level. Chip Disable pin. 81 CDI , reception from a controller . 92, 93, 94 NC Input V1 and VEE are selected levels. V3 and V4 are


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PDF SDN0080G 80-Segment SDN0080G SDN8000G 80-common 80-output cdi dc/dc dc dc for CDI Circuit cdi schematics dc cdi schematic diagram QFP100 LQFP100 cdi unit SEG339
2006 - 6 pin cdi

Abstract: LC7940KD LC7941KDR LC7942KD QIP100D cdi diagram lc7940k lc7942k B8852
Text: read 4-bit parallel or serial input, display data from a controller into an 80-bit latch, and then , DISPOFF P/S VSS VEE V4 V3 NC VDD V1 M DI1 DI2 DI3 SDI LOAD CDI CP O30 O26 O27 O28 , O75 O74 O73 1 2 3 4 5 6 O80 O79 O78 O77 CP CDI LOAD SDI DI3 DI2 DI1 M V1 VDD NC , (7bits) DI1 P/S 20 SER/PAR Control Chip Disable & Latch Control CDO CDI CP LOAD , CDI I Chip disable. 98 83 LOAD I Data is read in When LOW, and not read in When


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PDF ENA0573 LC7940KD LC7941KDR LC7940KD LC7941KDR 80-bit LC7942KD QIP80D) 6 pin cdi LC7942KD QIP100D cdi diagram lc7940k lc7942k B8852
LC79430K

Abstract: No abstract text available
Text: LC79401KNE latches 80 bits of display data sent from a controller using a 4-bit parallel transfer technique , Input high level voltage VIH DI1 to DI4, CP, LOAD, CDI , R/L, M, DISPOFF Input low level voltage VIL DI1 to DI4, CP, LOAD, CDI , R/L, M, DISPOFF CP Shift clock fCP CP CP pulse , IIH Input low level current IIL VIN=VSS, LOAD, CP, CDI , R/L, DI1 to DI4, M, DISPOFF , resistance min VIN=VDD, LOAD, CP, CDI , R/L, DI1 to DI4, M, DISPOFF unit 1 -1 µA µA VDD


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PDF ENA1419 LC79401KNE LC79401KNE 80-outputs LC79430KNE QIP100E) A1419-8/8 LC79430K
AO1041

Abstract: cdi circuit diagram 6 pin cdi A01043 LC79431D LC79430D LC79401D QIP100D EN4366B display 8 segment
Text: of display data sent from a controller using a 4-bit parallel transfer technique and generates LCD , alternation signal 81 CDI Input Chip disable pin High level: Data is not acquired Low level: Data is acquired. 100 CDO Output Connect to the CDI pin on the next chip when cascade connection is used. 89 , Vb-=VDD-2/16vLC0 vlcd Vc-VDD-14/16Vlcd Vd-VDD-15/16VLCD -«- Va-VDD-VLC0 No. 4366-5/8 Controller FLM , Supply voltage (LCD) Vdd-Vee *2, 3 12 32 V Input high level voltage Vih DM to DI4, CP, LOAD, CDI , R/L


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PDF EN4366B LC79401D LC79401D LC7943D QIP80D) LC79430D QIP100D) LC79431D AO1041 cdi circuit diagram 6 pin cdi A01043 LC79431D LC79430D QIP100D EN4366B display 8 segment
Not Available

Abstract: No abstract text available
Text: systems. The LC79401KNE latches 80 bits of display data sent from a controller using a 4-bit parallel , , 3 DI1 to DI4, CP, LOAD, CDI , R/L, M, DISPOFF DI1 to DI4, CP, LOAD, CDI , R/L, M, DISPOFF CP CP LOAD , *7 Input capacitance CI Conditions VIN=VDD, LOAD, CP, CDI , R/L, DI1 to DI4, M, DISPOFF VIN=VSS, LOAD, CP, CDI , R/L, DI1 to DI4, M, DISPOFF IOH=-400A, CDO IOL=400A, CDO VDD-VEE=30V, VDE-VO=0.5V: O1 to O80 , 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CDI V1 V3 V4


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PDF ENA1419 LC79401KNE LC79401KNE 80-outputs LC79430KNE QIP100E) A1419-8/8
1995 - AN1063/D

Abstract: DRAM Controller for the MC68340 MC68340 digital count up and countdown timer M68340 MC68000 MC68010 MC68HC000 M68000 64 pin hardware interface MC68000
Text: EXTERNAL BUS INTERFACE INTERMODULE BUS BUS ARBITRATION IEEE TEST TWO-CHANNEL DMA CONTROLLER , · Two-Channel Low-Latency DMA Controller for High-Speed Memory Transfers - Single- or Dual-Address , XTAL EXTAL TWO-CHANNEL DMA CONTROLLER IRQ7/PORT B7 IRQ6/PORT B6 IRQ5/PORT B5 IRQ3/PORT B3 , modules and typical glue logic. These functions on the MC68340 include the SIM40, a DMA controller , a , of information between the internal CPU32 or DMA controller and memory, peripherals, or other


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PDF MC68340/D MC68340 MC68340V MC68340 32-bit M68000-compatible CPU32 AN1063/D DRAM Controller for the MC68340 digital count up and countdown timer M68340 MC68000 MC68010 MC68HC000 M68000 64 pin hardware interface MC68000
1992 - M68300

Abstract: MC68000 MC68010 MC68020 MC68302 MC68340 MC68340V space qualified synthesizer, 48 bits MC68332
Text: TWO-CHANNEL DMA CONTROLLER TIMER MODULE TIMER MODULE Figure 1. MC68340 Simplified Block Diagram , · Two-Channel Low-Latency DMA Controller for High-Speed Memory Transfers - Single- or Dual-Address , TWO-CHANNEL DMA CONTROLLER IRQ7/PORT B7 IRQ6/PORT B6 IRQ5/PORT B5 IRQ3/PORT B3 CS3/IRQ4/PORT B4 CS2 , controller , a serial module, and two timers. The processor communicates with these modules over the on-chip , or DMA controller and memory, peripherals, or other processing elements in the external address


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PDF MC68340/D MC68340 MC68340V MC68340 32-bit M68000-compatible CPU32 M68300 MC68000 MC68010 MC68020 MC68302 MC68340V space qualified synthesizer, 48 bits MC68332
2012 - M3-5H

Abstract: No abstract text available
Text: LC79401KNE latches 80 bits of display data sent from a controller using a 4-bit parallel transfer technique , DI1 to DI4, CP, LOAD, CDI , R/L, M, DISPOFF DI1 to DI4, CP, LOAD, CDI , R/L, M, DISPOFF CP CP LOAD DI1 , *7 Input capacitance CI Conditions VIN=VDD, LOAD, CP, CDI , R/L, DI1 to DI4, M, DISPOFF VIN=VSS, LOAD, CP, CDI , R/L, DI1 to DI4, M, DISPOFF IOH=-400A, CDO IOL=400A, CDO VDD-VEE=30V, VDE-VO=0.5V: O1 to O80 , 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CDI V1 V3 V4


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PDF ENA1419 LC79401KNE LC79401KNE 80-outputs LC79430KNE QIP100E) A1419-8/8 M3-5H
cdi schematics pcb

Abstract: SAP1024B AVANT SAP1024B dc cdi schematic diagram cdi schematics SCN6400G LQFP100 footprint lqfp100 weight LC7980 cp639
Text: or serial interface with a controller for display data. · Capability of being cascaded in , (5 bits) Serial/Parallel Chip Disable & Latch Control Control CDO CDI CP LOAD , V1 M DI1 DI2 DI3 SDI/DI4 LOAD CDI CP 81 82 83 84 85 86 87 88 89 90 91 92 93 , 56 55 54 53 52 51 CP CDI LOAD SDI/DI4 DI3 DI2 DI1 M V1 VDD NC V3 V4 VEE VSS P/S , Table 3 for output voltage level. Chip Disable pin. 99 82 CDI Input When CDI=High


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PDF SCN0080G 80-Segment SCN6400G cdi schematics pcb SAP1024B AVANT SAP1024B dc cdi schematic diagram cdi schematics LQFP100 footprint lqfp100 weight LC7980 cp639
1995 - M68000PM

Abstract: M68300 MC68000 MC68010 MC68020 MC68302 MC68340 MC68340V DRAM Controller for the MC68340
Text: TWO-CHANNEL DMA CONTROLLER TIMER MODULE TIMER MODULE Figure 1. MC68340 Simplified Block Diagram , · Two-Channel Low-Latency DMA Controller for High-Speed Memory Transfers - Single- or Dual-Address , TWO-CHANNEL DMA CONTROLLER IRQ7/PORT B7 IRQ6/PORT B6 IRQ5/PORT B5 IRQ3/PORT B3 CS3/IRQ4/PORT B4 CS2 , controller , a serial module, and two timers. The processor communicates with these modules over the on-chip , or DMA controller and memory, peripherals, or other processing elements in the external address


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PDF MC68340/D MC68340 MC68340V MC68340 32-bit M68000-compatible CPU32 M68000PM M68300 MC68000 MC68010 MC68020 MC68302 MC68340V DRAM Controller for the MC68340
DR12

Abstract: DR14 MC68341 MCD251FU MCD251
Text: imaging technology to cost sensitive computer, communications and consumer applications, e.g. CD­i , patent right to use this IC in any Mdeo­CD application. CD-i is a registered trademark of Philips , time stamp data are sent directly to the system controller . The video data input also recognizes the video staticodes and passes them on to the system controller . The data sorter and dequantizer takes , controller controls all other functions, reading and interpreting their status and issuing commands. q


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PDF MCD251 MCD251/D. MCD251 MK145BP, MCD251TS/D DR12 DR14 MC68341 MCD251FU
Not Available

Abstract: No abstract text available
Text: Dhrystones/Second • Two-Channel Low-Latency DMA Controller for High-Speed Memory Transfers — Single- or , ARBITRATION RMC TWO-CHANNEL DMA CONTROLLER TIMER MODULE TIMER MODULE 111 h 5 O Jâ , controller , a serial module, and two timers. The processor communicates with these modules over the on-chip , or DMA controller and memory, peripherals, or other processing elements in the external address , characteristic is the high-speed 32-bit DMA controller , used to quickly move large blocks of data between


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PDF MC68340/D MC68340 MC68340V MC68340 32-bit M68000-compatible CPU32
rtd 2486

Abstract: YM6063 YM6063B TC9200 YAMAHA RA 200 cdi wiring diagram yamaha 68000 ADPCM NEC make dc cdi hr/rtd 2486
Text: YAMAHA L S I YM6063B CD- I Data Controller (CDC ) OUTLINE The CDC ( CD-I Data Controller ) is a data processor capable of handling data from both CD-I and CD-ROM sources. This receives data read out from a CD-I disk and detects the synchronous pattern, then descrambles the data and puts it in a buffer , . It is also possible to create a compact CD-I system configuration by using this together with the YM6064 (ADP) and YM7302 (MPC). FEATURES · · · Capacity to handle either CD-I or CD-ROM. Real time errors


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PDF YM6063B YM6064 YM7302 CA95112 3K-0305 rtd 2486 YM6063 YM6063B TC9200 YAMAHA RA 200 cdi wiring diagram yamaha 68000 ADPCM NEC make dc cdi hr/rtd 2486
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