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Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
CD54AC153F3A Texas Instruments Dual 4-Input Multiplexers 16-CDIP -55 to 125
CD54AC257F3A Texas Instruments Quad Non-Inverting 2-Input Multiplexers with 3-State Outputs 16-CDIP -55 to 125
CD54AC574F3A Texas Instruments Non-Inverting Octal D-Type Flip-Flops with 3-State Outputs 20-CDIP -55 to 125
CD54ACT138F3A Texas Instruments 3-Line to 8-Line Inverting Decoders/Demultiplexers 16-CDIP -55 to 125
CD54ACT283F3A Texas Instruments 4-Bit Binary Full Adder with Fast Carry 16-CDIP -55 to 125
CD54ACT573F3A Texas Instruments Non-Inverting Octal Transparent Latch with 3-State Outputs 20-CDIP -55 to 125

CD54/74HCXXXX-S Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
ir1253

Abstract: 74hc273 ov534 cd401068 74hct273 AN6525 cd401106 Harris CMOS Integrated Circuits CV7030 AN7323
Text: .1-47 _l O < E oc < UJ s Z oc ui o o u. Logic Ordering Information HC/HCTHigh Speed CMOS and AC/ACT , Mount SOIC H - Chip SM - Plastic Shrink SOIC (SSOP) JO < t OC < UJ S te UJ o O LL FCT Nomenclature , , Three-State (B Side), Open-Drain (A Side) 20 2358 I S ui z 111 1-9 Logic Selection Guide CD4000 Series Data , 954 CD4043B CMOS Quad Three-State FVS Latch 16 956 CD4044B CMOS Quad Three-State R/ S Latch 16 956 , /74HC73, CD54/74HCT73 RESET ■DATA -CLOCK' SET RESET DATA -CLOCK - Sff 10 2 R 3 F/F1 »CP S 7 13


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PDF CD4000 ir1253 74hc273 ov534 cd401068 74hct273 AN6525 cd401106 Harris CMOS Integrated Circuits CV7030 AN7323
HC 4053 M

Abstract: ic hc 4053 cd 4053 M t4051 pin diagram of ic 74hc4052 hc 4051 4053
Text: ) Low crosstalk between sw itches · Fast s w itching and propagation speeds » "B rea k-be fore -m a , C Alternate Source is P hilips/ S ignetics CD 54H C /C D 74HC Types: 2 to 6 V O peration, con trol , o gic C om p atibility IV = 0.8 V Max., Vih = 2 V Min. CMOS Inp ut C om p atibility l , S 1 f i A @ , /74HC4053, CD54/74HCT4053 A CHANNELS IN/OUT s C H A N N E L .^0 0 IN/OUT I 2 ( S 2- COM OUT/IN Br - , C Bn COM OUTJih A" C3M OUTilN COM OUT/IN Cn - IN/OUT CO A1 > f :hannel I- ve - GNO - S 1


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PDF CD54/74HC4051, CD54/74HCT4051 CD54/74HC4052, CD54/74HCT4052 CD54/74HC4053, CD54/74HCT4053 CD54/74HC/HCT4051 CD54/74H T4051, HC 4053 M ic hc 4053 cd 4053 M t4051 pin diagram of ic 74hc4052 hc 4051 4053
4352H

Abstract: SS74HC tla 3683 74hct4352
Text: itches Fast s w itc h in g and p ro p a g a tio n speeds "B re a k-before-m ake " sw itch in g G N O- 10 C D 54/74H C /H C T4351 TER M IN A L A S SIG NM EN T The RCA C D 54/74H C /H C T4351,4352, and 4353 are dig ita lly co n tro lle d analog sw itches w h ic h u tilize s ilic o n -g a te CMOS te ch n o lo g y to achieve o p eratin g speeds s im ila r to LSTTL w ith th e lo w p o w e r c o n s u m p tio n o f s ta n d a rd C M O S integrated circuits. These analog m u ltip le x e rs /d e m u


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PDF CD54/74HC4351, CD54/74HCT4351 CD54/74HC4352, CD54/74HCT4352 CD54/74HC4353, CD54/74HCT4353 92CS- 54/74H T43C/HC T4353 4352H SS74HC tla 3683 74hct4352
74hct4518

Abstract: 24201B 74HC 4518 74HC-HCT4518 BCD counter 74HCT4518
Text: /HCT4520 - Binary Type Features: P o s it iv e o r N e g a t i v e E d g e T r i g g e r i n g S y n c h ro n o u s In te rn a l C a rry P ro p a g a tio n 9 2 C 5 - 3B 4 0 9 RI FU N C T IO N A L D , independent internally synchronous 4-stage counters. The counter stages are D -type flip -flo p s having , (E s u ffix ), and in 16-lead surface m ount p lastic d u a l-in -lin e packages (M suffix). The C D , Transition Times S ignificant Pow er R eduction Com pared to LSTTL Logic ICs A lternate Source is P hilips


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PDF CD54/74HC4518, CD54/74HCT4518 CD54/74HC4520, CD54/74HCT4520 CD54/74HC/HCT4518 CD54/74HC/HCT4520 CD54/74HC4518 74hct4518 24201B 74HC 4518 74HC-HCT4518 BCD counter 74HCT4518
74hc191

Abstract: No abstract text available
Text: Semiconductor SCHS275 In st r u m e n t s 1SÍ 1M01 9\ ASYN, PARALLEL LOAO ENABLE 11 H C/HC T190 HC/HCT191 , ENABLE -02 BCO (tdO) BINARY (191» OUTPUTS 5 4 03 J TERMINAL COUNT_ RtPPLE CLOCK 92C S , (Over Temperature Range): S tandard O utputs - 10 LSTTL Loads Bus D river O utputs - 15 LSTTL Loads , Transition Times S ig n ifica n t Pow er R eduction Com pared to LSTTL Logic ICs A lternate Source is P hilips/ S ignetics C D54HC/CD74HC Types: 2 to 6 V Operation H igh Noise Im m unity: N,L = 30%, N,H = 30


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PDF CD54/74HC190, CD54/74HCT190 CD54/74HC191, CD54/74HCT191 SCHS275 HC/HCT191 38520R CD54/74HC/HCT190 CD54/74HC/HCT191 74hc191
74AC323

Abstract: No abstract text available
Text: Technical Data n ÿ Te x a s In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SC H S288 CD54/74AC299, CD54/74AC323 CD54/74ACT299, CD54/74ACT323 S O -Ô Ë Ï -Q £ 2 -| / 0 6 -I/O « -i/ o 2 - l/ 0 0 00 MR 1 2 0 - v c c 19 - ie w s 1 2 3 4 5 6 7 B 9 10 - 0 S 7 -0 7 I/O 7 I/O 5 8-Input Universal Shift/Storage Register with , SCR-Latchup-resistant CMOS process and circuit design m Speed o f bipolar FAST` /A S / S with significantly reduced pow


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PDF CD54/74AC299, CD54/74AC323 CD54/74ACT299, CD54/74ACT323 CD54/74AC/ACT299 CD54/74AC/ACT323 74AC323
Not Available

Abstract: No abstract text available
Text: FCT Interface Logic HARRIS S E M I C O N D U C T O R HARRIS RCA GE INTERSIL , transparent latches use a small-geometry B iC M O S technology. The output stage is a combination of bipolar and C M O S transistors that limits the output-HIGH level to two diode drops below V CC. This , and circuit design m FCTXXXA - Speed of bipolar FAST*/AS/ S ; FCTXXXBT - 30% taster than FAST/AS/ S , trademark of Fairchild Semiconductor Corp. FUNCTION T A B L E S OUT­ PUTS INPUTS CLR OE LE


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PDF CD54/74FCT843A, CD54/74FCT843BT CD54/74FCT844A, CD54/74FCT844BT CD54/74FCT843BT CD54/74FCT844BT FCT843A) 54/74FCT843A,
pin diagram of ic 74163

Abstract: CD74HCT160 IC 74160 decade counter diagram
Text: /HCT163 M A X I M U M R A T I N G S , A b s o lu t e - M a x im u m V a lu e s : D C S U P P L Y -V O L T A G E , (Vcc): (V o lta g e s re fe re n ce d to g r o u n d , ) :. ± 5 0 m A POW ER DIS S IP A TIO N PER PACKAG E (PD): F or T a = -40 to +60° C (PAC KAG E TYPE E , S O LD E R IN G ): A t d is ta n c e 1/16 ± 1/32 in. (1.59 ± 0.79 m m ) fro m case fo r 10 s m a x . +26 5°C U n it in se rte d in to a PC B o a rd (m in . th ic k n e s s 1/16 in., 1.59 m m ) w ith


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PDF CD54/74HC/HCT160, CD54/74HC/HCT161 CD54/74HC/HCT162, CD54/74HC/HCT163 D54/74H CT160 CT162 54/74H pin diagram of ic 74163 CD74HCT160 IC 74160 decade counter diagram
Not Available

Abstract: No abstract text available
Text: 33 H June 1998 A R R IS S E M I C O N D U C T O R Technical Data CD54/74AC653, CD54 , CLOCKS |c b A C L O C K c t n n i & r (SAB SOURCE S E LE C TIO N IS B A SOURCE IN PU TS PIN 24 = Vc c , s , and co n tro l c irc u itry arranged fo r m ultiplexed transm ission of data dire ctly from the , n tro l the transceiver fu n ctio n s . SAB and SBA co ntro l pins are provided to select w hether , fo llo w in g exam ples dem onstrate the fo u r fundam ental bus-m anagem ent fu n c tio n s that can


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PDF CD54/74AC653, CD54/74AC654 CD54/74ACT653, C054/74ACT654 CD54/74AC/ACT653 CD54/74AC/ACT654 CD54/74AC653 CD54/74ACT653 CD54/74ACT654
rca 1967

Abstract: 74AC112
Text: circuit design m Speed of bipolar FAST'/AS/ S with significantly reduced power consumption m Balanced , OUTPUTS S R CP J K a Q L X X X H L H L X X X L H L L X X X H* H' H H L L L H H H —r H L TOGGLE H H L H NO CHANGE H H H H H L H H L X X NO CHANGE •Unpredictable and unstable condition if both S , -«0J4I CD54/74AC/ACT112 FUNCTIONAL DIAGRAM INPUTS OUTPUTS S R CP J K a a L H X X X H L H L, X X X L H L L , states unpredictable if S and R go High simultaneously alter both being Low at the same time. H = High


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PDF CD54/74AC109, CD54/74AC1à CD54/74ACT109, CD54/74ACT112 SCHS282 92cs-3sà CD54/74AC/ACT109 CD54/74AC/ACT112 CD54/74AC109 rca 1967 74AC112
ACT540

Abstract: No abstract text available
Text: process and circuit design · Speed o f bipolar FAST&/AS/ S with significantly reduced power consumption m , lines ' hA S T is a R e g is te re d T ra d em a rk o f F a irc h ild S e m ic o n d u c to r Corp , 0.79 mm) from case for 10 s maximum . , /dv at 1.5 V to 3 V (AC Types) at 3.6 V to 5.5 V (AC Types) at 4.5 V to 5.5 V (ACT Types) 'U n le s s o th e rw is e s pec ified , all v o ltag e s a re re fe re n c e d to g ro u n d . TERMINAL


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PDF CD54/74AC540, CD54/74AC541 CD54/74ACT540, CD54/74ACT541 C/ACT541 RCA-CD54/74AC540, CD54/74AC/ACT540 CD54/74AC/ACT541 CD74AC540, ACT540
74FCT244AT

Abstract: 74fct240 74fct241 74fct244
Text: 2 3 HARRIS S E M I C O N D U C T O R February 1996 CD54/74FCT240, CD54/74FCT240AT, CD54 , FCTXXX Types - Speed of Bipolar FASTO/AS/ S ; FCTXXXAT Types - 30% Faster Than FAST/AS/ S with Significantly , ). 500mW For TA = » +70°C to + 1 25°C (PACKAGE TYPE S M ). Derate Linearly at 6.6mW/°C to 135mW OPERATING-TEMPERATURE RANGE (TA): PACKAGE TYPE E ,M , S M , CD54/74FCT540, CD54/74FCT540AT, CD54/74FCT241, CD54/74FCT244, CD54/74FCT244AT S w itch in g S p


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PDF CD54/74FCT240, CD54/74FCT240AT, CD54/74FCT241, CD54/74FCT244, CD54/74FCT244AT 240AT, 244AT 700-MHz FCT240 74FCT244AT 74fct240 74fct241 74fct244
Not Available

Abstract: No abstract text available
Text: HARRIS SEMICOND SECTOR 37E D l 4302271 002SM47 7 H H A S · ' , A S - Z Z - O Z PO P1 P 2 PS Synchronous Presettable Binary Counters - QO -13-01 -Ü .0 2 03 J lr c OHO* 9 Vcc*'* C D 54 / 74 A C /A C T 161 A s yn ch ro n o u s R eset C D 54 / 74 A C /A C T 163 · S y n c h ro n o u s Reset SPÎ - « -2 sra - pe - w -JS . ·2 C S - J T 9 9 ( * I , SCR-Latchup-resistant CMOS process and circuit design m Speed o f bipolar FAST'/AS/ S with significantly reduced power


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PDF 002SM47 CD54/74AC161, CD54/74AC163 CD54/74ACT161, CD54/74ACT163 CD54/74AC161 CD54/74ACT161 CD54/74ACT163 92CS-38928R2
ic hc 4053

Abstract: No abstract text available
Text: n ce : 70 C i t y p ( l/cc" I/ee = 4 .5 V) 4 0 n ty p ( V cc- V e e = 9 V) ■L o w c ro s s ta lk b e tw e e n s w itc h e s ■Fa st s w itc h in g a n d p ro p a g a tio n sp ee d s • " B re a k -b e fo re -m a k e " s w itc h in g T h e R C A C D 5 4 /7 4 H C /H C T 4 0 5 1 , 4052, and 4053 are d ig i­ ta lly c o n tro lle d a n a lo g s w itc h e s w h ic h u tiliz e s ilic o n -g a te C M O S te c h n o lo g y to a ch ie ve o p e ra tin g sp e e d s s im ila r to L S T T L w


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PDF CD54/74HC4051, CD54/74HCT4051 CD54/74HC4052, CD54/74HCT4052 CD54/74HC4053, CD54/74HCT4053 CD54/74HC/HCT4051 ic hc 4053
4510 bcd up down binary counter

Abstract: 4516 PIN DIAGRAM
Text: /74HCT4516 57E D B 4302271 ODlTRtb 2 B H A S HARRIS SEMICON]) SECTOR High-Speed CMOS Logic jn \5 - , DIAGRAM S yn ch ro n o u s c o u n tin g an d a syn chron ous lo a d in g Look-ah ead c a rry to r h ig , r s y n c h ro n o u s ly clocked D -typ e flip -flo p s (w ith a ga ting s tru c tu re to provide T , r advances up o r dow n on each p o s itive -go ing c lo c k tra n s itio n . S ynchronou s casca , rry -O u t o f a less s ig n ific a n t stage to the C a rry -ln o f a m ore s ig n ific a n t stage


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PDF CD54/74HC4510, CD54/74HCT4510 CD54/74HC4516, CD54/74HCT4516 D54/74H T4510 T4516 54/74H 4510 bcd up down binary counter 4516 PIN DIAGRAM
CD54AC157

Abstract: CD54ACT157
Text: four bits of data from two sources under the control of a commonselect input ( S ). The Enable input (E , SCR-LalChup-resistant CMOS process and circuit design m Speed Of bipolar FAST&/AS/ S with significantly reduced power , Output Enable Input Inputs 157 158 E S lo Ii Y Y H X X X L H L L L X L H L L H X H L L H X L L H L H X H H L I6 I5 vcc T S Ho I z I4 "Io II I 3 lì «Il TT A l2 4i 2in 5 H JI0 6 I0 2? _7_ 9 2 Y , s Unit inserted into PC board min. thickness 1/16


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PDF SCHS283 CD54/74AC157, CD54/74AC158 CD54/74ACT157, GD54/74ACT158 AC/ACT157 AC/ACT158 AC/ACT158) CD54AC157 CD54ACT157
74fct241

Abstract: 74fCT244at
Text: CD74FCT240AT and CD74FCT244AT were not acquired from Harris Semiconductor. J /j _ In s t r u m I nts Data sheet acquired from Harris Semiconductor SCHS270A CD54/74FCT240, CD54/74FCT240AT, CD54/74FCT241, CD54/74FCT244, CD54/74FCT244AT FCT Interface Logic Octal Buffers/Line Drivers , BiCMOS Process and Circuit Design · FCTXXX Types - Speed of Bipolar FAST®/AS/ S ; FCTXXXAT Types - 30% Faster Than FAST/AS/ S with Significantly Reduced Power Consumption · 48mA to 64mA Output Sink Current


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PDF CD74FCT240AT CD74FCT244AT SCHS270A CD54/74FCT240, CD54/74FCT240AT, CD54/74FCT241, CD54/74FCT244, CD54/74FCT244AT 240AT, 74fct241 74fCT244at
s3885

Abstract: No abstract text available
Text: : File N um ber 1665 P o s itiv e o r N e g a tiv e E d g e T r ig g e r in g S y n c h r o n o u s , internally synchronous 4-stage counters. The cou nter stages are D -type flip -flo p s having interchangeable , Temperature Range: C D 74H C /H C T: -40 to +85'C B alanced P ropagation D elay and Transition Times S ignifican t Pow er R eduction Com pared to LSTTL Lo gic ICs A lternate Source is P hilips/ S ignetics · C D , IN A L A S S IG N M E N T 580 Technical Data CD54/74HC4518, CD54/74HCT4518 CD54/74HC4520


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PDF CD54/74HC4518, CD54/74HCT4518 CD54/74HC4520, CD54/74HCT4520 CD54/74HC/HCT4518 D54/74HC/HCT4520 92CS-304O9RI CD54/74HC4518 s3885
74hct354

Abstract: No abstract text available
Text: alanced Propagation Delay and Transition Times · S ignifican t Pow er R eduction Compared to LSTTL Logic ICs mA lternate Source is P hilips/ S ignetics · C D 54HC/CD74HC Types: 2 to 6 V Operation H igh Noise , - 1 * iis - X 2 1 s ? - Ü 10 GND - * E fo r 354 C P fo r 356 W3Í TE R M IN A L A S SIG N M EN T 370 Technical Data CD54/74HC354, CD54/74HCT354 CD54/74HC356, CD54 , ost recent lo w -to -h ig h tra n sitio n o f data co ntro l or c lo ck _ # T his co lum n show s the


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PDF CD54/74HC354, CD54/74HCT354 CD54/74HC356, CD54/74HCT356 CDS4/74HC/HCT354 C054/74HC/HCT356 54/74HC 54/74H 74hct354
ACT540

Abstract: ACT541 J406 74AC540 “RCA H 541” 74ACT541
Text: &/AS/ S with significantly reduced power consumption m Balanced propagation delays m AC types feature , ) from case for 10 S maximum.+265"C Unit inserted into PC board min , (IPHL. IPLHI 2 VccllPLZ. IPZL). (OPEN DRAIN) O OUT CL S 500 n • 50 pF ? rL 92CM-4240J •FOR AC SERIES ONLY: WHEN VCC = I S V. RL1 kfl Fig 1 - Simultaneous switching transient waveforms. Fig. 2 -


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PDF CD54/74AC540, CD54/74AC541 CD54/74ACT540, CD54/74ACT541 4240a SCHS285 CD74AC/ACT540 AC/ACT541 RCA-CD54/74AC540, ACT540 ACT541 J406 74AC540 “RCA H 541” 74ACT541
74FCT245TP

Abstract: 74fct563
Text: Family 1 .0 - SMHz Q U IE S C E N T £ 0 .9 - O 0 .5 - O 0.8ta i a 0.7M o.ez SC 0 .4 jj[ 0 .3 - 2 0. 2 0.1 - oL F -T T L B C T - BICM O S F C T -C M O S Fig. 79 C o m p a ris o n o f p o w e r c o n s u m p tio n fo r a n o c ta l tra n s c e iv e r type , case for 10 s maximum .+265°C Unit , Fig. 61 - P ro p a g a tio n d e la y tim es. Fig. 83 - S e tu p , h o ld , a n d re m o v a


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PDF 21-slot CD54/74FCT240 CD54/74FCT374 CD54/74FCT244 CD54/74FCT533 CD54/74FCT245 CD54/74FCT534 CD54/74FCT373 74FCT245TP 74fct563
Not Available

Abstract: No abstract text available
Text: HARRIS S E M I C O N D U C T O R RCA BE HARRIS INTERSIL FCT Interface Logic CD54/74FCT647 , - OE DIR FUP - S CAB CLOCK FLOP \ CBA CUOCK - CLOCKS ' BO B1 B2 B B3 L DATA B* PORT BS B« B7 DATA i , tranceivers/registers use a small-geometry B iC M O S technology. The output stage Is a combination of bipolar and C M O S transistors that limits the output-HIGH level to two diode drops below VCC. This resultant , transceivers with D-type flip-flops which act a s internal storage registers on the LO W -to-H iG H transition


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PDF CD54/74FCT647, CD54/74FCT647AT CD54/74FCT649, CD54/74FCT649AT 80UHCE1 54/74FC D54/74FCT649, D54/7 T649A
Not Available

Abstract: No abstract text available
Text: Technical Data Tf x a s In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SC , -883, Method 3015 m SCR-Latchup-resistant CMOS process and circuit design m Speed o f bipolar FAST'/AS/ S with , Corp. CD54/74AC/ACT109 TRUTH TABLE INPUTS S L H L H H H H H R H L L H H H H H L CP X X X _ /~ -T , ` Unpredictable and unstable condition if both S and R go high simultaneously. T his d ata sheet is applicable to th e C D 54/74A C 109, C D 54AC 112, C D 45A C T 109, and C D 5 4 A C T 112. S ee S


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PDF CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 CD54/74AC/ACT109 CD54/74AC/ACT112 CS-36532 CD54/74AC109
S-42S62

Abstract: cq54
Text: Non-Inverting Outputs CD54/74AC/ACT258 - Inverting Outputs 92C S -42S62 FU N CTIONAL DIAGRAM Type , selects fo u r bits o f data from tw o sources under the control o f a com m on Select input ( S >. The O , -55 to +125°C tempera ture range. Family Features: Exceeds 2-kV E S D P rotection - MIL-STD-883, M ethod 3015 m SCR-Latch-up-resistant CMOS process and circuit design m Speed o f bipo lar FA S T'/A S ! S w ith significantly reduced po w e r consum ption m Balanced propagation delays AC types


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PDF CD54/74AC257, CD54/74AC258 CD54/74ACT257, CD54/74ACT258 CD54/74AC/ACT257 CD54/74AC/ACT258 S-42S62 54/74AC257 CD54/74ACT257 S-42S62 cq54
Not Available

Abstract: No abstract text available
Text: P fC A B CLO CK -CLOCKS \ C B A CLOCK - DATA 2 fS A B SOURCESOURCE 22 s e l e c t io n I s b a s o u r c e INPUTS " 8 0 -*^B1 -*- B2 B3 B DATA PORT Octal-Bus Transceiver/Registers , GND = -I2 VCC = 2 4 9 2 C S -3 8 5 2 9 R 1 FUNCTIONAL DIAGRAM Type Features: Buffered inputs m , process and circuit design m Speed o f bipolar FAST'/AS/ S with significantly reduced pow er consum ption m , -ohm transmission lines 'F A S T is a R e g is te r e d T ra d e m a rk o f F a ir c h ild S e m ic o n d u c t o r


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PDF CD54/74AC646, CD54/74AC648 CD54/74ACT646, CD54/74ACT648 CD54/74AC/ACT646 CD54/74AC/ACT648 CD54/74AC646 CD54/74ACT646 CD54/)
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