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TMS320C6712DGDP150 TMS320C6712DGDP150 ECAD Model Texas Instruments Floating-Point Digital Signal Processors 272-BGA 0 to 90 Visit Texas Instruments Buy
SM32C6712DGDPA16EP SM32C6712DGDPA16EP ECAD Model Texas Instruments Enhanced Product Floating-Point Dsp 272-BGA -40 to 105 Visit Texas Instruments Buy
TMS320C6712DZDP150 TMS320C6712DZDP150 ECAD Model Texas Instruments Floating-Point Digital Signal Processors 272-BGA 0 to 90 Visit Texas Instruments Buy
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Texas Instruments
TMS320C6712GFN100 IC FLOATING POINT DSP 256-BGA
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SM32C6712DGDPA16EP IC DSP FLOATING-POINT 272-BGA
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TMS320C6712CGDP150 DIGITAL SIGNAL PROCESSOR, 32-BIT
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TMS320C6712DZDP150 IC DSP FLOATING POINT 272-BGA
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TMS320C6712DGDP150 IC DSP FLOATING POINT 272-BGA
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Rochester Electronics LLC
SM32C6712DGDPA16EP SM320C6712D-EP ENHANCED PRODUCT
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TMS320C6712DGDP150 TMS320, DIGITAL SIGNAL PROCESSOR
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TMS320C6712DZDP150 TMS320, DIGITAL SIGNAL PROCESSOR
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Texas Instruments
TMS320C6712CGDP150 TMS320C6712 - Digital Signal Processors, Floating Point, 32-Bit Size, 16-Ext Bit, 149.25MHz, PBGA272
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C6712 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2000 - Architecture of TMS320C67X

Abstract: 272-pin BGA drawing
Text: /Cache (L2) 0x0202 100 10 ns ( C6712-100 ) 1.8 3.3 Bypass (x1), x4 - 0x0203 150 6.7 ns ( C6712D-150 ) 6.7 ns , (GFN Suffix) [ C6712 Only] 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffix) [ C6712C / C6712D , / C6712D ) - 0.18-µm/5-Level Metal Process ( C6712 ) 3.3-V I/Os, 1.20-V Internal ( C6712C / C6712D ) 3.3-V I/Os , relating to the C6712 , C6712C , and C6712D devices, have been incorporated. All devices are now at the , ADDITIONS/CHANGES/DELETIONS Mechanical Data for C6712 / C6712C / C6712D section: Deleted the "GFN (S-PBGA-N256


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PDF TMS320C6712, TMS320C6712C, TMS320C6712D SPRS148K TMS320C67x C6712C, C6712D) 32-Bit 150-MHz Architecture of TMS320C67X 272-pin BGA drawing
2000 - 8284 clock generator

Abstract: pin configuration 1K variable resistor pin diagram of Dual core cpu S-PBGA-N272 pad 8284 pin diagram DSP/BIOS example code Programmable PLL Clock Generator x10 frequency multiplier 272-PIN TMS320C6000
Text: , their individual full device part numbers will be used or abbreviated as C6712 or C6712C. 4 POST , MHz Cycle Time ns 0x0202 0x0203 100 150 Voltage 10 ns ( C6712-100 ) 6.7 ns ( C6712C-150 ) Core (V) 1.8 1.26 I/O (V) 3.3 3.3 PLL Options CLKIN frequency , [ C6712 ] Flexible Software-Configurable PLL-Based Clock Generator Module [ C6712C ] A Dedicated , 0.18-µm/5-Level Metal Process ( C6712 ) 3.3-V I/Os, 1.26-V Internal ( C6712C ) 3.3-V I/Os, 1.8-V Internal


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PDF TMS320C6712, TMS320C6712C SPRS148D TMS320C67x TMS320C6712C) 32-Bit 150-MHz 32-Bit 8284 clock generator pin configuration 1K variable resistor pin diagram of Dual core cpu S-PBGA-N272 pad 8284 pin diagram DSP/BIOS example code Programmable PLL Clock Generator x10 frequency multiplier 272-PIN TMS320C6000
2004 - SM320C6712D-EP

Abstract: No abstract text available
Text: (x1), x4 - 256-Pin BGA (GFN) 0.18 µm PP 0x0203 167 6 ns ( C6712D-167 ) 6 ns ( C6712C-167 ) 1.20 3.3 - /1 , ( C6712C / C6712D ) - 0.18-µm/5-Level Metal Process ( C6712 ) D D D D D D D D D D D D , family in the TMS320C6000 DSP platform. The C6712 , C6712C , and C6712D devices are based on the , second (MMACS). The C6712 / C6712C / C6712D uses a two-level cache-based architecture and has a powerful and , includes a dedicated general-purpose input/output (GPIO) peripheral module. The C6712 / C6712C / C6712D DSPs


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PDF SM320C6712EP, SM320C6712CEP, SM320C6712DEP SGUS055 320C67x SM320C6712, C6712C, C6712D) 32-Bit 167-MHz SM320C6712D-EP
2000 - Not Available

Abstract: No abstract text available
Text: will be used or abbreviated as C6712 or C6712C. 4 POST OFFICE BOX 1443 · HOUSTON, TEXAS , Data (L1D) Cache 64KB Unified Mapped RAM/Cache (L2) 0x0202 100 10 ns ( C6712-100 ) 1.8 3.3 Bypass (x1), x4 - 256-Pin BGA (GFN) 0.18 µm PD 0x0203 150 6.7 ns ( C6712C-150 ) 1.26 3.3 ­ /1, /2, /3, ., /32 x4 , ) Clock Generator [ C6712 ] Flexible Software-Configurable PLL-Based Clock Generator Module [ C6712C ] A , -µm/5-Level Metal Process ( C6712 ) 3.3-V I/Os, 1.26-V Internal ( C6712C ) 3.3-V I/Os, 1.8-V Internal ( C6712


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PDF TMS320C6712, TMS320C6712C SPRS148D TMS320C67x TMS320C6712C) 32-Bit 150-MHz TMS320C67x
2000 - C6711 DSP kit

Abstract: TMS320C6711 DSK module SPRZ168 SPRA429 TMS320C6201 DSP starter kit SPRU401 TMS320C6711 DSK kit circuit diagram SPRU258 programming tms320c6000 TMS320 DSP kit circuit diagram
Text: the C6712. Those blocks in dark gray are shared between the C6701, C6711, and C6712. Those blocks in white are shared between the C6211, C6711, and C6712. Those blocks in light gray are shared between all , utilize the HPI will require almost no modification to use on the C6712. The EMIF CE Space Control , C6712. The 32-bit memory type is no longer available on the C6712 , thus EMIF CE Space Control Register , C6712. The identical architectures of the C6211, C6711, and C6712 devices allow for many system-level


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PDF SPRA693 TMS320C6712 C6000 C6712 C6711 TMS320C6000TM C6000TM C6711 DSP kit TMS320C6711 DSK module SPRZ168 SPRA429 TMS320C6201 DSP starter kit SPRU401 TMS320C6711 DSK kit circuit diagram SPRU258 programming tms320c6000 TMS320 DSP kit circuit diagram
2000 - S-PBGA-N272

Abstract: TMS320C6712 TMS320C6712C TMS320C6712D
Text: ( C6712D-150 ) 6.7 ns ( C6712C-150 ) Core (V) Voltage 0x0202 1.8 1.20 I/O (V) 3.3 3.3 , ) [ C6712 Only] 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffix) [ C6712C / C6712D Only , -µm/5-Level Metal Process ( C6712 ) 3.3-V I/Os, 1.20-V Internal ( C6712C / C6712D ) 3.3-V I/Os, 1.8 , 4 ADDITIONS/CHANGES/DELETIONS Mechanical Data for C6712 / C6712C / C6712D section: Deleted the "GFN , TMS320C6000 DSP platform. The C6712 , C6712C , and C6712D devices are based on the high-performance, advanced


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PDF TMS320C6712, TMS320C6712C, TMS320C6712D SPRS148K TMS320C67x C6712C, C6712D) 32-Bit 150-MHz S-PBGA-N272 TMS320C6712 TMS320C6712C TMS320C6712D
2000 - en 4004

Abstract: No abstract text available
Text: /Cache (L2) 0x0202 100 10 ns ( C6712-100 ) 1.8 3.3 Bypass (x1), x4 - 0x0203 150 6.7 ns ( C6712D-150 ) 6.7 ns , (GFN Suffix) [ C6712 Only] 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffix) [ C6712C / C6712D , / C6712D ) - 0.18-µm/5-Level Metal Process ( C6712 ) 3.3-V I/Os, 1.20-V Internal ( C6712C / C6712D ) 3.3-V I/Os , relating to the C6712 , C6712C , and C6712D devices, have been incorporated. All devices are now at the , ADDITIONS/CHANGES/DELETIONS Mechanical Data for C6712 / C6712C / C6712D section: Deleted the "GFN (S-PBGA-N256


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PDF TMS320C6712, TMS320C6712C, TMS320C6712D SPRS148K TMS320C67x C6712C, C6712D) 32-Bit 150-MHz en 4004
2000 - Not Available

Abstract: No abstract text available
Text: /Cache (L2) 0x0202 100 10 ns ( C6712-100 ) 1.8 3.3 Bypass (x1), x4 - 0x0203 150 6.7 ns ( C6712D-150 ) 6.7 ns , (GFN Suffix) [ C6712 Only] 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffix) [ C6712C / C6712D , / C6712D ) - 0.18-µm/5-Level Metal Process ( C6712 ) 3.3-V I/Os, 1.20-V Internal ( C6712C / C6712D ) 3.3-V I/Os , relating to the C6712 , C6712C , and C6712D devices, have been incorporated. All devices are now at the , ADDITIONS/CHANGES/DELETIONS Mechanical Data for C6712 / C6712C / C6712D section: Deleted the "GFN (S-PBGA-N256


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PDF TMS320C6712, TMS320C6712C, TMS320C6712D SPRS148K TMS320C67x C6712C, C6712D) 32-Bit 150-MHz
2000 - Not Available

Abstract: No abstract text available
Text: 4KB L1 Data (L1D) Cache 64KB Unified Mapped RAM/Cache (L2) 0x0202 100 10 ns ( C6712-100 ) 1.8 3.3 Bypass (x1), x4 - 0x0203 150 6.7 ns ( C6712C-150 ) 1.20 3.3 - /1, /2, /3, ., /32 x4, x5, x6, ., x25 /1, /2 , , and C6711D devices have a 32-bit EMIF, while the C6712 , C6712C , and C6712D devices have a 16-bit EMIF , , C6712C , and C6712D devices do not. D The C6712 , C6712C , and C6712D devices have dedicated device , supports Big Endian mode. D The C6712 / C6712C / C6712D is the lowest-cost entry in the TMS320C6000 platform


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PDF TMS320C6712, TMS320C6712C SPRS148K TMS320C67x TMS320C6712 C6712C) 32-Bit 150-MHz
2004 - TMS320C6713 kit

Abstract: SM320C6712D-EP application of dsp tms320c6713
Text: (x1), x4 - 256-Pin BGA (GFN) 0.18 µm PP 0x0203 167 6 ns ( C6712D-167 ) 6 ns ( C6712C-167 ) 1.20 3.3 - /1 , ( C6712C / C6712D ) - 0.18-µm/5-Level Metal Process ( C6712 ) D D D D D D D D D D D D , family in the TMS320C6000 DSP platform. The C6712 , C6712C , and C6712D devices are based on the , second (MMACS). The C6712 / C6712C / C6712D uses a two-level cache-based architecture and has a powerful and , includes a dedicated general-purpose input/output (GPIO) peripheral module. The C6712 / C6712C / C6712D DSPs


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PDF SM320C6712EP, SM320C6712CEP, SM320C6712DEP SGUS055 320C67x SM320C6712, C6712C, C6712D) 32-Bit 167-MHz TMS320C6713 kit SM320C6712D-EP application of dsp tms320c6713
2000 - PANASONIC ECR

Abstract: No abstract text available
Text: will be used or abbreviated as C6712 or C6712C. 4 POST OFFICE BOX 1443 · HOUSTON, TEXAS , Data (L1D) Cache 64KB Unified Mapped RAM/Cache (L2) 0x0202 100 10 ns ( C6712-100 ) 1.8 3.3 Bypass (x1), x4 - 256-Pin BGA (GFN) 0.18 µm PD 0x0203 150 6.7 ns ( C6712C-150 ) 1.26 3.3 - /1, /2, /3, ., /32 x4 , ) Clock Generator [ C6712 ] Flexible Software-Configurable PLL-Based Clock Generator Module [ C6712C ] A , -µm/5-Level Metal Process ( C6712 ) 3.3-V I/Os, 1.26-V Internal ( C6712C ) 3.3-V I/Os, 1.8-V Internal ( C6712


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PDF TMS320C6712, TMS320C6712C SPRS148F TMS320C67x TMS320C6712C) 32-Bit 150-MHz PANASONIC ECR
2000 - TMS320C6712

Abstract: TMS320C6712C TMS320C6712D
Text: ( C6712-100 ) 6.7 ns ( C6712D-150 ) 6.7 ns ( C6712C-150 ) 1.8 1.20 Core (V) I/O (V) 3.3 3.3 , ) [ C6712 Only] 272-Pin Ball Grid Array (BGA) Package (GDP Suffix) [ C6712C / C6712D Only] CMOS Technology - 0.13-µm/6-Level Copper Metal Process ( C6712C / C6712D ) - 0.18-µm/5-Level Metal Process ( C6712 ) 3.3-V I/Os, 1.20-V Internal ( C6712C / C6712D ) 3.3-V I/Os, 1.8-V Internal ( C6712 ) Please be aware , timing [ C6712 ] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 reset timing [ C6712C / C6712D


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PDF TMS320C6712, TMS320C6712C, TMS320C6712D SPRS148J TMS320C67x C6712C, C6712D) 32-Bit 150-MHz TMS320C6712 TMS320C6712C TMS320C6712D
2000 - INT08

Abstract: 272-PIN TMS320C6000 TMS320C6712 TMS320C6712C
Text: ( C6712-100 ) 6.7 ns ( C6712C-150 ) Core (V) 1.8 1.26 I/O (V) 3.3 3.3 PLL Options , or abbreviated as C6712 or C6712C. 4 POST OFFICE BOX 1443 · HOUSTON, TEXAS 77251­1443 , [ C6712 ] Flexible Software-Configurable PLL-Based Clock Generator Module [ C6712C ] A Dedicated , 0.18-µm/5-Level Metal Process ( C6712 ) 3.3-V I/Os, 1.26-V Internal ( C6712C ) 3.3-V I/Os, 1.8-V Internal , interrupt selector [ C6712 only] . . . . 38 interrupt sources and interrupt selector [ C6712C only] . . . 39


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PDF TMS320C6712, TMS320C6712C SPRS148E TMS320C67x TMS320C6712C) 32-Bit 150-MHz 32-Bit INT08 272-PIN TMS320C6000 TMS320C6712 TMS320C6712C
2000 - Not Available

Abstract: No abstract text available
Text: /Cache (L2) 0x0202 100 10 ns ( C6712-100 ) 1.8 3.3 Bypass (x1), x4 - 0x0203 150 6.7 ns ( C6712D-150 ) 6.7 ns , (GFN Suffix) [ C6712 Only] 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffix) [ C6712C / C6712D , / C6712D ) - 0.18-µm/5-Level Metal Process ( C6712 ) 3.3-V I/Os, 1.20-V Internal ( C6712C / C6712D ) 3.3-V I/Os , relating to the C6712 , C6712C , and C6712D devices, have been incorporated. All devices are now at the , ADDITIONS/CHANGES/DELETIONS Mechanical Data for C6712 / C6712C / C6712D section: Deleted the "GFN (S-PBGA-N256


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PDF TMS320C6712, TMS320C6712C, TMS320C6712D SPRS148K TMS320C67x C6712C, C6712D) 32-Bit 150-MHz
2000 - 0X01A

Abstract: No abstract text available
Text: /Cache (L2) 0x0202 100 10 ns ( C6712-100 ) 1.8 3.3 Bypass (x1), x4 - 0x0203 150 6.7 ns ( C6712D-150 ) 6.7 ns , (GFN Suffix) [ C6712 Only] 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffix) [ C6712C / C6712D , / C6712D ) - 0.18-µm/5-Level Metal Process ( C6712 ) 3.3-V I/Os, 1.20-V Internal ( C6712C / C6712D ) 3.3-V I/Os , relating to the C6712 , C6712C , and C6712D devices, have been incorporated. All devices are now at the , ADDITIONS/CHANGES/DELETIONS Mechanical Data for C6712 / C6712C / C6712D section: Deleted the "GFN (S-PBGA-N256


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PDF TMS320C6712, TMS320C6712C, TMS320C6712D SPRS148K TMS320C67x C6712C, C6712D) 32-Bit 150-MHz 0X01A
2000 - Not Available

Abstract: No abstract text available
Text: ) 1.8 3.3 Bypass (x1), x4 - 256-Pin BGA (GFN) 0.18 µm PD 0x0203 150 6.7 ns ( C6712D-150 ) 6.7 ns ( C6712C-150 , (GFN Suffix) [ C6712 Only] 272-Pin Ball Grid Array (BGA) Package (GDP Suffix) [ C6712C / C6712D Only] CMOS Technology - 0.13-µm/6-Level Copper Metal Process ( C6712C / C6712D ) - 0.18-µm/5-Level Metal Process ( C6712 ) 3.3-V I/Os, 1.26-V Internal ( C6712C / C6712D ) 3.3-V I/Os, 1.8-V Internal ( C6712 ) D D D D D D D D D , of the floating-point DSP family in the TMS320C6000 DSP platform. The C6712 , C6712C , and C6712D


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PDF TMS320C6712, TMS320C6712C, TMS320C6712D SPRS148I TMS320C67x C6712C, C6712D) 32-Bit 150-MHz
2004 - datasheet TMS320 C6713

Abstract: SM320C6712D-EP
Text: 100 167 10 ns ( C6712-100 ) 6 ns ( C6712D-167 ) 6 ns ( C6712C-167 ) Core (V) Voltage 0x0202 , Process ( C6712C / C6712D ) - 0.18-µm/5-Level Metal Process ( C6712 ) Please be aware that an important , members of the floating-point DSP family in the TMS320C6000 DSP platform. The C6712 , C6712C , and C6712D , million MACs per second (MMACS). The C6712 / C6712C / C6712D uses a two-level cache-based architecture and , . The C6712 / C6712C / C6712D DSPs also have application-specific hardware logic, on-chip memory, and


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PDF SM320C6712EP, SM320C6712CEP, SM320C6712DEP SGUS055 320C67x SM320C6712, C6712C, C6712D) 32-Bit 167-MHz datasheet TMS320 C6713 SM320C6712D-EP
2004 - SM320C6712D-EP

Abstract: No abstract text available
Text: (x1), x4 - 256-Pin BGA (GFN) 0.18 µm PP 0x0203 167 6 ns ( C6712D-167 ) 6 ns ( C6712C-167 ) 1.20 3.3 - /1 , ( C6712C / C6712D ) - 0.18-µm/5-Level Metal Process ( C6712 ) D D D D D D D D D D D D , family in the TMS320C6000 DSP platform. The C6712 , C6712C , and C6712D devices are based on the , second (MMACS). The C6712 / C6712C / C6712D uses a two-level cache-based architecture and has a powerful and , includes a dedicated general-purpose input/output (GPIO) peripheral module. The C6712 / C6712C / C6712D DSPs


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PDF SM320C6712EP, SM320C6712CEP, SM320C6712DEP SGUS055 320C67x SM320C6712, C6712C, C6712D) 32-Bit 167-MHz SM320C6712D-EP
2005 - SPRU233

Abstract: C6000 TMS320C6712 TMS320C6712C TMS320C6712D C6712C C6212 eken c6712D
Text: C6712. This pin must be connected to GROUND on the C6712D. 2 Migrating from TMS320C6712/ C6712C to , . Migration issues from C6712 and C6712C to C6712D are indicated with the following symbols, which are , /software modification is required. [D] Means the C6712 , C6712C , and C6712D are different (usually due to , following sections detail differences you must address when migrating from the C6712 device to C6712D. , not exist on the C6712D. The D7 pin that is the CLKOUT1 pin on the C6712 now becomes a reserved


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PDF SPRA852F TMS320C6712/C6712C TMS320C6712D C6000 TMS320C6712 TMS320C6712C C6712 C6712C C6712D SPRU233 TMS320C6712D C6212 eken
2004 - C6000

Abstract: TMS320C6712 TMS320C6712C TMS320C6712D
Text: . Migration issues from C6712 and C6712C to C6712D are indicated with the following symbols, which are , /software modification is required. [D] Means the C6712 , C6712C , and C6712D are different (usually due to , following sections detail differences you must address when migrating from the C6712 device to C6712D. , The D7 pin that is the CLKOUT1 pin on the C6712 now becomes a reserved, no-connect pin on the C6712D. , connected to GROUND on the C6712D. 2 Migrating from TMS320C6712/ C6712C to TMS320C6712D SPRA852E


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PDF SPRA852E TMS320C6712/C6712C TMS320C6712D C6000 TMS320C6712 TMS320C6712C C6712 C6712C C6712D TMS320C6712D
2000 - Not Available

Abstract: No abstract text available
Text: /Cache (L2) 0x0202 100 10 ns ( C6712-100 ) 1.8 3.3 Bypass (x1), x4 - 0x0203 150 6.7 ns ( C6712D-150 ) 6.7 ns , (GFN Suffix) [ C6712 Only] 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffix) [ C6712C / C6712D , / C6712D ) - 0.18-µm/5-Level Metal Process ( C6712 ) 3.3-V I/Os, 1.20-V Internal ( C6712C / C6712D ) 3.3-V I/Os , relating to the C6712 , C6712C , and C6712D devices, have been incorporated. All devices are now at the , ADDITIONS/CHANGES/DELETIONS Mechanical Data for C6712 / C6712C / C6712D section: Deleted the "GFN (S-PBGA-N256


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PDF TMS320C6712, TMS320C6712C, TMS320C6712D SPRS148K TMS320C67x C6712C, C6712D) 32-Bit 150-MHz
2000 - Not Available

Abstract: No abstract text available
Text: ) 1.8 3.3 Bypass (x1), x4 - 256-Pin BGA (GFN) 0.18 µm PD 0x0203 150 6.7 ns ( C6712D-150 ) 6.7 ns ( C6712C-150 , (GFN Suffix) [ C6712 Only] 272-Pin Ball Grid Array (BGA) Package (GDP Suffix) [ C6712C / C6712D Only] CMOS Technology - 0.13-µm/6-Level Copper Metal Process ( C6712C / C6712D ) - 0.18-µm/5-Level Metal Process ( C6712 ) 3.3-V I/Os, 1.26-V Internal ( C6712C / C6712D ) 3.3-V I/Os, 1.8-V Internal ( C6712 ) D D D D D D D D D , of the floating-point DSP family in the TMS320C6000 DSP platform. The C6712 , C6712C , and C6712D


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PDF TMS320C6712, TMS320C6712C, TMS320C6712D SPRS148H TMS320C67x C6712C, C6712D) 32-Bit 150-MHz
2004 - SM320C6712D-EP

Abstract: No abstract text available
Text: 100 167 10 ns ( C6712-100 ) 6 ns ( C6712D-167 ) 6 ns ( C6712C-167 ) Core (V) Voltage 0x0202 , Process ( C6712C / C6712D ) - 0.18-µm/5-Level Metal Process ( C6712 ) Please be aware that an important , members of the floating-point DSP family in the TMS320C6000 DSP platform. The C6712 , C6712C , and C6712D , million MACs per second (MMACS). The C6712 / C6712C / C6712D uses a two-level cache-based architecture and , . The C6712 / C6712C / C6712D DSPs also have application-specific hardware logic, on-chip memory, and


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PDF SM320C6712EP, SM320C6712CEP, SM320C6712DEP SGUS055 320C67x SM320C6712, C6712C, C6712D) 32-Bit 167-MHz SM320C6712D-EP
2004 - SM320C6712D-EP

Abstract: No abstract text available
Text: (x1), x4 - 256-Pin BGA (GFN) 0.18 µm PP 0x0203 167 6 ns ( C6712D-167 ) 6 ns ( C6712C-167 ) 1.20 3.3 - /1 , ( C6712C / C6712D ) - 0.18-µm/5-Level Metal Process ( C6712 ) D D D D D D D D D D D D , family in the TMS320C6000 DSP platform. The C6712 , C6712C , and C6712D devices are based on the , second (MMACS). The C6712 / C6712C / C6712D uses a two-level cache-based architecture and has a powerful and , includes a dedicated general-purpose input/output (GPIO) peripheral module. The C6712 / C6712C / C6712D DSPs


Original
PDF SM320C6712EP, SM320C6712CEP, SM320C6712DEP SGUS055 320C67x SM320C6712, C6712C, C6712D) 32-Bit 167-MHz SM320C6712D-EP
2000 - Not Available

Abstract: No abstract text available
Text: floating-point DSP family in the TMS320C6000™ DSP platform. The C6712 , C6712C and C6712D devices are based on , MHz Cycle Time ns 0x0202 0x0203 100 150 10 ns ( C6712-100 ) Core (V) Voltage 1.8 6.7 ns ( C6712C-150 ) 1.20†I/O (V) 3.3 3.3 PLL Options CLKIN frequency , TMS320C62x™ DSP core (CPU), while the C6711, C6711B, C6711C, C6711D, C6712 , C6712C , and C6712D devices have , a 32-bit EMIF, while the C6712 , C6712C , and C6712D devices have a 16-bit EMIF. D The C6211


Original
PDF TMS320C6712, TMS320C6712C SPRS148M TMS320C67xâ TMS320C6712 C6712C) 32-Bit 150-MHz 32-Bit
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