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TP3070V-G/63 Texas Instruments IC PROGRAMMABLE CODEC, Codec
TLC32040MFK Texas Instruments PCM CODEC, CQCC28
TLC32044IFN Texas Instruments PCM CODEC, PQCC28
TLC32041IFN Texas Instruments PCM CODEC, PQCC28
TLC32041CFNR Texas Instruments PCM CODEC, PQCC28
TLC32044IFNR Texas Instruments PCM CODEC, PQCC28

Biphase decoder Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
Biphase decoder

Abstract: BPSK demodulator bpsk modulation and demodulation XTAL 38khz RDS decoder S1A0905X01 digital clock and carrier recovery RDS Radio IC bpsk demodulator circuit 16-SOP-225
Text: Clock Recovery Circuit · Biphase Decoder & Differential Decoder · Quality Indication Output , Clock Recovery PLL 1.1875kHz VSS BPSK CLKO Recovered clock VREF Biphase Decoder VDDA BGR BIAS VSSA COMP 2 QUAL(High or Low) Differential Decoder DATAO 20pF , carrier recovery circuit, a bit rate clock recovery circuit, BPSK decoder , differential decoding circuit


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PDF S1A0905 16-SOP-225 DCF-77 57kHz. 1875kbit/sec. 1875kbit/sec, S1A0905X01 Biphase decoder BPSK demodulator bpsk modulation and demodulation XTAL 38khz RDS decoder S1A0905X01 digital clock and carrier recovery RDS Radio IC bpsk demodulator circuit 16-SOP-225
Biphase decoder

Abstract: MPC1346CS P24GM-50-300B-1
Text: , bit-rate-clock playback circuit, DSB demodulator circuit, bi-phase PSK decoder , differential decoding circuit , Integration F ilte r Pin Band Pass F ilte r f c A djustm ent Biphase Signal O u tp u t Pin Biphase Decoder In , BIPHASE DECODER SK DET CLOCK RECOVERY OSC DEF. DECODER 0.01 //F Ï s a ~ |2 2 pF


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PDF b427SES uPC1346 24PIN S24C-70-300B Biphase decoder MPC1346CS P24GM-50-300B-1
PLL pSK DEMODULATOR

Abstract: Biphase decoder 565 PLL pin diagram 57KHz
Text: 57KHz PLL, BI-PHASE PSK decoder , differential decoding circuit, ARI in dication and RDS signal quality , BIPHASE DECODER - 1 D IF F . i 13 DECODER ·RDDA X -L 15 14 ARI QUAL TI 19 TEST , signal (RDDA) and clock signal (RDCL) can be further processed by a suitable RDS decoder (microprocessor , npxiN 2?0pF Bth ORDER S C "BANDPASS FILTER 14pF PLL 5?KHz OSCILLATOR b OIUIDER r~ BIPHASE DECODER 19 TEST LOGIC IS 14 AR] QUAL T 1 T3 T4 T2 T57 20 RDDA Ï . TM POD GND FILOUT -L


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PDF A7330B 57KHz 332MHz 664MHz TDA7330B PLL pSK DEMODULATOR Biphase decoder 565 PLL pin diagram
2000 - Biphase decoder

Abstract: bandpassfilter
Text: 20 19 18 17 16 15 14 13 57kHz BPF COSTAS SK DET BIPHASE DECODER DIFFERENTIAL DECODER 1 2 3 CLOCK RECOVERY 4 5 6 OSC 7 8 9 10 11 12 , 16 15 14 13 57kHz BPF COSTAS SK DET BIPHASE DECODER DIFFERENTIAL DECODER 1


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PDF PC2539 PC2539 57kHz PC2539GS 24-pin Biphase decoder bandpassfilter
2008 - Biphase decoder

Abstract: FSK remote control transmitter circuit CODER MANCHESTER DIFFERENTIAL PMA5110 embedded 8051 ask rf remote decoder ASK transmitter 125 KHz antenna 125khz TSSOP-38 Biphase
Text: Peripherals: " Manchester/ Biphase Coder/ Decoder , " CRC Unit " Pseudo Random Number Generator " Watchdog , FSK deviation up to 100kHz ! LF 125kHz ASK Receiver " Manchester/ Biphase Decoder " data rate from


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PDF PMA5110 PMA5110 TSSOP-38 PMA5110- Biphase decoder FSK remote control transmitter circuit CODER MANCHESTER DIFFERENTIAL embedded 8051 ask rf remote decoder ASK transmitter 125 KHz antenna 125khz Biphase
Not Available

Abstract: No abstract text available
Text: 57KHz PLL, BI-PHASE PSK decoder , differential decoding circuit, ARI in dication and RDS signal quality , 14pF 1 L !27pF 1 C5 PLL 5?KHz 1 BIPHASE DECODER IFF. DECODER 13 RDDA Ï . IS iA GND , PLL 5?KHz RECOUERY PLL 1 .1875KHz BIPHASE DECODER - 1 DIFF. i 13 'RDDft DECODER , decoder (microprocessor). The device operates in accordance with the EBU (European Broadcasting Union , clock edge is used by the decoder (ris ing or falling edge) the data will remain valid for 416.7 (isec


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PDF 57KHz 332MHz 664MHz TDA7330B
1999 - mobile phone basic block diagram

Abstract: 74HC151
Text: -172 DSTi C4o F0o Extracted 4Mb/s Clock Clock Extractor DNIC Framer Bi-Phase Coder Bi-Phase Coder DSTi C4i Extracted 4Mb/s Clock F0i Clock Extractor DSTo FIFO Bi-Phase Decoder Bi-Phase Decoder DNIC Framer Extracted Frame Position FIFO DSTo RxSB Extracted Frame Position MT9172


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PDF MSAN-172 MT9173/74 MT9174 mobile phone basic block diagram 74HC151
2000 - Biphase decoder

Abstract: No abstract text available
Text: 18 17 16 15 14 13 57kHz BPF COSTAS SK DET BIPHASE DECODER DIFFERENTIAL DECODER 1 2 3 CLOCK RECOVERY 4 5 6 OSC 7 8 9 10 11 12 The , 16 15 14 13 57kHz BPF COSTAS SK DET BIPHASE DECODER DIFFERENTIAL DECODER 1


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Biphase decoder

Abstract: tda7330 sk 753 RDS modulator
Text: , BI-PHASE PSK decoder , differential decoding cir cuit, ARI identification and signal quality outputs. BLOCK DIAGRAM C3 lO G n F Ucc H h _ MPXIN · 2?0pF COSTAS LOOP PLL 57KHZ 1 BIPHASE DECODER CLOCK RECOUERV PLL 1 ·1075KHz - 1 I IFF. DECODER O ^RDDfl 15 14 May 1991 This is advanced


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PDF TDA7330 -77-C 57KHz TDA7330 57KHz) -40dB Biphase decoder sk 753 RDS modulator
565 PLL pin diagram

Abstract: PLL IC 565 PLL pSK DEMODULATOR rds decoder 57KHz h/RDS decoder TDA7331D TDA7331 S020 DIP20
Text: 57KHz PLL, BI-PHASE PSK decoder , differential decoding circuit, ARI indication and RDS signal quality , * CHRYSTPlL TYPE - EURO QUARTZ F5EL -Ç- PLL 57KHz BIPHASE DECODER □ n/a f f OSCILLATOR & DIU[DER CLOCK RECOUERY PLL 1.1875KHz zr DIFF, DECODER TEST LOGIC QUAL NC NC NC NC Tb? 'T* □SCOUT 27pFà , decoder (microprocessor). BLOCK DIAGRAM The device operates in accordance with the EBU (European , by the decoder (rising or falling edge) the data will remain valid for 416.7 |jsec after the clock


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PDF TDA7331 57KHz 332MHz 328MHz DIP20 TDA7331 TDA7331D 565 PLL pin diagram PLL IC 565 PLL pSK DEMODULATOR rds decoder h/RDS decoder TDA7331D S020 DIP20
2002 - BU1924F

Abstract: BU1924
Text: VDD2 (12) 2 QUAL (6) Digital Power supply PLL 57kHZ RDS/ARI Bi-phase decoder PLL 1187.5Hz Differential decoder (2) RDATA (11) VSS2 Measurement circuit , BU1924 / BU1924F Audio ICs RDS / RBDS decoder BU1924 / BU1924F The BU1924 and BU1924F are RDS / RBDS decoders that employ a digital PLL and have a built-in anti-aliasing filter and an eight-stage BPF (switched-capacitor filter). Linear CMOS circuitry is used for low power consumption


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PDF BU1924 BU1924F BU1924F 57kHz BU1924
BU1922

Abstract: BU1922F 560PF 565 PLL pin diagram DSB 717
Text: 4.332MHz HIH 777 777 Bi-phase decoder Comparator RCLK QUAL Differential decoder TEST CIRCUIT T1 T2 RDATA , Audio ICs RDS/RBDS decoder BU1922/BU1922F The BU1922 and BU1922F are RDS/RBDS decoders that employ a digital PLL. They have a built-in anti-aliasing filter and an eight-stage BDF (switched-capacitor filter). Linear CMOS circuitry is used for low power consumption. •Applications RDS/RBDS compatible FM receivers for Europe and North America, car stereo systems, home stereo systems and FM pagers. •Features 1


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PDF BU1922/BU1922F BU1922 BU1922F 57kHz Vdd2BU1922F BU1922/BU1922F 560PF 565 PLL pin diagram DSB 717
2002 - BU1924F

Abstract: BU1924
Text: VDD2 (12) 2 QUAL (6) Digital Power supply PLL 57kHZ RDS/ARI Bi-phase decoder PLL 1187.5Hz Differential decoder (2) RDATA (11) VSS2 Measurement circuit , BU1924 / BU1924F Audio ICs RDS / RBDS decoder BU1924 / BU1924F The BU1924 and BU1924F are RDS / RBDS decoders that employ a digital PLL and have a built-in anti-aliasing filter and an eight-stage BPF (switched-capacitor filter). Linear CMOS circuitry is used for low power consumption


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PDF BU1924 BU1924F BU1924F 57kHz BU1924
2003 - BU1924FS

Abstract: BU1924 BU1924F SSOP-A16
Text: BU1924 / BU1924F / BU1924FS Audio ICs RDS / RBDS decoder BU1924 / BU1924F / BU1924FS The BU1924, BU1924F and BU1924FS are RDS / RBDS decoders that employ a digital PLL and have a built-in anti-aliasing filter and an eight-stage BPF (switched-capacitor filter). Linear CMOS circuitry is used for low , VSS1 VDD2 (12) 2 QUAL (6) Digital Power supply PLL 57kHZ RDS Bi-phase decoder PLL 1187.5Hz Differential decoder (2) RDATA (11) VSS2 Measurement circuit


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PDF BU1924 BU1924F BU1924FS BU1924, BU1924FS 57kHz SSOP-A16
2000 - 1187

Abstract: BU1923 BU1923F 565 PLL pin diagram
Text: Power supply VSS2 (11) PLL 57kHZ RDS/ARI Bi-phase decoder PLL 1187.5Hz Measurement circuit Reference clock (13) (14) XI Differential decoder (10) (9) XO T2 T1 , BU1923 / BU1923F Audio ICs RDS / RBDS decoder BU1923 / BU1923F The BU1923 and BU1923F are RDS / RBDS decoders that employ a digital PLL and have a built-in anti-aliasing filter and an eight-stage BPF (switched-capacitor filter). Linear CMOS circuitry is used for low power consumption


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PDF BU1923 BU1923F BU1923F 57kHz BU1923 1187 565 PLL pin diagram
2000 - F570

Abstract: BU1924F 20filter 565 PLL pin diagram BU1924 PLL IC 565
Text: supply PLL 57kHZ RDS/ARI Bi-phase decoder PLL 1187.5Hz Differential decoder (2 , BU1924 / BU1924F Audio ICs RDS / RBDS decoder BU1924 / BU1924F The BU1924 and BU1924F are RDS / RBDS decoders that employ a digital PLL and have a built-in anti-aliasing filter and an eight-stage BPF (switched-capacitor filter). Linear CMOS circuitry is used for low power consumption. !Applications RDS / RBDS compatible FM receivers for American and European markets, car stereos, high-fidelity


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PDF BU1924 BU1924F BU1924F 57kHz BU1924 F570 20filter 565 PLL pin diagram PLL IC 565
2000 - BU1924F

Abstract: No abstract text available
Text: VDD2 (12) Digital Power supply (11) PLL 57kHZ RDS/ARI PLL 1187.5Hz Bi-phase decoder Differential decoder (2) RDATA 2 VSS2 Reference clock (13) XI 4.332MHZ (14) X0 (10) Measurement , BU1924 / BU1924F Audio ICs RDS / RBDS decoder BU1924 / BU1924F The BU1924 and BU1924F are RDS / RBDS decoders that employ a digital PLL and have a built-in anti-aliasing filter and an eight-stage BPF (switched-capacitor filter). Linear CMOS circuitry is used for low power consumption. zApplications RDS / RBDS


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PDF BU1924 BU1924F BU1924F 57kHz
2001 - MT9174

Abstract: mobile phone basic block diagram 74HC151 74hc574 MSAN-172 MT8980 MT9172 automatic purchase counter system circuit diagram 11-CLEAR
Text: DSTi Bi-Phase Coder Bi-Phase Coder DSTi C4i C4o F0o Extracted 4Mb/s Clock DNIC Framer FIFO DSTo Clock Extractor Clock Extractor Bi-Phase Decoder Bi-Phase Decoder


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PDF MSAN-172 MT9173/74 MT9174 mobile phone basic block diagram 74HC151 74hc574 MSAN-172 MT8980 MT9172 automatic purchase counter system circuit diagram 11-CLEAR
2001 - mobile phone basic block diagram

Abstract: 74HC151 74HC574 MSAN-172 MT8980 MT9172 MT9174
Text: DSTi Bi-Phase Coder Bi-Phase Coder DSTi C4i C4o F0o Extracted 4Mb/s Clock DNIC Framer FIFO DSTo Clock Extractor Clock Extractor Bi-Phase Decoder Bi-Phase Decoder


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PDF MSAN-172 MT9173/74 mobile phone basic block diagram 74HC151 74HC574 MSAN-172 MT8980 MT9172 MT9174
Biphase decoder

Abstract: BUS-1555 manchester Manchester block diagram BUS-63105 BUS-8559
Text: OUT - NRZ RECONSTRUCTED TO SERIAL BIPHASE ~ DECODER SHIFT . CLOCK IDECCKI SVNC TYPE -LOAD PULSE -FRAME , -1555 MIL-STD-1553 MANCHESTER II DECODER FOR TEST EQUIPMENT FEATURES • 16 MHz CLOCK RATE DESCRIPTION AND , -1555 Manchester II Decoder Module avails Itself to a wide range of applications. The decoder is encapsulated in a , Models BUS-63105 and BUS-8559 are directly compatible with this decoder . The BUS-1555 will sample , +5.5V and nominal power dissipation is 2.5 watts. The input is biphase TTL complementary serial data


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PDF 00073b3 BUS-1555 MIL-STD-1553 BUS-63105 BUS-8559 VII-16 Biphase decoder manchester Manchester block diagram
2007 - sc6579a

Abstract: SOP-16-375-1 SC6579S SC6579 SOP-16-225-1
Text: : digital demodulator part can be divided into three parts (PLL, Bi-phase decoder , differential decoder , -16-300-2.54 outputs for further processing by a suitable decoder (microcomputer). FEATURES * Anti-aliasing filter , oscillator with variable dividers * Clock regeneration with lock on bi-phase data rate * Bi-phase symbol decoder with integrate and dump functions * Differential decoder * Signal quality detector ORDERING , signal in form of bi-phase symbols being output from the integrate and dump circuit. The final stages of


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PDF SC6579 SC6579 DIP-16-300-2 OP-16-375-1 OP-16-225-1 sc6579a SOP-16-375-1 SC6579S SOP-16-225-1
Not Available

Abstract: No abstract text available
Text: detector, a bit rate clock recovery circuit, a 57KHz PLL, BI-PHASE PSK decoder , differential decoding , r PLL 5?KHz 27BpF Bth ORDER 5C-BANDPAS3 FILTER BIPHASE DECODER 14pF X -CU­ RA , (RDCL) can be further processed by a suitable RDS decoder (microprocessor). The device operates in , decoder (ris­ ing or falling edge) the data will remain valid for 416.7 usee after the clock transition , DIUIDER UREF ANTIALIAS FILTER — r PLL 5?KHz 2?0pF SC-BANDPASS FILTER biphase


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PDF 57KHz 332MHz 664MHz TDA7330B 007S0S1
SP9960

Abstract: No abstract text available
Text: Biphase Decoder VC C VEE ODE Vee:45 Vee:80 Vee:LD V ee:10 Fig.2 Functional block diagram , pulling the ODE pin low. They are enabled if the ODE pin is left unconnected. Biphase Mark Encoding


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PDF SP9960 50M-BIT SP9960 SP9960AC, MIL-STD-B83
Not Available

Abstract: No abstract text available
Text: GEC PLESSEY ISE MIC ONDUCT OR S | PRELIMINARY INFORMATION 2 1 2 1 - 1.0 SP9921 50 MBIT MANCHESTER BIPHASE DECODER The SP9921 is a bipolar m onolithic silicon integrated circuit for clock and data recovery from a M anchester biphase-m ark encoded signal It operates from a single 5V supply and has ECL outputs. The device is also available as the SP9921AC, which has guaranteed operation over , Biphase Encoder Vcc RXO VEE F ig .2 F u n c tio n a l b lo c k d ia g ra m 3-45 SP9921


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PDF SP9921 SP9921 SP9921AC, MIL-STD-883C 50Mbit/s OuSP9921
Not Available

Abstract: No abstract text available
Text: GEC PLESSEY [ s e m i c o n d u c t o r s | _ PRELIMINARY INFORMATION DS2121-1.0 SP9921 50 MBIT MANCHESTER BIPHASE DECODER The SP9921 is a bipolar m onolithic silicon integrated circuit for clock and data recovery from a M anchester biphase-m ark encoded signal. It operates from a single 5V supply and has ECL outputs. The device is also , plifier SP9960 50M -Bit Manchester Biphase Encoder RCI (TTL l/P) REFF RX + RX - RXO Fig.Z


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PDF DS2121-1 SP9921 SP9921 SP9921AC, MIL-STD-883C 40MBIT/S /77T7
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