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Part Manufacturer Description Datasheet Download Buy Part
LTC2938CMS#PBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: 0°C to 70°C
LTC2939CMS#PBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C
LTC2938CMS#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 12; Temperature Range: 0°C to 70°C
LTC2939CMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C
LTC2938HDE#TRPBF Linear Technology LTC2938 - Configurable 4-Supply Monitors with Watchdog Timer; Package: DFN; Pins: 12; Temperature Range: -40°C to 125°C
LTC2939HMS#TRPBF Linear Technology LTC2939 - Configurable 6-Supply Monitors with Watchdog Timer; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C

BRX 49 SCR PIN CONFIGURATION Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1998 - interrupt in assembly for sharc

Abstract: ASDP-21065L
Text: output pair. The BRx input pin on one processor connects to the BRx output pin on the other. To make , drives the BRx pin that corresponds to its ID1-0 inputs and monitors the other. When the slave , current bus master deasserts its BRx pin · The slave processor asserts its BRx pin By keeping its BRx , its CPA pin and its bus request ( BRx ) pin . CPA is an open-drain output and connects both processors in , processor asserts both its CPA pin and its BRx pin when its core has an external bus access pending. 2


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PDF ADSP-21065L ASDP-21065L interrupt in assembly for sharc
2004 - AN2070

Abstract: emcp
Text: memory bank the type of data error protection must be selected in the BRx [DECC] field. Furthermore, the , example, if BRx [MS] = 001 and BRx [DECC]=10, RMW parity will be generated and checked on the Local Bus). , pin will be asserted as a result of parity errors or ECC fatal errors. The NMI_OUT is automatically , the BRx [DECC] register. If an external memory controller is used and data error protection is required, a memory bank must be defined (using a BRx /ORx register pair) and the bit BRx [EMEMC] must be set


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PDF AN2070 AN2070 emcp
1997 - M-BUS

Abstract: bus arbitration protocol how dsp is used in radar ADSP-21060 ADSP-21062
Text: used equal to the number of ADSP-2106xs in the system. Each processor drives the BRx pin , bus transition cycle. A bus transition cycle occurs when the current bus master's BRx pin is , by keeping its BRx pin asserted. Also, the bus master does not always lose bus mastership when it , bus request pin ( BRx ). CPA is an open-drain output which is connected to all ADSP-2106xs in the , . The core processor of an ADSP-2106x bus slave asserts its CPA pin (with the same timing as BRx ) when


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PDF ADSP-2106x ADSP-2106xs. ADSP-2106xs DATA47-0, ADDR31-0, ADSP-2106x 16-to-48 32-to-48 M-BUS bus arbitration protocol how dsp is used in radar ADSP-21060 ADSP-21062
2004 - AN2176

Abstract: MPC8260 Size16
Text: by clearing the HardResetConfiguration[EBM] bit during the configuration . © Freescale , Access (2) Program ORx for CS and WE timing(1). (3) Program BRx [MS] to select GPCM and appropriate bus, BRx [PS] for port size, etc. Reference: (1) MPC8260 PowerQUICC II User's Manual, P10 , Use the same program except BRx [PS] = 10 to set the port size = 16 bits. Due to port size limitation , Figure 4. GPCM, 60x, Port Size=16, 32-Bit Write, 2 Cycle Wait 1 Use the same program except BRx [PS] =


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PDF AN2176 MPC8260 MPC8260, AN2176 Size16
2013 - AEZE

Abstract: ADSP-21369
Text: SDRAM External Port Pin MUX Peripherals External Port Figure 1. Functional Block Diagram , . 12 208-Lead LQFP_EP Pinout . 57 Pin Function , Related Signal Chains . 12 Corrected EMU pin type from O/T(pu) to O(O/D, pu) in Pin Function Descriptions . 13 Corrected Junction , . 48 Updated Figure 37 in SPI Interface—Slave . 49 Changes to Ordering Guide


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PDF ADSP-21367/ADSP-21368/ADSP-21369 32-bit/40-bit ADSP-21367/ADSP-21368/ADSP-21369 D05267-0-10/13 AEZE ADSP-21369
1998 - CAN BUS

Abstract: ADSP-21160 virpt ADSP-21060
Text: transition cycle. A bus transition cycle occurs when the current bus masters BRx pin is deasserted and one , keeping its BRx pin asserted. Also, the bus master does not always lose bus mastership when it deasserts , determined by the setting of the RPBA pin . Table 10-2 defines the ADSP-21160 pins used in multiprocessing , -21160 only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-21160s, the unused BRx pins should be tied high


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PDF ADSP-21160 ADSP-21160s 75HJLVWHU6WDWXV ADSP-21160) CAN BUS virpt ADSP-21060
2001 - SanDisk compactflash datasheet

Abstract: MPC8260 compact flash 8260 cf 44 pin to ide 1.8 ata commands toshiba service manual 39 pin ide connector compact flash card schematic
Text: are mapped into common memory space (REG# pin = H). When mapped to common memory space, the task , where the card's configuration registers and CIS (card information structure, also known as metaformat , ) The value in the card configuration option register (address 200h in attribute memory space , registers are also mapped into I/O address space. The True IDE mode is selected if the OE# pin (also called , card configuration registers are accessible. Only accesses to the task file registers is possible: ·


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PDF MPC8260 SanDisk compactflash datasheet compact flash 8260 cf 44 pin to ide 1.8 ata commands toshiba service manual 39 pin ide connector compact flash card schematic
1999 - TEA 2029 A

Abstract: MPC8260 MPC860 KM416S1120A
Text: precharge pin Determine the address configuration parameters for this memory. 1. The address , precharge pin Determine the address configuration parameters for this memory. 10 - 38 Exercise - , Controller Pins? (1 of 3) Memory Controller Pin Summary Local or 60x Bus Accesses: · CS[0-11]* - chip select pins · PSDVAL* - data valid pin · BADDR[27-31] - burst address pins 60x Bus Mode Accesses Only , the 60x data bus. Pin Description 1. PSDVAL- Indicates that a beat data transfer completed


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PDF MPC8260 MPC860 CS0-11* 0x28000000; 0xFFFF8000; 0x08000000; 0x18000000; TEA 2029 A KM416S1120A
2001 - MT48LC16M16A2 rev B

Abstract: mclf MPC8XX MT48LC8M16A2 MT48LC *48lc16m16a2 "mpc860 users manual" mpc860 users manual MT48LC8M16A2TG-75 MPC8xx pin
Text: hardware connection scheme can be derived as displayed in Table 2. Note that address pin A19 for the MPC8xx is not connected to the SDRAM. Instead, the pin A10 for the SDRAM is connected to GPL0 on the , SDRAM devices in a 32-bit wide configuration . Diagram 1 MPCxx/SDRAM Hardware Interface BS(0-3) DQ , SDRAMs regardless of the densities and/or configuration . For example, if the design requires two 256Mb , A7 SDRAM/8xx Map 8xx Mux 8xx Pin SDRAM Pin Column A0 A1 A2 A3 A4 A5 A6 A7 A8


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PDF TN-48-12 32-bit 16-bit MT48LC8M16A2 MPC860 TN4812 MT48LC16M16A2 rev B mclf MPC8XX MT48LC *48lc16m16a2 "mpc860 users manual" mpc860 users manual MT48LC8M16A2TG-75 MPC8xx pin
2008 - Not Available

Abstract: No abstract text available
Text: connections between all DAI/DPI components 2 muxed flag/IRQ lines 1 muxed flag/timer expired line /MS pin 1 muxed flag/IRQ /MS pin DEDICATED AUDIO COMPONENTS S/PDIF-compatible digital audio receiver , . 15 Added Automotive Products .55 Pin Function , RPBA pin . Table 5 on Page 12 provides descriptions of the pins used in multiprocessor systems. I/O , peripherals. These include a 20- pin digital applications interface which controls: • Eight serial ports â


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PDF ADSP-21367/ADSP-21368/ADSP-21369 ADSP-21367/ADSP-21368/ADSP-21369 32-bit/40-bit 208-Lead SW-208-1 ADSP-21369KBPZ-2A ADSP-21369BBP-2A ADSP-21369BBPZ-2A ADSP-21369KBPZ-3A3 ADSP-21369KSWZ-1A
2009 - ADSP-21369

Abstract: No abstract text available
Text: SDRAM External Port Pin MUX Peripherals External Port Figure 1. Functional Block Diagram , . 12 256-Ball BGA_ED Pinout . 51 Pin Function , determined by the setting of the RPBA pin . Table 8 on Page 13 provides descriptions of the pins used in , communicate with other SPI-compatible devices. The SPI consists of two data pins, one device select pin , and one clock pin . It is a full-duplex synchronous serial interface, supporting both master and slave


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PDF ADSP-21367/ADSP-21368/ADSP-21369 32-bit/40-bit ADSP-21367/ADSP-21368/ADSP-21369 OrdSP-21369BSWZ-2A3 208-Lead SW-208-1 ADSP-21369BSWZ-1A D05267-0-7/09 ADSP-21369
2004 - MPC8250

Abstract: MPC8260 MPC8260ADS MPC8265 MPC8266 MPC860
Text: the ways toggle the RSTCONF pin to latch the Hard Reset Configuration Word (HRCW) from the data bus , Section 4.3.2.6, "SIU Module Configuration Register (SIUMCR)." 10­11 DPPC1 Data parity pin , Configuration Register (SIUMCR)." Local bus pin configuration . Defines the value of SIUMCR[LBPC]. See Section , 24­25 CS10PC1 26­27 - Address parity pin configuration . Defines the initial value of SIUMCR[APPC]. See Section 4.3.2.6, "SIU Module Configuration Register (SIUMCR)." CS10 pin configuration


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PDF MPC8260ADS AN2450/D MPC8250 MPC8260 MPC8260ADS MPC8265 MPC8266 MPC860
2009 - transistor SMD W06

Abstract: transistor SMD w04 smd w04 74 smd code W06 ADSP-21367BBP-2A2 smd transistor w04 BP MSX 60 JB 2256 W04 SMD SMD Transistor W08
Text: SDRAM External Port Pin MUX Peripherals External Port Figure 1. Functional Block Diagram , . 12 256-Ball BGA_ED Pinout . 51 Pin Function , ­4 signals and the priority scheme for bus arbitration is determined by the setting of the RPBA pin . Table 8 , communicate with other SPI-compatible devices. The SPI consists of two data pins, one device select pin , and one clock pin . It is a full-duplex synchronous serial interface, supporting both master and slave


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PDF ADSP-21367/ADSP-21368/ADSP-21369 32-bit/40-bit ADSP-21367/ADSP-21368/ADSP-21369 OrdeADSP-21369BSWZ-2A3 208-Lead SW-208-1 ADSP-21369BSWZ-1A D05267-0-7/09 transistor SMD W06 transistor SMD w04 smd w04 74 smd code W06 ADSP-21367BBP-2A2 smd transistor w04 BP MSX 60 JB 2256 W04 SMD SMD Transistor W08
2003 - BCR 133 Motorola

Abstract: MPC8250 MPC8260 MPC8260ADS MPC8265 MPC8266 MPC860
Text: (SIUMCR)." 10­11 DPPC1 Data parity pin configuration . Defines the initial value of SIUMCR[DPPC]. , Local bus pin configuration . Defines the value of SIUMCR[LBPC]. See Section 4.3.2.6, "SIU Module , 26­27 - Address parity pin configuration . Defines the initial value of SIUMCR[APPC]. See Section 4.3.2.6, "SIU Module Configuration Register (SIUMCR)." CS10 pin configuration . Defines the initial value , Status Registers (BCSRx) located on the ADS board or the Hard Reset Configuration Word (HRCW) located in


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PDF AN2450/D MPC8260ADS BCR 133 Motorola MPC8250 MPC8260 MPC8260ADS MPC8265 MPC8266 MPC860
2007 - transistor SMD w04

Abstract: smd transistor w04 transistor SMD W06 smd transistor w06 smd w04 74 BP MSX 60 transistor SMD t04 smd transistor w08 smd w04 SMD Transistor W03
Text: bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32 , /IRQ lines 1 muxed flag/timer expired line /MS pin 1 muxed flag/IRQ /MS pin DEDICATED AUDIO , . 7 Revised Table 21, Precision Clock Generator (Direct Pin Routing , ) .47 Additional Information . 11 Pin Function Descriptions , Hold vs. Load Capacitance (at Junction Temperature) . 49 This revision adds 400 MHz


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PDF ADSP-21367/ADSP-21368/ADSP-21369 ADSP-21367/ADSP-21368/ADSP-21369 32-bit/40-bit S-208-2 D05267-0-10/07 transistor SMD w04 smd transistor w04 transistor SMD W06 smd transistor w06 smd w04 74 BP MSX 60 transistor SMD t04 smd transistor w08 smd w04 SMD Transistor W03
1999 - BRX 49 SCR PIN CONFIGURATION

Abstract: PIN SCR BRX 49 SCR BRX 49 PIN IC20B 9pin rs232 4k7 variable resistor st16554 IC19C SCR BRX 49 RS323
Text: Configuration Circuit Configuration Description Unterminated A B B UART PIN A C , RS232 these channels offer all the signals found on a PC AT type 9- pin RS232 port. Similarly, the other two channels (CandD) are configured as RS232, supporting all the signals found on a PC AT type 9- pin , LSR Line Status Register 6 MSR Modem Status Register 7 SCR Scratchpad Register Baud Rate , Links Link Position Diagram User Configuration Diagram Default Shipment Configuration Channel A


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PDF 16-bit 16c550 RS232 RS422 RS485. PC-COM4-RS232) RS422/485 BRX 49 SCR PIN CONFIGURATION PIN SCR BRX 49 SCR BRX 49 PIN IC20B 9pin rs232 4k7 variable resistor st16554 IC19C SCR BRX 49 RS323
2008 - transistor SMD W06

Abstract: transistor SMD w04 smd transistor w06 smd transistor w04 transistor SMD t04 SMD w06 smd code W06 smd transistor w08 smd w04 74 SMD Transistor W03
Text: components 2 muxed flag/IRQ lines 1 muxed flag/timer expired line /MS pin 1 muxed flag/IRQ /MS pin , . 10 Additional Information . 11 Pin Function Descriptions , . 49 208-Lead LQFP_EP Pinout . 52 Package Dimensions , setting of the RPBA pin . Table 5 on Page 12 provides descriptions of the pins used in multiprocessor , set of peripherals. These include a 20- pin digital audio interface which controls: · Eight serial


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PDF ADSP-21367/ADSP-21368/ADSP-21369 ADSP-21367/ADSP-21368/ADSP-21369 32-bit/40-bit 208-Lead SW-208-1 ADSP-21369KBPZ-3A ADSP-21369BSWZ-1A transistor SMD W06 transistor SMD w04 smd transistor w06 smd transistor w04 transistor SMD t04 SMD w06 smd code W06 smd transistor w08 smd w04 74 SMD Transistor W03
MPC565MZP56D

Abstract: MPC565MZP56D device marking MPC565 MPC566 J1850 AR922 TEA 1019 jtag mpc565
Text: CLKOUT periods USIU: Do not enable BRx [SST] with SCCR[EBDF]>0 USIU: Do not assert TEA pin on fetch , not rely on the VDDSRAM Low Voltage Detect Circuit Bit 15 of the Reset Configuration Word is not , the VDDSRAM pin (s) is below the minimum data retention voltage. CDR_AR_912 Customer Information MPC565.D Bit 15 of the Reset Configuration Word is not documented DESCRIPTION: Bit 15 of the Reset Configuration Word is not documented in the Reference Manual


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PDF 32-BIT MPC565 MPC565MZP56D MPC565MZP56D device marking MPC566 J1850 AR922 TEA 1019 jtag mpc565
2006 - transistor SMD BR21

Abstract: SMD Transistor W08 adsp-21369ksz smd w04 74 smd code W06 transistor SMD W06 smd code t04 ADSP-21369 SMD Transistors w06 56 SMD W05
Text: bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32 , connections between all DAI/DPI components 2 muxed flag/IRQ lines 1 muxed flag/timer expired line /MS pin 1 muxed flag/IRQ /MS pin DEDICATED AUDIO COMPONENTS DMA controller supports: 34 zero-overhead DMA , . 11 Pin Function Descriptions . 12 Data Modes , . 48 256-Ball SBGA Pinout . 49 208-Lead MQFP Pinout


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PDF ADSP-21367/ADSP-21368/ADSP-21369 ADSP-21367/ADSP-21368/ADSP-21369 32-bit/40-bit ADSP-21369KSZ-1A2 ADSP-21368BBP-2A 256-Ball BP-256 D05267-0-8/06 transistor SMD BR21 SMD Transistor W08 adsp-21369ksz smd w04 74 smd code W06 transistor SMD W06 smd code t04 ADSP-21369 SMD Transistors w06 56 SMD W05
2000 - BR10

Abstract: MPC8260 PC10 PC11 PC13 PC14 PC15 abb acs 101
Text: with the following: "Local bus pin configuration . Defines the value of SIUMCR[LBPC]. See Section , Description Interrupt Vector 44­47 Reserved 0b10_1100­0b10_1111 48 PC15 0b11_0000 49 , and Table 4-9 , move BCE[EAV] from bit 9 to bit 11; bits 9 and 10 are reserved. 4.3.2.1, 4-27 In Table 4-9 , for EPAR and LEPAR, `0' means odd parity and `1' means even. Also, correct the typo in the fifth row entry of Table 4-9 ; it should be `19­20' not `16­20' that are reserved. 4.3.2.3, 4-29


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PDF MPC8260 MPC603e EC603e MPC8260EC/D BR10 PC10 PC11 PC13 PC14 PC15 abb acs 101
1999 - AWM VW-1

Abstract: MDR 26 pin MINI D ribbon MDR 26 pin 3M MDR 14 pin MDR 26 pin
Text: 26 Position ` Transmitter, TX 26 Position MDR SMT Receptacle 14526-EZ5B-XXX-02C MDR 26 Pin , ARx In Clk gnd 8 19 ATx Out Clk gnd 7 CTL 1 CTL 1 20 CTL 2 7 20 CTL 2 8 BTx Out 0 gnd BRx In 0 gnd 19 BRx In 06 21 BTx Out 09 BTx Out 0+ BRx In 0+ 18 BRx In 1 gnd 5 22 BTx Out 1 gnd , Clk26 BTx Out Clk+ BRx In 1- 17 BRx In 1+ 4 BRx In 2 gnd 16 BRx In 23 BRx In 2+ 15 BRx In Clk gnd 2 BRx In Clk- 14 BRx In Clk+ 1 o Symbols Key: 100 Ohm balanced individually shielded


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PDF 14526-EZ5B-XXX-02C TS-0866-02 Clk26 AWM VW-1 MDR 26 pin MINI D ribbon MDR 26 pin 3M MDR 14 pin MDR 26 pin
2004 - 60x-bus

Abstract: CPM 1 operation manual MPC603E MPC107 MPC8260 bus arbiter
Text: each data structure configuration ). Then, the address is compared with BRx to select a given state , 60x bus. This means that CPM accesses can be snooped (controlled by GBL configuration bit discussed , either the local bus or the 60x bus, depending on a configuration parameter selectable for each single , ( BRx ) MS bit. Refer to Section 10.2 in the MPC8260 PowerQUICC IITM User's Manual. When a transaction , compared for a match in one of BRx . If a match occurs, BRx [MS] selects a state machine (SDRAM, UPM or GPCM


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PDF AN2335/D MPC8260 MPC8260 MPC8265AUMAD/D) 60x-bus CPM 1 operation manual MPC603E MPC107 bus arbiter
csc 9803

Abstract: QML-38534 LA4-DA BMS SYSTEM qualification CE7Y
Text: A A A A A A A A A A A A A A A A A A A SHEET 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 , Identifying Number ( PIN ). When available, a choice of radiation hardness assurance levels are reflected in the PIN . 1.2 PIN . The PIN shall be as shown in the following example: 5962-97507 01 H X C Federal RHA , . MIL-STD-973 - Configuration Management. MIL-STD-1835 - Microcircuit Case Outlines. HANDBOOK DEPARTMENT OF , MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer


OCR Scan
PDF AD14060LBF/QML-4 5962-9750702HXC AD14060LTF/QML-4 csc 9803 QML-38534 LA4-DA BMS SYSTEM qualification CE7Y
2000 - MPC8260

Abstract: Size16
Text: configuration . Under this bus mode, the MPC8260 is the only bus master device in the system. The internal memory , CS and WE timing(1). (3) Program BRx [MS] to select GPCM and appropriate bus, BRx [PS] for port size , wait (1) Use the same program except BRx [PS] = 10 to set the port size = 16 bits. Due to port size , Fig. 1-4 GPCM, 60x, Port Size=16, 32-bit write , 2 cycle wait (1) Use the same program except BRx [PS , is entered by setting the HardResetConfiguration[EBM] bit during the configuration . Under this bus


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PDF MPC8260 MPC8260 MPC8260, Mot-800-441-2447 Size16
2005 - MDR 26 pin 3M

Abstract: MDR 26 pin atx wiring diagram MDR 14 pin MDR 26 pin MINI plug MDR 26 pin MINI D wiring MDR 26 pin plug 14526 MDR26
Text: -02C Transmitter, TX 26 Position MDR SMT Receptacle 1 MDR 26 Pin , Pinout F26-0 Cable Receiver , RX 26 , - 9 ARx In Clk+ 21 ARx In Clk gnd 8 CTL 1 20 CTL 2 7 BRx In 0 gnd 19 BRx In 0- 6 BRx In 0+ 18 BRx In 1 gnd 5 10 BTx Out 1- BRx In 1- 17 23 BTx Out 1+ BRx In 1+ 4 11 BTx Out 2 gnd BRx In 2 gnd 16 24 BTx Out 2- BRx In 2- 12 BTx Out 2+ BRx In 2+ 15 25 BTx Out Clk gnd 3 BRx In Clk gnd 2 13 BTx Out Clk- BRx In Clk- 14 26 BTx Out Clk


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PDF 14526-EZ5B-XXX-02C TS-0866-08 MDR 26 pin 3M MDR 26 pin atx wiring diagram MDR 14 pin MDR 26 pin MINI plug MDR 26 pin MINI D wiring MDR 26 pin plug 14526 MDR26
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