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Part ECAD Model Manufacturer Description Datasheet Download Buy Part
OPA2196IDGKT OPA2196IDGKT ECAD Model Texas Instruments 36V, Low Power, All-Purpose Amplifier with MUX-Friendly Input 8-VSSOP -40 to 125
OPA2196IDGKR OPA2196IDGKR ECAD Model Texas Instruments 36V, Low Power, All-Purpose Amplifier with MUX-Friendly Input 8-VSSOP -40 to 125
OPA196IDGKT OPA196IDGKT ECAD Model Texas Instruments 36V, Low Power, All-Purpose Amplifier with MUX-Friendly Input 8-VSSOP -40 to 125
OPA196IDGKR OPA196IDGKR ECAD Model Texas Instruments 36V, Low Power, All-Purpose Amplifier with MUX-Friendly Input 8-VSSOP -40 to 125
10140957-101LF 10140957-101LF ECAD Model Amphenol Communications Solutions VerIO™ Connector, Input Output Connectors, BulkHead Receptacle for all Interfaces
OPA196ID OPA196ID ECAD Model Texas Instruments 36V, Low Power, All-Purpose Amplifier with MUX-Friendly Input 8-SOIC -40 to 125

BR-05-ALL-002 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
bussmann semiconductor fuse

Abstract: ATc Fuses 1A1907-02 1A4533-01 1A4533-06 1A4533-07 1A4534-01 1A4534-06 1A4534-07 bussmann Fuse
Text: 4.06 .160 5.08 .200 1.57 .062 3.66 .144 2.54Å}. 05 .100Å}. 002 (TYP-4) 5.08 .200 DIA. HOLE MOUNTING LAYOUT 1.65Å}. 05 .065Å}. 002 (TYP-4) 3.66 .144 DIA. HOLE 4.47 .176 , 1.65Å}. 05 .065Å}. 002 (TYP-4) MATERIAL: BRASS, NICKEL PLATED, .30 THICK .012 . BRASS , (3.66) .144" (3.66) .200" ( 5.08) C (4 holes) .065 ± . 002 (1.65 ± . 05 ) .065 ± . 002 (1.65 ± . 05 ) .100 ± . 002 (2.54 ± . 05 ) Board Thickness .062 (1.57) .062 (1.57) .062 (1.57) -


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PDF 1A4534 1A4533 1A4533-07 1A4533-06 1A4534-07 1A4534-06 102ronic SB99168 bussmann semiconductor fuse ATc Fuses 1A1907-02 1A4533-01 1A4533-06 1A4533-07 1A4534-01 1A4534-06 1A4534-07 bussmann Fuse
2004 - 1A1907-02

Abstract: 1A1907-03 1A4533-01 1A4533-06 1A4534-01 1A4534-06 bussmann Fuse
Text: 2.54Å}. 05 .100Å}. 002 (TYP-4) 5.08 .200 DIA. HOLE MOUNTING LAYOUT 1.65Å}. 05 .065Å}. 002 , . . MOUNTING LAYOUT FOR 2 CLIPS BASE MATERIAL 1.65Å}. 05 .065Å}. 002 (TYP-4) MATERIAL , ( 5.08) C (4 holes) .065 ± . 002 (1.65 ± . 05 ) .065 ± . 002 (1.65 ± . 05 ) .100 ± . 002 (2.54 ± . 05 , (20.80 ± .38) - - - - - - - - - .093 ± . 002 (2.36 ± . 05 ) .067 - , .266" (1.5mm) (3.58mm + 0.38mm) (6.75mm) .022" + . 002 " .032" + . 002 " (0.56mm + 0.05mm


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PDF 1A4534 1A4533 1A3398-07 1A4533-06 1A4534-06 1A4533-01 SB04208 1A1907-02 1A1907-03 1A4533-01 1A4533-06 1A4534-01 1A4534-06 bussmann Fuse
2005 - K8D3216UBC-pi07

Abstract: K5E5658HCM KAD070J00M KBH10PD00M K5D1257ACM-D090000 samsung ddr2 ram MTBF KBB05A500A K801716UBC k5d1g13acm k5a3281ctm
Text: 667Mbps BR-05-ALL-002 Voltage: 1.8V Package: FBGA (11x13mm) SAMSUNG SEMICONDUCTOR, INC. 3a , : TSOP components B3 = DDR333 (166MHz @ CL=2.5) Voltage: 2.5V BR-05-ALL-002 Notes CC = , Voltage: 3.3V Speed: PC133 (133MHz CL=3/PC100 CL2) BR-05-ALL-002 SAMSUNG SEMICONDUCTOR, INC. 5a , BR-05-ALL-002 Comments Voltage: 3.3V APRIL 2005 A Section MEMORY AND STORAGE , APRIL 2005 BR-05-ALL-002 SAMSUNG SEMICONDUCTOR, INC. 7a A Section MEMORY AND STORAGE


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PDF BR-05-ALL-002 K8D3216UBC-pi07 K5E5658HCM KAD070J00M KBH10PD00M K5D1257ACM-D090000 samsung ddr2 ram MTBF KBB05A500A K801716UBC k5d1g13acm k5a3281ctm
1998 - 74HC4060

Abstract: 74hct4060 application notes
Text: Oscillator the negative transition of I (and O). All inputs and outputs are buffered. Schmitt trigger action , Reset input is provided which resets the counter to the all -0's state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave , STATE No Change Advance to Next State All Outputs are Low 2 CD54/74HC4060, CD54/74HCT4060 , VIH or VIL - 0.02 - 0.02 - 0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 - 0.02 - 0.02 - 0.02 2 4.5 6 4.5 6 2 4.5 6 4.5


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PDF CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 SCHS207G 14-Stage HCT4060 HC4060; HC406 74HC4060 74hct4060 application notes
1998 - Not Available

Abstract: No abstract text available
Text: Oscillator the negative transition of I (and O). All inputs and outputs are buffered. Schmitt trigger action , Reset input is provided which resets the counter to the all -0's state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave , STATE No Change Advance to Next State All Outputs are Low 2 CD54/74HC4060, CD54/74HCT4060 , VIH or VIL - 0.02 - 0.02 - 0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 - 0.02 - 0.02 - 0.02 2 4.5 6 4.5 6 2 4.5 6 4.5


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PDF CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 SCHS207G 14-Stage HCT4060 HC4060; HC406
1998 - Not Available

Abstract: No abstract text available
Text: Oscillator the negative transition of I (and O). All inputs and outputs are buffered. Schmitt trigger action , Reset input is provided which resets the counter to the all -0's state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave , STATE No Change Advance to Next State All Outputs are Low 2 CD54/74HC4060, CD54/74HCT4060 , VIH or VIL - 0.02 - 0.02 - 0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 - 0.02 - 0.02 - 0.02 2 4.5 6 4.5 6 2 4.5 6 4.5


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PDF CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 SCHS207G 14-Stage HCT4060 HC4060; HC406
1998 - Not Available

Abstract: No abstract text available
Text: Oscillator the negative transition of I (and O). All inputs and outputs are buffered. Schmitt trigger action , Reset input is provided which resets the counter to the all -0's state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave , STATE No Change Advance to Next State All Outputs are Low 2 CD54/74HC4060, CD54/74HCT4060 , VIH or VIL - 0.02 - 0.02 - 0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 - 0.02 - 0.02 - 0.02 2 4.5 6 4.5 6 2 4.5 6 4.5


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PDF CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 SCHS207G 14-Stage HCT4060 HC4060; HC406
1998 - hc4060

Abstract: HC4060 application data
Text: Oscillator the negative transition of I (and O). All inputs and outputs are buffered. Schmitt trigger action , Reset input is provided which resets the counter to the all -0's state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave , STATE No Change Advance to Next State All Outputs are Low 2 CD54/74HC4060, CD54/74HCT4060 , VIH or VIL - 0.02 - 0.02 - 0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 - 0.02 - 0.02 - 0.02 2 4.5 6 4.5 6 2 4.5 6 4.5


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PDF CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 SCHS207G 14-Stage HCT4060 HC4060; HC406 hc4060 HC4060 application data
1998 - Not Available

Abstract: No abstract text available
Text: Oscillator the negative transition of I (and O). All inputs and outputs are buffered. Schmitt trigger action , Reset input is provided which resets the counter to the all -0's state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave , STATE No Change Advance to Next State All Outputs are Low 2 CD54/74HC4060, CD54/74HCT4060 , VIH or VIL - 0.02 - 0.02 - 0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 - 0.02 - 0.02 - 0.02 2 4.5 6 4.5 6 2 4.5 6 4.5


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PDF CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 SCHS207G 14-Stage HCT4060 HC4060; HC406
1998 - Not Available

Abstract: No abstract text available
Text: or VIL - 0.02 - 0.02 - 0.02 VCC or GND VIH or VIL -4 -5.2 0.02 0.02 0.02 4 VCC or GND VCC or GND VCC or , 0.5 0.5 0.26 0.26 ±0.1 2 -40oC TO +85oC MIN 1.7 3.6 4.8 1.8 4 5.5 3.84 5.34 MAX 0.3 0.8 1.1 0.2 0.5 0.5 0.33 0.33 ±1 20 -55oC TO 125oC MIN 1.7 3.6 4.8 1.8 4 5.5 3.7 5.2 MAX 0.3 0.8 1.1 0.2 0.5 0.5 0.4 , products that are compatible with the current RoHS requirements for all 6 substances, including the , Seating Plane 1,20 MAX 0,15 0, 05 0,10 PINS * DIM A MAX 8 14 16 20 24 28 3,10 5


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PDF CD74HCU04 SCHS127D CD74HCU04 HCU04 -55oC 125oC
1998 - CD74HC14M96

Abstract: CD74HC14MT
Text: Level Output Voltage TTL Loads Input Leakage Current II VCC and GND VCC or GND VCC - 2.1 VOL VT+ VOH V T- 0.02 -4 0.02 4 4.5 4.5 4.5 4.5 5.5 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.98 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.26 ±0.1 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.84 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.33 ±1 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.7 , VOH V T- 0.02 - 0.02 - 0.02 High Level Output Voltage TTL Loads -4 -5.2 Low Level Output Voltage CMOS Loads VOL VT+ 0.02 0.02 0.02 Low Level Output Voltage TTL Loads 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 0.7


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PDF CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 SCHS129F HCT14 CD74H -55oC 125oC CD74HC14M96 CD74HC14MT
1998 - 74HC4060 application note

Abstract: No abstract text available
Text: Oscillator the negative transition of I (and O). All inputs and outputs are buffered. Schmitt trigger action , Reset input is provided which resets the counter to the all -0's state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave , STATE No Change Advance to Next State All Outputs are Low 2 CD54/74HC4060, CD54/74HCT4060 , VIH or VIL - 0.02 - 0.02 - 0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 - 0.02 - 0.02 - 0.02 2 4.5 6 4.5 6 2 4.5 6 4.5


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PDF CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 SCHS207G 14-Stage HCT4060 HC4060; HC406 74HC4060 application note
1998 - Not Available

Abstract: No abstract text available
Text: Oscillator the negative transition of I (and O). All inputs and outputs are buffered. Schmitt trigger action , Reset input is provided which resets the counter to the all -0's state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave , STATE No Change Advance to Next State All Outputs are Low 2 CD54/74HC4060, CD54/74HCT4060 , VIH or VIL - 0.02 - 0.02 - 0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 - 0.02 - 0.02 - 0.02 2 4.5 6 4.5 6 2 4.5 6 4.5


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PDF CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 SCHS207G 14-Stage HCT4060 HC4060; HC406
1997 - Not Available

Abstract: No abstract text available
Text: speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All , VCC or GND VOL VIH or VIL VOH VIH or VIL - 0.02 - 0.02 - 0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 , ) specification is 1.8mA. II VCC and GND VCC or GND VCC - 2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL - 0.02 4.5 to


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PDF CD54HC08, CD74HC08, CD54HCT08, CD74HCT08 SCHS118C CD74HCT08 74HCT
1998 - CD74HC14M96

Abstract: No abstract text available
Text: Level Output Voltage TTL Loads Input Leakage Current II VCC and GND VCC or GND VCC - 2.1 VOL VT+ VOH V T- 0.02 -4 0.02 4 4.5 4.5 4.5 4.5 5.5 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.98 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.26 ±0.1 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.84 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.33 ±1 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.7 , VOH V T- 0.02 - 0.02 - 0.02 High Level Output Voltage TTL Loads -4 -5.2 Low Level Output Voltage CMOS Loads VOL VT+ 0.02 0.02 0.02 Low Level Output Voltage TTL Loads 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 0.7


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PDF CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 SCHS129F HCT14 CD74H -55oC 125oC CD74HC14M96
1997 - CD74HC125M96

Abstract: No abstract text available
Text: VIL 2 4.5 6 High Level Output Voltage CMOS Loads VOH VIH or VIL - 0.02 - 0.02 - 0.02 High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL -6 -7.8 0.02 0.02 0.02 Low Level , 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 , VIL or VIH VOL VIH or VIL VIH VIL VOH VIH or VIL - 0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2


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PDF CD54HC125, CD74HC125, CD54HCT125, CD74HCT125 SCHS143C HC125 HCT125 HC125 HCT12 -55oC CD74HC125M96
1998 - HJ4060

Abstract: No abstract text available
Text: Oscillator the negative transition of I (and O). All inputs and outputs are buffered. Schmitt trigger action , Reset input is provided which resets the counter to the all -0's state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave , STATE No Change Advance to Next State All Outputs are Low 2 CD54/74HC4060, CD54/74HCT4060 , VIH or VIL - 0.02 - 0.02 - 0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 - 0.02 - 0.02 - 0.02 2 4.5 6 4.5 6 2 4.5 6 4.5


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PDF CD54HC4060, CD74HC4060, CD54HCT4060, CD74HCT4060 SCHS207G 14-Stage HCT4060 HC4060; HC406 HJ4060
1998 - CD74HC14M96

Abstract: No abstract text available
Text: Level Output Voltage TTL Loads Input Leakage Current II VCC and GND VCC or GND VCC - 2.1 VOL VT+ VOH V T- 0.02 -4 0.02 4 4.5 4.5 4.5 4.5 5.5 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.98 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.26 ±0.1 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.84 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.33 ±1 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.7 , VOH V T- 0.02 - 0.02 - 0.02 High Level Output Voltage TTL Loads -4 -5.2 Low Level Output Voltage CMOS Loads VOL VT+ 0.02 0.02 0.02 Low Level Output Voltage TTL Loads 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 0.7


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PDF CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 SCHS129F HCT14 CD74H -55oC 125oC CD74HC14M96
1997 - Not Available

Abstract: No abstract text available
Text: Three-State Non-Inverting Outputs all other input conditions. Moving data from two groups of registers to , The Output Enable input (OE) is active LOW. When OE is HIGH, all of the outputs (1Y-4Y) are in the , Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads VOH VIH or VIL - 0.02 - 0.02 - 0.02 High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL -6 -7.8 0.02 0.02 0.02 Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND 6 7.8 2 4.5 6 4.5


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PDF CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 SCHS171D HC257 HCT25
1997 - Not Available

Abstract: No abstract text available
Text: speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All , VCC or GND VOL VIH or VIL VOH VIH or VIL - 0.02 - 0.02 - 0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 , ) specification is 1.8mA. II VCC and GND VCC or GND VCC - 2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL - 0.02 4.5 to


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PDF CD54HC08, CD74HC08, CD54HCT08, CD74HCT08 SCHS118C CD74HCT08 74HCT
1997 - CD74HC125M96

Abstract: CD74HC125M96E4 CD54HCT125 CD54HCT125F3A CD74HC125 CD74HCT125 HC125 HCT125 CD54HC125 CD54HC125F3A
Text: - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V - 0.02 2 1.9 - - 1.9 - 1.9 - V - 0.02 4.5 4.4 - - 4.4 - 4.4 - V - 0.02 6 5.9 - - 5.9 - 5.9 - V , 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - -


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PDF HC125 HCT12 CD54HC125, CD74HC125, CD54HCT125, CD74HCT125 SCHS143C HC125 HCT125 CD74HC125M96 CD74HC125M96E4 CD54HCT125 CD54HCT125F3A CD74HC125 CD74HCT125 CD54HC125 CD54HC125F3A
1997 - CD74HC125M96

Abstract: CD74HC125M96E4 CD54HC125 CD54HC125F3A CD54HCT125 CD54HCT125F3A CD74HC125 CD74HCT125 HC125 HCT125
Text: - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V - 0.02 2 1.9 - - 1.9 - 1.9 - V - 0.02 4.5 4.4 - - 4.4 - 4.4 - V - 0.02 6 5.9 - - 5.9 - 5.9 - V , 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - -


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PDF HC125 HCT12 CD54HC125, CD74HC125, CD54HCT125, CD74HCT125 SCHS143C HC125 HCT125 CD74HC125M96 CD74HC125M96E4 CD54HC125 CD54HC125F3A CD54HCT125 CD54HCT125F3A CD74HC125 CD74HCT125
1997 - Not Available

Abstract: No abstract text available
Text: Three-State Non-Inverting Outputs all other input conditions. Moving data from two groups of registers to , The Output Enable input (OE) is active LOW. When OE is HIGH, all of the outputs (1Y-4Y) are in the , Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads VOH VIH or VIL - 0.02 - 0.02 - 0.02 High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL -6 -7.8 0.02 0.02 0.02 Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND 6 7.8 2 4.5 6 4.5


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PDF CD54HC257, CD74HC257, CD54HCT257, CD74HCT257 SCHS171D HC257 HCT25
1998 - CD74HC14M96E4

Abstract: No abstract text available
Text: Level Output Voltage TTL Loads Input Leakage Current II VCC and GND VCC or GND VCC - 2.1 VOL VT+ VOH V T- 0.02 -4 0.02 4 4.5 4.5 4.5 4.5 5.5 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.98 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.26 ±0.1 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.84 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.33 ±1 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.7 , VOH V T- 0.02 - 0.02 - 0.02 High Level Output Voltage TTL Loads -4 -5.2 Low Level Output Voltage CMOS Loads VOL VT+ 0.02 0.02 0.02 Low Level Output Voltage TTL Loads 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 0.7


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PDF CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 SCHS129F HCT14 CD74H -55oC 125oC CD74HC14M96E4
1998 - CD74HC14M96

Abstract: No abstract text available
Text: Level Output Voltage TTL Loads Input Leakage Current II VCC and GND VCC or GND VCC - 2.1 VOL VT+ VOH V T- 0.02 -4 0.02 4 4.5 4.5 4.5 4.5 5.5 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.98 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.26 ±0.1 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.84 1.9 2.1 1.2 1.4 1.4 1.5 0.1 0.33 ±1 1.2 1.4 0.5 0.6 0.4 0.4 4.4 3.7 , VOH V T- 0.02 - 0.02 - 0.02 High Level Output Voltage TTL Loads -4 -5.2 Low Level Output Voltage CMOS Loads VOL VT+ 0.02 0.02 0.02 Low Level Output Voltage TTL Loads 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 0.7


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PDF CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 SCHS129F HCT14 CD74H -55oC 125oC CD74HC14M96
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