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Part Manufacturer Description Datasheet Download Buy Part
LT1126AMJ8/883B Linear Technology IC DUAL OP-AMP, 170 uV OFFSET-MAX, 65 MHz BAND WIDTH, CDIP8, CERDIP-8, Operational Amplifier
LT1124AMJ8/883B Linear Technology IC DUAL OP-AMP, 170 uV OFFSET-MAX, 12.5 MHz BAND WIDTH, CDIP8, CERDIP-8, Operational Amplifier
LT1124AMPS8-1#PBF Linear Technology IC DUAL OP-AMP, 170 uV OFFSET-MAX, 12.5 MHz BAND WIDTH, PDSO8, 0.150 INCH, LEAD FREE, PLASTIC, SOP-8, Operational Amplifier
LT1124AMJ8 Linear Technology IC DUAL OP-AMP, 170 uV OFFSET-MAX, 12.5 MHz BAND WIDTH, CDIP8, 0.300 INCH, HERMETIC SEALED, CERAMIC, DIP-8, Operational Amplifier
LT1126AMJ8 Linear Technology IC DUAL OP-AMP, 170 uV OFFSET-MAX, 65 MHz BAND WIDTH, CDIP8, 0.300 INCH, HERMETIC, CERAMIC, DIP-8, Operational Amplifier
LT1124CJ8#TR Linear Technology IC DUAL OP-AMP, 170 uV OFFSET-MAX, 12.5 MHz BAND WIDTH, CDIP8, 0.300 INCH, HERMETIC SEALED, CERAMIC, DIP-8, Operational Amplifier

BI 170-1-2 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
BI 170-1-2

Abstract: A/BI 170-1-2 DAC725BH DAC725BH-BI DAC725SH/QM
Text: 15 DIM AC) A id B Bi C DC) E E i« ei eA r° U U Hj * 1 o 14 INCHES MIN MAX .169 -.200 , leV activation energy. Plastic "- BI " models: +70°C Ceramic "- BI " models: +85°C Ceramic DAC725SH/QM , , add "- BI " to the base model number. s? ll * 0 o ra S $ °-1 m +i p < u tr o> O£ g £ 0.01 Z i_o 75


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PDF 17313bS DAC725 16-Bit DAC725 BI 170-1-2 A/BI 170-1-2 DAC725BH DAC725BH-BI DAC725SH/QM
Not Available

Abstract: No abstract text available
Text: No file text available


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PDF 16-bit
2003 - BC 536

Abstract: FRB CRS AN2491
Text: prediction, as part of the instruction mnemonic rather than as numeric operands (the BO and BI operands). , branch instructions that include BO and BI operands; there is no need to simplify unconditional branch , Conditional target_addr bc (bca bcl bcla) BO, BI ,target_addr Branch Conditional to Link Register Freescale Semiconductor, Inc. Syntax bclr (bclrl) Branch Conditional to Count Register BO, BI bcctr (bcctrl) BO, BI The BO and BI operands correspond to two fields in the instruction opcode, as


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PDF AN2491 BC 536 FRB CRS AN2491
bi 240

Abstract: SnAgCu NA200 flux NA200 QFP-208 NA-200 QFP PACKAGE thermal resistance QFP 128 bonding SMD Packages epson, whisker
Text: 3-2 Dependence of bonding reliability on Bi density (1) Bonding reliability of Sn-Bi plating/Sn-Ag-Cu , Temperature Profile Used in Mount Testing 5. Sn Whisker Evaluation ( Bi Density Dependence) 6. Soldering , * Dependence of lead bend appearance on Bi density Cu frame Sn-1.5% Bi -3.0% Bi -4.5% Bi -6.0% Bi -3.0% Bi -4.5% Bi -6.0% Bi 42 alloy frame Sn-1.5% Bi · Plating cracks on lead bend increase as the Bi density increases. (Plating cracks are not deep enough to expose the lead


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PDF NA200) bi 240 SnAgCu NA200 flux NA200 QFP-208 NA-200 QFP PACKAGE thermal resistance QFP 128 bonding SMD Packages epson, whisker
RD272

Abstract: bc 303 transistor BC 536 AN2491
Text: mnemonic rather than as numeric operands (the BO and BI operands). Table 4 shows the four general types of , BI operands; there is no need to simplify unconditional branch mnemonics. Table 4. Branch , (bca bcl bcla) BO, BI ,target_addr Branch Conditional to Link Register Freescale Semiconductor, Inc. Syntax bclr (bclrl) Branch Conditional to Count Register BO, BI bcctr (bcctrl) BO, BI The BO and BI operands correspond to two fields in the instruction opcode, as Figure 1 shows for Branch


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PDF AN2491 32-Bit RD272 bc 303 transistor BC 536 AN2491
2006 - NA200 flux

Abstract: bi 240 QFP 208 MT90810AK3 NA200 QFP208-pin epson, whisker
Text: 3-2 Dependence of bonding reliability on Bi density (1) Bonding reliability of Sn-Bi plating/Sn-Ag-Cu , Temperature Profile Used in Mount Testing 5. Sn Whisker Evaluation ( Bi Density Dependence) 6. Soldering , * Dependence of lead bend appearance on Bi density Cu frame Sn-1.5% Bi -3.0% Bi -4.5% Bi -6.0% Bi -3.0% Bi -4.5% Bi -6.0% Bi 42 alloy frame Sn-1.5% Bi · Plating cracks on lead bend increase as the Bi density increases. (Plating cracks are not deep enough to expose the lead


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PDF MT90810AK3 NA200) NA200 flux bi 240 QFP 208 MT90810AK3 NA200 QFP208-pin epson, whisker
2001 - 7400 series CMOS Logic ICs

Abstract: VIA P4X266 ICS93712 ICS93718 ICS950905 SEL24 ICS93715 PC133 registered reference design 7400 fan-out
Text: disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 7 8 1 PWD X , ) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# X X X X X X X X , ) (Reserved) (Reserved) Byte 6: Vendor ID Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Revision ID Bit3 Revision ID Bit2 Revision ID Bit1 , ) (Reserved) (Reserved) (Reserved) Byte 7: Revision ID and Device ID Register Bit Bi t 7 Bi t 6 Bi


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PDF ICS950905 48MHz 318MHz MO-118 ICS950904yFT 7400 series CMOS Logic ICs VIA P4X266 ICS93712 ICS93718 ICS950905 SEL24 ICS93715 PC133 registered reference design 7400 fan-out
ISL9504

Abstract: pg65d SH0925 U8550 DP431 U8500 j4310 c5855 PP3V42G3H U4900
Text: 80 14 7 80 14 7 80 14 7 80 14 7 80 14 7 80 14 7 80 14 7 80 14 7 80 14 7 7 OMIT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI 6 U1000 ADS* BNR* BPRI* DEFER* DRDY* DBSY* BR0* IERR* INIT* LOCK* H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 80 5 BI BI BI 7 14 80 7 14 80 14 80 4 3 2 1 D 80 , > XDP_BPM_L<5> XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L =PP1V05_S0_CPU BI BI BI 14 80 7 14 80 7 14 80 8 10 11 12 13 1 R1002 54.9 BI 7 14 80 1% 1/16W MF-LF 2 402 PLACE


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PDF ISL10 ISL11 ISL9504 pg65d SH0925 U8550 DP431 U8500 j4310 c5855 PP3V42G3H U4900
2003 - ICS950219

Abstract: 7400 series CMOS Logic ICs 318M CK-408 pci 32 bit 5v
Text: _0 Byte 4: Output Control Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 31 30 48 1 27 28 PWD X X 1 1 1 1 1 1 Description , Byte 5: Programming Edge Rate (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# X X X X X X X PWD 1 1 1 1 1 1 1 0 Description , bi t 0 = 0 66.01MHz/33.00MHz (Async with CPU) 66.66MHz/33.33MHz (Sync with CPU) B 5 bi t 0 =


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PDF ICS950219 318MHz MO-118 ICS950219yFLF-T 0640D--12/30/03 ICS950219 7400 series CMOS Logic ICs 318M CK-408 pci 32 bit 5v
ISL9504

Abstract: j4310 BD9828 ISL9504B NVIDIA G84m RN5VD30A-F SLG2AP101 Q7080 88E8058 eng boost press sht hi 128 102 03
Text: 83 14 7 83 14 7 7 OMIT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI 6 U1000 MEROM FCBGA 1 , F1 D20 B3 H4 83 5 BI BI BI 7 14 83 7 14 83 14 83 4 3 2 1 D 83 14 7 83 14 7 83


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PDF 03/19/m 100-ohm 95-ohms ISL10 ISL11 ISL9504 j4310 BD9828 ISL9504B NVIDIA G84m RN5VD30A-F SLG2AP101 Q7080 88E8058 eng boost press sht hi 128 102 03
2001 - EF232

Abstract: ICS950202 48MHZ CK-408 PS-0500 6666M
Text: Logi c i nput frequency select bi t. Input latched at power on. 3.3V P C I clock output. 6 FS 1 9 , bi t. Input latched at power on. O UT 17, 16, 15, 12, 11, 10 P C IC LK (6:1) 23 IN This , internal VCO or 48MHz (non-SSC). Logi c i nput frequency select bi t. Input latched at power on. A nalog power 3.3V. 3.3V F i xed 48MHz clock output for D OT. Logi c i nput frequency select bi t. Input , external resistors are required for voltage bias. Logi c i nput frequency select bi t. Input latched at


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PDF ICS950202 CK-408 318MHz 150ps 250ps MO-118 ICS950202yFT EF232 ICS950202 48MHZ PS-0500 6666M
e3 sot363 8pin

Abstract: ISL9504 PP3V42G3H C8050 R5370 "cross reference" k50 apple p66 apple M75 MLB 820-2101 NVIDIA G84m 051-7225
Text: 79 14 7 79 14 7 7 OMIT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI 6 U1000 MEROM FCBGA 1 , F1 D20 B3 H4 79 5 BI BI BI 7 14 79 7 14 79 14 79 4 3 2 1 D 79 14 7 79 14 7 79 , XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L PP1V05_S0 BI BI BI 14 79 7 14 79 7 14 79 8 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 1 R1002 54.9 BI 7 14 79 1% 1/16W MF-LF 2 402 PLACE TESTPOINT ON FSB_IERR_L WITH A GND 0.1" AWAY D IN 23 47 79 BI 7 14 79 79 14 7 79 14 7 79


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PDF 01/17/2007ER ISL10 ISL11 e3 sot363 8pin ISL9504 PP3V42G3H C8050 R5370 "cross reference" k50 apple p66 apple M75 MLB 820-2101 NVIDIA G84m 051-7225
ISL9504

Abstract: PP3V42G3H NVIDIA G84m ISL9504BCRZ b6886 k50 apple p66 apple M75 MLB 820-2101 PP3V42 C8050 12v
Text: 1 8 79 14 7 79 14 7 79 14 7 79 14 7 79 14 7 79 14 7 79 14 7 79 14 7 79 14 7 7 OMIT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI 6 U1000 MEROM FCBGA 1 OF 4 ADS* BNR* BPRI* DEFER* DRDY* DBSY* ADDR GROUP0 BR0* CONTROL IERR* INIT* LOCK* H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 79 5 BI BI BI 7 , XDP_DBRESET_L PP1V05_S0 BI BI BI 14 79 7 14 79 7 14 79 8 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 1 R1002 54.9 BI 7 14 79 1% 1/16W MF-LF 2 402 PLACE TESTPOINT ON FSB_IERR_L WITH A


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PDF ISL10 ISL11 ISL9504 PP3V42G3H NVIDIA G84m ISL9504BCRZ b6886 k50 apple p66 apple M75 MLB 820-2101 PP3V42 C8050 12v
ISL6259

Abstract: transistor C3229 ISL6258AHRTZ transistor c6074 ISL9504BCRZ of transistor c2570 transistor c3300 c3228 transistor transistor c3150 c2570 transistor
Text: No file text available


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2002 - ICS950213

Abstract: ef232 318M CK-408 ICS950219 7400 series CMOS Logic ICs
Text: Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 , ) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Revision ID Bit3 , Device ID Register Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Device , Byte 8: Byte Count Read Back Register Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0 PWD Description 0 0 0


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PDF ICS950219 318MHz 150ps 250ps 100ps MO-118 ICS950219yFT ICS950213 ef232 318M CK-408 ICS950219 7400 series CMOS Logic ICs
PP3V42G3H

Abstract: NVIDIA G84m apple J8000 ISL9504 p66 apple C4740 apple computer C8050 C7103 338S0432
Text: 8 79 14 7 79 14 7 79 14 7 79 14 7 79 14 7 79 14 7 79 14 7 79 14 7 79 14 7 7 OMIT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI 6 U1000 MEROM FCBGA 1 OF 4 ADS* BNR* BPRI* DEFER* DRDY* DBSY* ADDR GROUP0 BR0* CONTROL IERR* INIT* LOCK* H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 79 5 BI BI BI 7 14 79


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PDF MBP15 ISL10 ISL11 PP3V42G3H NVIDIA G84m apple J8000 ISL9504 p66 apple C4740 apple computer C8050 C7103 338S0432
2002 - p4m 29

Abstract: kn266 ICS950902 CK408 ICS-950902
Text: Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 , /Inactive Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 35 36 37 38 41 42 43 44 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 , /Inactive) SDRAM0/DDRT0 (Active/Inactive) Byte 6: Vendor ID Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Revision ID Bit3 Revision ID


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PDF ICS950902 P4X/P4M/KT/KN266/333 200MHz. 318MHz MO-153 ICS950902yGT 0475E--12/19/02 p4m 29 kn266 ICS950902 CK408 ICS-950902
ISL9504

Abstract: ISL9504B PP3V42G3H M75 MLB 820-2101 c7381 c5855 C8550 N8242 ISL9504 U7500 c3334 schematic diagram
Text: 79 14 7 79 14 7 7 OMIT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI 6 U1000 MEROM FCBGA 1 , F1 D20 B3 H4 79 5 BI BI BI 7 14 79 7 14 79 14 79 4 3 2 1 D 79 14 7 79 14 7 79 , XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L PP1V05_S0 BI BI BI 14 79 7 14 79 7 14 79 8 10 11 12 13 14 18 19 21 23 26 27 30 46 50 61 1 R1002 54.9 BI 7 14 79 1% 1/16W MF-LF 2 402 PLACE TESTPOINT ON FSB_IERR_L WITH A GND 0.1" AWAY D IN 23 47 79 BI 7 14 79 79 14 7 79 14 7 79


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PDF ISL10 ISL11 ISL9504 ISL9504B PP3V42G3H M75 MLB 820-2101 c7381 c5855 C8550 N8242 ISL9504 U7500 c3334 schematic diagram
2003 - Not Available

Abstract: No abstract text available
Text: : Frequency Select Active/Inactive Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 0475F-10/13/03 Pin# 20 21 1 PWD X X X X 1 1 1 Description Latched , Active/Inactive Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 35 36 37 38 41 42 43 44 PWD 1 1 1 1 1 1 1 1 Description SDRAM7/DDRC3 (Active , (Active/Inactive) Byte 6: Vendor ID Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4


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PDF ICS950902 P4X/P4M/KT/KN266/333 CK408 48MHz 48MHz 318MHz MO-153 ICS950902yGT 0475F--10/13/03
2003 - ICS950219

Abstract: 318M CK-408 7400 series CMOS Logic ICs
Text: _0 Byte 4: Output Control Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 31 30 48 1 27 28 PWD X X 1 1 1 1 1 1 Description , Byte 5: Programming Edge Rate (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# X X X X X X X PWD 1 1 1 1 1 1 1 0 Description , bi t 0 = 0 66.01MHz/33.00MHz (Async with CPU) 66.66MHz/33.33MHz (Sync with CPU) B 5 bi t 0 =


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PDF ICS950219 318MHz 150ps 250ps 100ps MO-118 ICS950219yFT 0640C--05/28/03 ICS950219 318M CK-408 7400 series CMOS Logic ICs
RTL8211E

Abstract: RTL8211CL reference Design HS82117 MCP79 rtl8211cl RTL8211 ISL6258A u9701 C5855 TC7SZ08AFEAPE
Text: 14D6 71D3 14D6 71D3 14C6 71D3 14C6 71D3 14C6 71D3 14C6 71D3 14C6 71D3 14C6 7 OMIT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI 6 ADS* BNR* BPRI* DEFER* DRDY* DBSY* H1 E2 G5 5 14B6 71C3 14B6 , PENRYN FCBGA FSB_ADS_L FSB_BNR_L FSB_BPRI_L FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L FSB_BREQ0_L 71B3 BI BI BI 1 OF 4 =PP1V05_S0_CPU 6D8 8D7 11C6 12B6 13D6 H5 F21 E1 BI BI BI 14B3 71C3 , * LOCK* F1 BI 9B2 14B6 71C3 2 D20 B3 CPU_IERR_L CPU_INIT_L FSB_LOCK_L D IN 14A3


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ar9350

Abstract: C496-0 PP3V42G3H C3979 U0700 RN5VD30A-F J5200 OG-503040 I251 diode p66 apple
Text: 86 12 5 86 12 5 86 12 5 86 12 5 7 OMIT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI 6 U0700 , PP1V05_S0 BI BI BI BI BI BI BI 5 12 86 5 12 86 12 86 5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66 4 , AB6 C20 D21 A24 A25 C7 86 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI IN OUT IN IN IN IN IN 6 6 6 6 6 6 6 6 6 6 86 12 5 86 12 5 86 12 , 2402 R0702 54.9 5 12 86 IN BI IN IN IN IN IN BI BI 21 86 PLACE TESTPOINT ON FSB_IERR_L


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PDF ITP700FLEX ar9350 C496-0 PP3V42G3H C3979 U0700 RN5VD30A-F J5200 OG-503040 I251 diode p66 apple
2004 - 0735A

Abstract: CK408 kn266 ICS950910 VX550 PC133-SDRAM X2453
Text: (Default=0) Description Bi t Bit2 Bi t (2,7:4) Bi t 3 Bi t 1 Bi t 0 PWD Bit7 Bit6 Bit5 , Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 , /Inactive Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 35 36 37 38 41 42 43 44 PWD 1 1 1 1 1 1 1 1 Description DDRC3 , : Vendor ID Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t


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PDF ICS950910 P4X/P4M/KT/KN266/333 CK408 48MHz 318MHz 250ps 500ps 0735A kn266 ICS950910 VX550 PC133-SDRAM X2453
2007 - X2453

Abstract: CK408 ICS950910 CPU408
Text: (Default=0) Description Bi t Bit2 Bi t (2,7:4) Bi t 3 Bi t 1 Bi t 0 PWD Bit7 Bit6 Bit5 , Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 , /Inactive Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 35 36 37 38 41 42 43 44 PWD 1 1 1 1 1 1 1 1 Description DDRC3 , : Vendor ID Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t


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PDF ICS950910 P4X/P4M/KT/KN266/333 CK408 48MHz 318MHz 250ps 500ps X2453 ICS950910 CPU408
2004 - CK408

Abstract: ICS950902
Text: Select Active/Inactive Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 20 21 1 PWD X X X X 1 1 1 Description Latched FS3 , . Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 35 36 37 38 41 42 43 44 PWD 1 1 1 1 1 , = enable, 0 = disable) Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name


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PDF ICS950902 P4X/P4M/KT/KN266/333 CK408 48MHz 48MHz 318MHz MO-153 ICS950902yGLF-T 0475G--03/23/04 ICS950902
Supplyframe Tracking Pixel