The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTM9009CY-14#PBF-ES Linear Technology LTM9009-14 - 14-Bit, 80Msps Low Power Octal ADCs; Package: BGA; Pins: 140; Temperature: Commercial
LTM9010CY-14#PBF-ES Linear Technology LTM9010-14 - 14-Bit, 105Msps Low Power Octal ADCs; Package: BGA; Pins: 140; Temperature: Commercial
LTM9009IY-14#PBF-ES Linear Technology LTM9009-14 - 14-Bit, 80Msps Low Power Octal ADCs; Package: BGA; Pins: 140; Temperature: Industrial
LTM9010IY-14#PBF-ES Linear Technology LTM9010-14 - 14-Bit, 105Msps Low Power Octal ADCs; Package: BGA; Pins: 140; Temperature: Industrial
LTM9011IY-14#PBF-ES Linear Technology LTM9011-14 - 14-Bit, 125Msps Low Power Octal ADCs; Package: BGA; Pins: 140; Temperature: Industrial
LTM9011CY-14#PBF-ES Linear Technology LTM9011-14 - 14-Bit, 125Msps Low Power Octal ADCs; Package: BGA; Pins: 140; Temperature: Commercial

BGA-64 pad Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2010 - Recommended land pattern smd-0.5

Abstract: "x-ray machine" Lattice Semiconductor Package Diagrams 256-Ball fpBGA pcb fabrication process package dimension 256-FTBGA nomenclature pcb hdi LC4064ZE ultra fine pitch BGA TN1074 BN256
Text: Semiconductor SMD/NSMD Pad Recommendations1 0.4 mm Ball Pitch 64 , 132 ucBGA Nominal BGA package pad opening diameter (mm) - SMD 0.5 mm Ball Pitch 0.8 mm Ball Pitch 56, 64 , 100, 132, 144 csBGA , Lattice Semiconductor SMD/NSMD Pad Recommendations table Added 64 csBGA to 0.5mm pitch column. 19-19 , as possible. If Non Solder Mask Defined Pads (NSMD) are used, the optimum pad dimensions will result , Defined (SMD) Pad Recommendations Optimum solder mask opening 0.22 0.30 0.40 PCB Non Solder


Original
PDF TN1074 Recommended land pattern smd-0.5 "x-ray machine" Lattice Semiconductor Package Diagrams 256-Ball fpBGA pcb fabrication process package dimension 256-FTBGA nomenclature pcb hdi LC4064ZE ultra fine pitch BGA TN1074 BN256
BGA-56 DATASHEET

Abstract: mini ball corner PQFP die size cpga dimensions BGA-64 pad atmel 0945 PQFP 132 PACKAGE DIMENSION
Text: 4-32 Packaging 0.75 REF 0.50 pkg-3.7-04/99 Mini Array BGA 64 /.8 Top View A1 BALL PAD , , 52, 64 , 80, 100, 120, 128, 132, 144, 160, 184, 208, 240, 304 Power Quad 144, 160, 208, 240, 304 L/TQFP 32, 44, 48, 64 , 80, 100, 120, 128, 144, 160, 176, 216 PLCC 20, 28, 32, 44, 52, 68, 84 CPGA 64 , 68, 84, 100, 124, 144, 155, 180, 223, 224, 299, 391 CQFP 64 , 68, 84, 100, 120 , 132, 144, 160, 180, 208 Chip Scale BGA(1) 40, 49, 56, 64 , 81, 84, 96, 100, 128 Note: 1


Original
PDF
2003 - LQFP-48 thermal pad

Abstract: exposed QFP 144 CQFP 240 QFP-128 20 x 14 pad exposed QFP 128 BGA-64 pad LQFP-64 thermal pad SOT23-6 1152 BGA 144 2-CQFP
Text: ) 135.7 JEDEC 2 Paddle soldered to board, no thermal vias in pad CSP 20 (4 ×4) 30.4 JEDEC 4 Paddle soldered to board, 9 thermal vias in pad CSP 20 (4 ×4) 70.5 JEDEC , board, no thermal vias in pad CSP 32 (5 ×5) 27.3 JEDEC 4 CSP 32 (5 ×5) 46 , 2S2P Paddle soldered to board, 9 thermal vias in pad CSP 48 (7 ×7) 25.9 JEDEC 4 , JEDEC 4 (5 × 5 mm) CSP BGA 64 165 JEDEC 2 (9 × 9 mm) CSP BGA 64 129


Original
PDF G38-87. LQFP-48 thermal pad exposed QFP 144 CQFP 240 QFP-128 20 x 14 pad exposed QFP 128 BGA-64 pad LQFP-64 thermal pad SOT23-6 1152 BGA 144 2-CQFP
35 x 35 PBGA, 580 100 balls

Abstract: of BGA Staggered Pins package BGA Ball Crack without underfill BGA PACKAGE thermal resistance 60um of BGA Staggered pins
Text: 0.5 0.4 0.3 Peripheral Pad Bare Die 6 7 8 9 10 20 30 40 50 70 100 Area Pad Bare Die , Table 1 Multi-Pin Packages Solder ball Low thermal resistance For fine pitch pad Chip , super high-speed device Thin For fine pitch pad NEC's Development of New Packages 1. Multi-pin , they surpass PBGAs in shrinking the pad pitch of the device. Already, TBGAs with a pitch of 60 µm , the pad pitch of the device (40 µm) or area pad placement · Can be used for a wide range of devices


Original
PDF
CMOS applications handbook

Abstract: ttl to mini-lvds CII51010-2 EP2C20 EP2C35 EP2C50 SSTL-18
Text: /O standards Cyclone II I/O banks Programmable current drive strength I/O termination Pad , timing requirements. Table 10­2 lists the specific Cyclone II devices that support 64 - and 32-bit PCI , Package 64 Bits EP2C5 32 Bits 144-pin TQFP 208-pin PQFP 256-pin FineLineBGA® 10­4 Cyclone , Grades Device Package 64 Bits EP2C8 32 Bits 144-pin TQFP 208-pin PQFP EP2C15 v , Table 10­3 lists the specific Cyclone II devices that support 64 -bit and 32-bit PCI at 33 MHz. Table


Original
PDF CII51010-2 SSTL-18, CMOS applications handbook ttl to mini-lvds EP2C20 EP2C35 EP2C50 SSTL-18
SSTL-18

Abstract: ttl to mini-lvds CII51010-2 EP2C20 EP2C35 EP2C50 JESD8-15
Text: /O standards Cyclone II I/O banks Programmable current drive strength I/O termination Pad , timing requirements. Table 10­2 lists the specific Cyclone II devices that support 64 - and 32-bit PCI , Package 64 Bits EP2C5 32 Bits 144-pin TQFP 208-pin PQFP 256-pin FineLineBGA® 10­4 Cyclone , Grades Device Package 64 Bits EP2C8 32 Bits 144-pin TQFP 208-pin PQFP EP2C15 v , Table 10­3 lists the specific Cyclone II devices that support 64 -bit and 32-bit PCI at 33 MHz. Table


Original
PDF CII51010-2 SSTL-18, SSTL-18 ttl to mini-lvds EP2C20 EP2C35 EP2C50 JESD8-15
1995 - AE23

Abstract: EP20K100E AF-1
Text: ­ 8 8 8 8 8 ­ 8 8 8 8 8 ­ ­ ­ ­ 8 8 8 Pad Number Orientation Pin/ Pad , Pad Number Orientation Pin/ Pad Function 144-Pin 208-Pin 240-Pin 144-Pin 324-Pin 356 , 7 7 ­ 7 7 7 7 7 ­ 7 7 7 7 7 ­ ­ 7 7 7 7 ­ ­ 61 62 63 64 65 66 67 68 , 6 6 6 6 6 ­ 6 6 6 6 ­ ­ 5 ­ ­ ­ ­ ­ ­ ­ ­ 5 ­ ­ Pad Number Orientation Pin/ Pad Function 144-Pin 208-Pin 240-Pin 144-Pin 324-Pin 356-Pin TQFP (1) PQFP (1) PQFP (1


Original
PDF EP20K100E 144-Pin 208-Pin 240-Pin 144-Pin 324-Pin 356-Pin AE23 AF-1
1999 - RC3041

Abstract: RC4640 RC4650 RC64474 RC64475
Text: - RC4xxx / RC5xxx CPU Bus Interface Direct connection between CPU & RC64145 32- or 64 -bit bus , Big or Little Endian support x Supports 32- or 64 -bit CPU and 32- or 64 -bit memory x Memory & , Supports 8-,16-,32- or 64 -bit devices 8-bit boot PROM support x SDRAM Controller 32- or 64 -bit, up to 4 , - or 64 -bit Timer, UART, Int Modules 64 bit IP Bus Memory and I/O Control DMA Channels 32- or 64 -bit Memory SDRAM Controller Memory CPU I/F and IP Bridge PCI I/F and


Original
PDF 32-bit 388-pin IDT79RC64 64-bit IDT79RC64V145 IDT79RC32V145 IDT79RCXX RC3041 RC4640 RC4650 RC64474 RC64475
1995 - TTL pin outs

Abstract: CMOS TTL Logic Family Specifications 30J341 footprint tqfp 208 BGA and QFP Package BITBLASTER v16 248 circuit diagram of plcc modem 431 data sheet N12110
Text: 1,250 2,500 5,000 10,000 Macrocells 32 64 128 256 512 Logic array , /O Control Block 3 to 16 I/O 16 3 to 16 Macrocells 49 to 64 3 to 16 6 Note , Min -12 Max Min Max tIN Input pad and buffer delay 0.6 0.7 0.9 1.1 ns tIO I/O input pad and buffer delay 0.6 0.7 0.9 1.1 ns tFIN Fast input delay , Internal output enable delay 0.0 0.0 0.0 0.0 ns tOD1 Output buffer and pad C1 = 35


Original
PDF 7000AE EPM7128A EPM7256A 256-pin TTL pin outs CMOS TTL Logic Family Specifications 30J341 footprint tqfp 208 BGA and QFP Package BITBLASTER v16 248 circuit diagram of plcc modem 431 data sheet N12110
2003 - AE23

Abstract: EP20K100E
Text: EP20K100E I/O Pins ver. 1.1 I/O & Pad Pin/ Pad VREF Number Function Bank Orientation 144 , Corporation 1 EP20K100E I/O Pins ver. 1.1 I/O & Pad Pin/ Pad VREF Number Function Bank Orientation , 7 7 7 ­ 7 7 7 7 7 ­ ­ 7 7 7 7 ­ ­ 6 6 6 6 6 6 6 6 6 6 ­ 61 62 63 64 , GNDIO 2 EP20K100E I/O Pins ver. 1.1 I/O & Pad Pin/ Pad VREF Number Function Bank Orientation , ­ 64 ­ VCCIO6 63 ­ ­ 62 ­ ­ VCCIO6 60 59 ­ ­ 58 57 56 VCCIO5 GND ­ VCCINT


Original
PDF EP20K100E 144-Pin 208-Pin 240-Pin 144-Pin 324-Pin 356-Pin AE23
2004 - 1000-pin bga 0,8 mm

Abstract: HQFP1414-64 HLQFP 176 Package QFN 64 8x8 footprint MO-235 FOOTPRINT BGA and QFP Package mounting HLQFP1414-100 "General Catalog" transistor sc100 LFPAK footprint
Text: , SDRAM). LSI Chip(4) Au wire Resin LSI Chip(3) LSI Chip(4) Resin Substrate Die pad Die bond materials LSI Chip(5) Die pad LSI Chip(6) LSI Chip(7) LSI Chip(8) LSI Chip (3) LSI , ) LSI Chip(4) Resin Substrate Die pad Die bond materials LSI Chip(5) Die pad LSI Chip(6 , Pad 280725µm LSI Chip WPP Cross-Sectional Structure LSI Chip WPP Planar Structure , Pad 280725µm LSI Chip WPP Cross-Sectional Structure LSI Chip WPP Planar Structure


Original
PDF Unit2607 REJ01K0003-0300 1000-pin bga 0,8 mm HQFP1414-64 HLQFP 176 Package QFN 64 8x8 footprint MO-235 FOOTPRINT BGA and QFP Package mounting HLQFP1414-100 "General Catalog" transistor sc100 LFPAK footprint
HL832N

Abstract: FCCSP HL832 Amkor CSP mold compound CABGA 6x6 amkor cabga thermal resistance cu pillar flip chip bga 0,8 mm amkor Cu pillar bga 9x9 Shipping Trays
Text: peripheral, 150 µm min. for area array ·Cu Pillar flip chip interconnect for finer bond pad pitches , cycles/hour, 2500 cycles 0 °C/+100 °C, 1 cycle/hour, 2230 cycles 8 mm body, 64 lead, 0.33 mm PWB NSMD pad size 17 mm body, 1019 lead to view the most current product information. www.amkor.com , 1.0 1.0 1.0 1.0 1.0 0.8 0.8 0.8 0.8 0.8 0.8 Ball Count 49 64 81 100 121 144 169 196 49 64 64 81 , 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Ball Count 169 196 25 36 48 64 64 84 80 108 96 132 156 180


Original
PDF
cu pillar

Abstract: Flip Chip Substrate HL832 ds7409 FCCSP chiparray amkor CABGA 48 7x7 amkor cabga thermal resistance ELC4785 flip chip bga 0,8 mm
Text: cycle/hour, 2230 cycles 8 mm body, 64 lead, 0.33 mm PWB NSMD pad size 17 mm body, 1019 lead , ·Cu Pillar flip chip interconnect for finer bond pad pitches ·Available in 0.4 mm - 1.0 mm BGA ball , 9x9 10 x 10 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 0.8 0.8 0.8 0.8 0.8 0.8 49 64 81 100 121 144 169 196 49 64 64 81 100 144 Full Full Full Full Full Full Full Full , 25 36 48 64 64 84 80 108 96 132 156 180 Full Full Full Full 2 Row Full 2 Row 3


Original
PDF
1995 - EPM7218

Abstract: No abstract text available
Text: 2.5 2.8 192.3 EPM7064AE 1,250 64 4 68 4.5 3.0 2.5 2.8 192.3 EPM7128AE EPM7128A 2,500 128 8 100 , Macrocells 49 to 64 3 to 16 I/O Control Block 3 to 16 I/O 16 6 3 to 16 3 to 16 6 , Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay , buffer and pad C1 = 35 pF delay, slow slew rate = off VCCIO = 3.3 V Output buffer and pad C1 = 35 pF delay, slow slew rate = off (6) VCCIO = 2.5 V Output buffer and pad C1 = 35 pF delay, slow slew rate =


Original
PDF 7000AE EPM7128A EPM7256A 256-pin EPM7218
1999 - 234 N02

Abstract: No abstract text available
Text: 61 62 63 64 65 GRP Delay from I/O Pad GRP Delay from Macrocell Global Clock 0 or 1 Delay Global , combinatorial function. A direct register input from the I/O pad facilitates efficient use of this feature to , To I/O Pad To GRP 6 PT 9 PT 8 PT 7 PT 6 PT 5 Global PTOE 0 . 5 Macrocell 1 From PTSA , Shared PT (P)reset 1 To I/O Pad To GRP 6 Global PTOE 0 . 5 PT 79 PT 78 PT 77 PT 76 PT 75 , Shared PT Clock 1 Shared PT (P)reset 1 To I/O Pad To GRP 6 Global PTOE 0 . 5 PT 159 PT


Original
PDF 5384VA 388-BGA 0212/5384va 5384VA-125LQ208 5384VA-125LB208 5384VA-125LB272 5384VA-125LB388 5384VA-100LQ208 5384VA-100LB208 5384VA-100LB272 234 N02
2008 - EP20K100E

Abstract: t25 4 j5
Text: ® Pin Information for the APEX EP20K100E Device Version 1.5 I/O & VREF Bank Pad Number Orientation Pin/ Pad Function 144-Pin TQFP (1) 208-Pin PQFP (1) 240-Pin PQFP (1) 144-Pin 324 , VREF Bank Pad Number Orientation Pin/ Pad Function 144-Pin TQFP (1) 208-Pin PQFP (1 , 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 , - VCCIO7 VCCIO6 71 - - 70 - 69 - 68 - - GND 67 - 66 - 65 - - - 64


Original
PDF EP20K100E 144-Pin 208-Pin 240-Pin 324-Pin 356-Pin PT-EP20K100E-1 t25 4 j5
2000 - construction of photo diode

Abstract: BGA 441 EH11 au 81 441 ball bga flip chip bga 0,8 mm
Text: substrate can be available. DBB AI PAD LSI Au Conductor Plastic Electrode WB ( Wire Bonding ) AI PAD Ni/Au chip coat High Temperature Solder Electrode High Temperature Solder Electrode Ceramic Substrate Au wire Ceramic Substrate PAD Pitch > 80 m > 170 , 169 121 Hole 11 11 11 121 64 Hole P = 1.0 mm 17 8 8 8 64 441


Original
PDF
1995 - T25 4 h5

Abstract: AE23 AF23 EP20K60E 356-pin 215 bga BGA128
Text: EP20K60E I/O Pins ver. 1.1 I/O & VREF Bank 8 8 8 8 ­ 8 8 8 8 8 ­ 8 ­ Pad Number Orientation Pin/ Pad Function 144-Pin TQFP (1) 208-Pin PQFP (1) 240-Pin PQFP (1) 144 , Pins ver. 1.1 I/O & Pad Number VREF Orientation Bank ­ 37 ­ 7 38 39 7 7 40 41 7 , 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 Altera Corporation Pin/ Pad Function 144-Pin TQFP (1) 208-Pin PQFP (1) 240-Pin PQFP (1) 144-Pin 324


Original
PDF EP20K60E 144-Pin 208-Pin 240-Pin 324-Pin 356-Pin T25 4 h5 AE23 AF23 356-pin 215 bga BGA128
1995 - C732B

Abstract: JESD-71 EPM7512AE EPM7256AE EPM7256A EPM7128AE EPM7128A EPM7064AE EPM7032AE m6251
Text: 1,250 2,500 5,000 10,000 Macrocells 32 64 128 256 512 Logic array , Control Block 2 to 16 I/O 16 2 to 16 Macrocells 49 to 64 2 to 16 6 Note: (1) 6 , Grade -4 Min Unit -7 Max Min -10 Max Min Max tIN Input pad and buffer delay 0.7 1.2 1.5 ns tIO I/O input pad and buffer delay 0.7 1.2 1.5 ns tFIN , output enable delay 0.0 0.0 0.0 ns tOD1 Output buffer and pad delay, slow slew rate =


Original
PDF 7000AE JESD-71 EPM7128A EPM7256A 49-pin 169-pin C732B JESD-71 EPM7512AE EPM7256AE EPM7128AE EPM7064AE EPM7032AE m6251
2007 - usb to rj45 extenders

Abstract: TCM-BF537B NET2272REV1A-LF 060TC1 PF48F2000P0XBQ0 ADSP-BF537 uclinux adsp-bf537 reflow KSZ8721BLI schematic usb extender 44 pins connector
Text: Hardware User Manual TCM-BF537 V1.4 BGA and Border Pad Versions Tinyboards from Bluetechnix , ) . 11 4 TCM-BF537B (Border Pad and BGA Versions , . 13 4.2 Footprint of Border Pad Baseboard . 14 4.3 Schematic Symbol of Border Pad Version . 15 4.4 Border Pad Pin Assignment


Original
PDF TCM-BF537 TCMBF537 TCM-BF537 TCM-BF537B TCM-BF537B-64 64MB-Flash usb to rj45 extenders TCM-BF537B NET2272REV1A-LF 060TC1 PF48F2000P0XBQ0 ADSP-BF537 uclinux adsp-bf537 reflow KSZ8721BLI schematic usb extender 44 pins connector
1999 - 5000VA

Abstract: b20 p03 A09 N03 5512VA 5384VA 5256VA 234 N02 5384VA-70L T14 N03 283 g23
Text: output can be an unrelated combinatorial function. A direct register input from the I/O pad facilitates , 1 From PTSA PTSA bypass PT 2 To I/O Pad PTOE PT Clock PT Reset PT Preset PT 3 PT , Global PTOE 0 . 5 Macrocell 1 PT 9 PT 8 From PTSA PTSA bypass PT 7 To I/O Pad PTOE , From PTSA PTSA bypass PT 77 To I/O Pad PTOE PT Clock PT Reset PT Preset PT 76 PT 75 , PTOE 0 . 5 Macrocell 31 PT 159 PT 158 From PTSA PTSA bypass PT 157 To I/O Pad


Original
PDF 5384VA 5384VA-125LB208 208-Ball 5384VA-125LB272 272-Ball 5384VA-125LB388 388-Ball 5384VA-100LQ208 208-Pin 5384VA-100LB208 5000VA b20 p03 A09 N03 5512VA 5384VA 5256VA 234 N02 5384VA-70L T14 N03 283 g23
1995 - eeprom programmer schematic

Abstract: No abstract text available
Text: 2.5 2.8 192.3 EPM7064AE 1,250 64 4 68 4.5 3.0 2.5 2.8 192.3 EPM7128AE EPM7128A 2,500 128 8 100 , Macrocells 49 to 64 3 to 16 I/O Control Block 3 to 16 I/O 16 6 3 to 16 3 to 16 6 , 2) Symbol Parameter Conditions -6 Min tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad C1


Original
PDF 7000AE EPM7128A EPM7256A EPM7128AE EPM7256AE EPM7512AE eeprom programmer schematic
1999 - A09 N03

Abstract: 5000VA 5256VA 5384VA 5512VA
Text: combinatorial function. A direct register input from the I/O pad facilitates efficient use of this feature to , Pad PTOE PT Clock PT Reset PT Preset PT 3 PT 4 Shared PT Clock 0 Shared PT (P)reset 0 , 8 From PTSA PTSA bypass PT 7 To I/O Pad PTOE PT Clock PT Reset PT Preset PT 6 PT , Global PTOE 0 . 5 Macrocell 15 PT 79 PT 78 From PTSA PTSA bypass PT 77 To I/O Pad , 158 From PTSA PTSA bypass PT 157 To I/O Pad PTOE PT Clock PT Reset PT Preset PT 156


Original
PDF 5384VA 5384VA-125LB208 208-Ball 5384VA-125LB272 272-Ball 5384VA-125LB388 388-Ball 5384VA-100LQ208 208-Pin 5384VA-100LB208 A09 N03 5000VA 5256VA 5384VA 5512VA
2000 - am3 938 pinout

Abstract: MA 573 U18 524 BN 672 M3
Text: Specification, Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits ­ Support for high-speed , Features Feature MultiCore system integration Hot-socketing support SignalTap logic analysis 64 -Bit, 66 , registers provide exceptional performance. IOEs provide a variety of features, such as 3.3-V, 64 -bit, 66


Original
PDF
1995 - AA10

Abstract: AA23 EP20K200E E22/6/BC237/238/239/EPC16/TL7660IDGKRG4-datasheet
Text: 8 8 8 8 8 ­ 8 8 8 8 8 ­ 8 8 8 8 8 ­ 8 8 8 8 8 ­ 8 8 8 8 8 ­ Pad Number Orientation Pin/ Pad Function 208-Pin PQFP (1) 240-Pin PQFP (1) 484-Pin 356 , ­ 8 8 8 8 8 ­ 8 8 8 8 8 ­ ­ ­ ­ 8 8 8 Pad Number Orientation Pin/ Pad , 672-Pin FineLine BGA 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 , ­ Pad Number Orientation Pin/ Pad Function 208-Pin PQFP (1) 240-Pin PQFP (1) 484


Original
PDF EP20K200E 208-Pin 240-Pin 484-Pin 356-Pin 652-Pin 672-Pin AA10 AA23 E22/6/BC237/238/239/EPC16/TL7660IDGKRG4-datasheet
Supplyframe Tracking Pixel