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ATM circuit diagram Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
ATM machine working circuit diagram

Abstract: T90500 ECTF PVC trunking
Text: Connection-Oriented Service - Before an ATM transmission can be initiated, a circuit called a "Virtual Circuit " must , Figure 10 - Block Diagram Of A Typical ATM Access Card TDM Data M VI P-90, SCSA, H.100 TDM Buses , via the establishment of an ATM Virtual Circuit (VC). Note that access to the ATM link occurs if user , that 24 TDM channels are assigned to an ATM Virtual Circuit . A cell holding 48 bytes of payload would , 6ms ATM AAL1 cell assembly delay mentioned earlier is equivalent to running a voice circuit over a


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RK73K2B

Abstract: TCO-700 R92-R96 computer Network Types diagram RK73K R97-R101 GAL16v8b NEC media gateway GRM40F104Z50 ATM circuit diagram
Text: DIAGRAM AND COMPONENT LIST This chapter shows the circuit diagrams and component lists. 6.1 C irc u it D iagram CHAPTER 6 CIRCUIT DIAGRAM AND COMPONENT LIST CHAPTER 6 CIRCUIT DIAGRAM AND COMPONENT LIST Figure 6-3. PCI Bridge 26 CHAPTER 6 CIRCUIT DIAGRAM AND COMPONENT LIST Figure 6-4. A T M SA R (^PD98401) 27 CHAPTER 6 CIRCUIT DIAGRAM AND COMPONENT LIST £i i T ì , DIAGRAM AND COMPONENT LIST 29 CHAPTER 6 CIRCUIT DIAGRAM AND COMPONENT LIST 6.2 C o m p o n


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PDF uPD98401 uPD98402A RK73K2B TCO-700 R92-R96 computer Network Types diagram RK73K R97-R101 GAL16v8b NEC media gateway GRM40F104Z50 ATM circuit diagram
1998 - ADSL Modem circuit diagram

Abstract: Signal Path Designer ATM circuit diagram
Text: machine is in PRESYNC mode, the payload data from the ATM cell is sent through a descrambling circuit , bytes of the ATM cell are used for the ATM header, and are clocked into the HEC generator circuit . The , Implementing 155 Mbps ATM in High Speed, High Density FPGAs with On-Chip RAM. Brian Faith , speed data communication applications such as 155 Mbps ATM demand the use of rate-matching buffers, or , will provide a case study of an FPGA-based ADSL application that uses the UTOPIA ATM interface


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1998 - ATM circuit diagram

Abstract: fifo ram 8bit Signal Path Designer
Text: machine is in PRESYNC mode, the payload data from the ATM cell is sent through a descrambling circuit , bytes of the ATM cell are used for the ATM header, and are clocked into the HEC generator circuit . The , Back Implementing 155 Mbps ATM in High Speed, High Density FPGAs with On-Chip RAM. Brian Faith , speed data communication applications such as 155 Mbps ATM demand the use of rate-matching buffers, or , will provide a case study of an FPGA-based ADSL application that uses the UTOPIA ATM interface


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1997 - TXC crystal osc

Abstract: ML6672 TXC-05551 TXC-05551-SCBA TXC-05551-SCCA TXC-21252-MC
Text: DEVELOPMENT BOARD INTRODUCTION TranSwitch has introduced the SARA-2 family of high-performance ATM cell , silicon. The TranSwitch SARA-2 Family is an integrated hardware and software solution for ATM , based on a unique version of microcode and a common SARA-2 integrated circuit (IC) device. The first , applications. The SARA-2 ATM Cell Processing IC contains several functional blocks that provide optimal cell processing via a careful mix of hardwired logic and programmable microcode. One subsystem, the SARA-2 ATM


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PDF TXC-21252 TXC-21252-MC TXC crystal osc ML6672 TXC-05551 TXC-05551-SCBA TXC-05551-SCCA TXC-21252-MC
1997 - CRC-10

Abstract: TXC-05551 TXC-05551-SCBA TXC-05551-SCCA
Text: BLOCK DIAGRAM DESCRIPTION Figure 2 shows a block diagram for the SARA-2 ATM Cell Processing IC. These , Control Test Access Port Figure 2. SARA-2 ATM Cell Processing IC Block Diagram -2- TXC , SARA-2 Product Family ATM Segmentation and Reassembly TXC-05551 PRODUCT INFORMATION SARA-2 ATM CELL PROCESSING IC INTRODUCTION TranSwitch has introduced the SARA-2 family of high-performance ATM cell processing products that provide the ultimate combination of ultra high-performance and


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PDF TXC-05551 TXC-05551-MC2 CRC-10 TXC-05551 TXC-05551-SCBA TXC-05551-SCCA
MC86000

Abstract: mc8600 circuit diagram adsl modem board INTEL 8086 teaklite mc68000 adsl modem input circuit 72MHZ RX samsung ap ADSL type 1 circuit diagrams
Text: easy to design a circuit diagram like below. S5N8947 nECS[i] 45 nWBE[i] 60 47 ADDR[9 , diagram is a UTOPIA interface circuit of the S5N8947 and S5N8950 in reference board, CM47-M66(72). A , to be assigned with a fixed value. In the below circuit diagram these values are set to "high". And , EVALUATION KIT FOR 8950/51 G.DMT CHIPSET ATM LAYER DEVICE INTERFACE DIAGRAM AND TIMING DIAGRAM TXCLK , in ATU-C, but it is not used in RT side in general Figure 3-2. Interconnection Diagram with ATM


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PDF S5N8947 16/32-Bit S5N8947 10/100BaseT RS232C S5N8950 S5N8950. MC86000 mc8600 circuit diagram adsl modem board INTEL 8086 teaklite mc68000 adsl modem input circuit 72MHZ RX samsung ap ADSL type 1 circuit diagrams
Not Available

Abstract: No abstract text available
Text: them to the ATM Controller Chip. Miscellaneous Synthesizer Circuit The synthesizer circuit allows , P/N IBM30CMTA5PRLQAAAT ATM 25Mbps PMD MODULE Introduction Description The PMD Module implements the complete ATM 25Mbps Physical Media Dependent (PMD) sublayer. The module is designed to interface to the ATM 25Mbps Controller Module series of devices which have the embedded Transmission , complete ATM -25 Mbps PMD sub­ layer function • PLL Clock and data recovery, based on proven IBM Token


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PDF IBM30CMTA5PRLQAAAT 25Mbps 64-pin RJ-45) 68X5655
2001 - CX28975

Abstract: CX28225 CX28394 physical layer interface
Text: circuit to generate all possible DSL clock rates ATM Layer Interface The IMA technology has been in , A key feature to support DSL is the timing circuit ; Block Diagram it is required for UTOPIA , Microprocessor Interface System Clock Reference Clock ATM Layer UTOPIA 2 Interface Timing Circuit , TM A CONEXANT BUSINESS IMA 4 Inverse Multiplexing for ATM CX28225 Inverse Multiplexing over ATM for DSL or T1/E1 applications requiring 4 ports Overview The CX28225 from Mindspeed


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PDF CX28225 CX28225 200ms laye2660-3007 500197B M01-0577 CX28975 CX28394 physical layer interface
2001 - CX28229

Abstract: CX28398 CX28985 6 PORT LIU G.SHDSL
Text: circuit to generate all possible DSL clock rates ATM Layer Interface The IMA technology has been in , to support DSL is the timing circuit ; it is Block Diagram The block diagram in figure 1 shows all the key functional blocks of the design: the ATM layer interface; timing circuit ; microprocessor , functionality · UTOPIA 2 master Timing Circuit · ATM Forum AF-PHY-0086.001 v1.1 and IMA v1.0 compliant , TM A CONEXANT BUSINESS IMA 8/32 Inverse Multiplexing for ATM CX28229 Inverse Multiplexing


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PDF CX28229 CX28229 CX28398 CX28985 6 PORT LIU G.SHDSL
1996 - VSC8110

Abstract: PM5355
Text: VITESSE VSC8110 Data Sheet ATM /SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with , Compatible with Industry ATM UNI Devices · SONET/SDH Frame Recovery · On Chip Clock Generation of the , General Description The VSC8110 is an ATM /SONET/SDH compatible transceiver integrating high speed clock , and reduced cost. The VSC8110 provides an integrated solution for ATM physical layers and SONET/SDH , clock multiplier unit is integrated into the transmit circuit to generate the high speed clock for the


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PDF VSC8110 STS-12/STM-4 VSC8110 G51011-0, PM5355
2001 - CX28975

Abstract: BT8370 AF-PHY-0086 physical layer interface
Text: circuit to generate all possible DSL clock rates ATM Layer Interface The IMA technology has been in , to support DSL is the timing circuit ; Block Diagram The block diagram in figure 1 shows all the key functional blocks of the design: the ATM layer interface; timing circuit ; microprocessor , for transmission convergence only functionality Timing Circuit · ATM Forum AF-PHY-0086.001 v1 , TM A CONEXANT BUSINESS IMA 2 Inverse Multiplexing for ATM CX28224 Inverse Multiplexing


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PDF CX28224 CX28224 l2660-3007 500194B M01-0575 CX28975 BT8370 AF-PHY-0086 physical layer interface
2001 - t1e8

Abstract: CX28229 CX28398 CX28985 M28228 physical layer interface
Text: key functional blocks of the design: the ATM layer interface; timing circuit ; microprocessor , : CX28229 Block Diagram Physical Layer Interface Mux UTOPIA 2 8 or 16 bit ATM Layer UTOPIA 2 , functionality · UTOPIA 2 master Timing Circuit · ATM Forum AF-PHY-0086.001 v1.1 and IMA v1.0 compliant , IMA 8/32 Inverse Multiplexing for ATM CX28229 Inverse Multiplexing over ATM for DSL or T1/E1 , Physical layer connectivity > Complete software support provided > ATM Forum AF-PHY-0086.001 v1.1 and


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PDF CX28229 CX28229 t1e8 CX28398 CX28985 M28228 physical layer interface
2001 - CX28225

Abstract: SHDSL chips CX28394 CX28975 physical layer interface
Text: functional in this circuit allow for flexible rate reference clocks. blocks of the design: the ATM , System Clock Reference Clock ATM Layer Utopia 2 Interface Timing Circuit IMA 4 , TM A CONEXANT BUSINESS IMA 4 Inverse Multiplexing for ATM CX28225 Overview The CX28225 , Utopia 2 Physical layer connectivity · Integrated differential delay SRAM · A timing circuit to , > ATM Forum AF-PHY-0086.001 v1.1 and compatible with v1.0 The IMA technology has been in the market


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PDF CX28225 CX28225 200ms solu2660-3007 00195A M01-0513 SHDSL chips CX28394 CX28975 physical layer interface
1999 - 155L

Abstract: CRC-10 HQFP240 MB86696 MB86697A
Text: Product Flyer June 1999 MB86696 FireStreamTM155L ATM 155Mbps SAR Device Version 1.0 FML/NPD/FS155L/FL/2212 The FireStream155L is a low cost high performance ATM protocol controller which autonomously terminates ATM Adaptation Layer standard Type 5 (AAL5). ATM cells are received through a UTOPIA , rate in excess of 155Mbps. PLASTIC PACKAGE HQFP240 All ATM Forum traffic classes (ABR, VBR, CBR, UBR) are supported with traffic management to ATM Forum TM4.0 specification on up to 1024 virtual


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PDF MB86696 FireStreamTM155L 155Mbps FML/NPD/FS155L/FL/2212 FireStream155L 155Mbps. HQFP240 FML/NPD/FS155L/FL/2212 155L CRC-10 HQFP240 MB86696 MB86697A
2003 - IMA-32

Abstract: 484-pin BGA M-0307 m285
Text: The block diagram in figure 1 shows all the key functional blocks of the design: the ATM layer , supports Transmission Convergence (TC) Timing Circuit · ATM forum AF-PHY-0086.001 v1.1 and , IMA-32 Inverse Multiplexing for ATM M28529 32 Port IMA Solutions for T1/E1 and DSL , 32 T1/E1 or DSL links > ATM forum AF-PHY-0086.001 v1.1 and compatible with v1.0 > 64 Kbps to , IMA solution · ATM Forum AF-PHY-0086.001 v1.1 and compatible with v1.0 IMA technology has been in


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PDF IMA-32 M28529 M28529 32-port AF-PHY-0086 192Mbps AF-PHY-008 28529-BRF-001-A M03-0773 484-pin BGA M-0307 m285
2011 - zero crossing detector using psoc

Abstract: 5607
Text: shown in SONET/SDH and ATM Interface on page 3 and CY7B951 to PMC-Sierra PM5345 SUNI Connection Diagram , CY7B951 Local Area Network ATM Transceiver Local Area Network ATM Transceiver Features , : <65 mA 0.8 µBiCMOS Pb-free Packages Available SONET/SDH and ATM Compatible Compatible with , Functional Description The Local Area Network ATM Transceiver is used in SONET/SDH and ATM applications to , provide differential data buffering for the Transmit side of the system. Logic Block Diagram


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PDF CY7B951 24-pin PM5345 52-MHz 44-MHz 84-MHz 48-MHz zero crossing detector using psoc 5607
2000 - Not Available

Abstract: No abstract text available
Text: Product Flyer April 2000 MB86697A FireStreamTM155 ATM 155Mbps SAR Device The FireStream155 is a high performance ATM protocol controller which autonomously terminates ATM Adaptation Layer standard Type 5 (AAL5). ATM cells are received through a UTOPIA v2.01 compliant interface. Simultaneous segmentation and reassembly can be achieved at an average rate in excess of 155Mbps. All ATM Forum traffic classes (ABR, VBR, CBR, UBR) are supported with traffic management to ATM Forum TM4.0 specification on up


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PDF MB86697A FireStreamTM155 155Mbps FireStream155 155Mbps. FML/NPD/FS155/FL/2040 FML/NPD/FS155/FL/2040
2000 - HQFP240

Abstract: MB86697A CRC-10
Text: Product Flyer April 2000 MB86697A FireStreamTM155 ATM 155Mbps SAR Device Version 2.1 FML/NPD/FS155/FL/2040 The FireStream155 is a high performance ATM protocol controller which autonomously terminates ATM Adaptation Layer standard Type 5 (AAL5). ATM cells are received through a UTOPIA , rate in excess of 155Mbps. PLASTIC PACKAGE HQFP240 All ATM Forum traffic classes (ABR, VBR, CBR, UBR) are supported with traffic management to ATM Forum TM4.0 specification on up to 65536 virtual


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PDF MB86697A FireStreamTM155 155Mbps FML/NPD/FS155/FL/2040 FireStream155 155Mbps. HQFP240 FML/NPD/FS155/FL/2040 HQFP240 MB86697A CRC-10
1995 - MACH110

Abstract: TXC-05501 TXC-05601 Transwitch SARA-R 010ns
Text: 5.1. TRANSMIT INTERFACE CIRCUIT IMPLEMENTATION 5.1.1. TRANSMIT INTERFACE TIMING 5.2. RECEIVE INTERFACE CIRCUIT IMPLEMENTATION 5.2.1. RECEIVE INTERFACE TIMING 7 8 8 9 6. APPENDIX A 10 , . Scope This application note addresses the implementation of a circuit that enables the interface of the SARA chipset to a UTOPIA compliant device. The SARA device is considered an ATM Layer device , timing for the interface is discussed and the circuit implementation given. 2. Related Documents


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PDF TXC-05501-0002-AN MACH110 TXC-05501 TXC-05601 Transwitch SARA-R 010ns
2003 - CX2839

Abstract: CN8380 CX28398 IMA16 M28525
Text: (TC) Timing Circuit · ATM forum AF-PHY-0086.001 v1.1 and compatible with v1.0 · Supports UNI , IMA-16 Inverse Multiplexing for ATM M28525 16 Port IMA Solution for T1/E1 and DSL Applications , T1/E1 and DSL applications. > Single chip 16-port IMA solution > ATM forum AF-PHY-0086.001 v1 , software and support · Integrated differential delay memory · Support for 16 T1/E1 or DSL links · ATM , . End prod- Block Diagram ucts include: access concentrators, DSLAM's, 3G wireless, The block


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PDF IMA-16 M28525 16-port AF-PHY-0086 192Mbps M28525 M28525-BRF-001-A M03-0791 CX2839 CN8380 CX28398 IMA16
tin 612, 12 volt regulator

Abstract: No abstract text available
Text: integrated solution for ATM physical layers and SONET/SDH systems applications. VSC8110 Block Diagram , diagram on page 1 shows the major functional blocks associated with the VSC8110. The receive circuit , VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet ATM /SONET/SDH 155/622 Mb/s , external components • Compatible with industry ATM UNI devices • SONET/SDH frame recovery â , package • 8 bit parallel TTL interface General Description The VSC8110 is an ATM /SONET/SDH


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PDF VSC8110 STS-12/STM-4 1SD2331 G51011 tin 612, 12 volt regulator
Not Available

Abstract: No abstract text available
Text: LUC4AC01 ATM Crossbar Element (ACE) Introduction The ACE IC is part of the ATLANTA chip set consist ing , menting the ATM layer core of an ATM switch system. The chip set enables construction of high-perfor mance, feature-rich, and cost-effective ATM switches, scalable over a wide range of switching capacities. This document discusses the ACE device. Facilitates circuit board testing with on-chip IEEE* standard boundary , architecture of an ATM switch designed with the ATLANTA chip set. This document summarizes ATLANTA switch


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PDF LUC4AC01
1995 - ALI-25

Abstract: ALI-25C ALI-25T MACH110 MACH210 TXC-07025 txc 20MHz
Text: the clock is sent from the ATM Layer Protocol to the ALI-25C. 5.1. Transmit Interface Circuit , 7 5.1. TRANSMIT INTERFACE CIRCUIT IMPLEMENTATION 5.1.1. TRANSMIT INTERFACE TIMING 5.2. RECEIVE INTERFACE CIRCUIT IMPLEMENTATION 5.2.1. RECEIVE INTERFACE TIMING 7 9 9 10 6. APPENDIX A 11 , . Scope This application note addresses the implementation of a circuit that enables the interface of an ALI-25C to a UTOPIA compliant device. The timing for the interface is discussed and the circuit


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PDF ALI-25 TXC-07125-0001-AN ALI-25C ALI-25T MACH110 MACH210 TXC-07025 txc 20MHz
PE-67583

Abstract: Ericsson Core Network Packet MSC ERICSSON
Text: , B-ISDN ATM Adaptation Layer 1 Specification af-vtoa-0078.000, Circuit Emulation Service Interoperability , ERICSSON ^ October 1998 PBM 990 08/1MQ ATM Multi Service Chip Description The ATM Multi , for ADSL, VDSL, FTTx and HFC applications, where all services are transported over ATM . The chip , interfaces. The integrated services are ATM Forum 25.6 and POTS/ISDN. Other services such as Ethernet can be added via the Utopia interface. Circuit emulation via AAL1 is performed for the POTS/ISDN service


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PDF 08/1MQ 240-pin 1/1522-PBM PE-67583 Ericsson Core Network Packet MSC ERICSSON
Supplyframe Tracking Pixel