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Part Manufacturer Description Datasheet Download Buy Part
LTC6905CS5#TRM Linear Technology LTC6905 - 17MHz to 170MHz Resistor Set SOT-23 Oscillator; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C
LTC6905HS5#TRM Linear Technology LTC6905 - 17MHz to 170MHz Resistor Set SOT-23 Oscillator; Package: SOT; Pins: 5; Temperature Range: -40°C to 125°C
LTC6906HS6#TR Linear Technology LTC6906 - Micropower, 10kHz to 1MHz Resistor Set Oscillator in SOT-23; Package: SOT; Pins: 6; Temperature Range: -40°C to 125°C
LTC1799CS5#TRMPBF Linear Technology LTC1799 - 1kHz to 33MHz Resistor Set SOT-23 Oscillator; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C
LTC6907CS6#TRMPBF Linear Technology LTC6907 - Micropower, 40kHz to 4MHz Resistor Set Oscillator in SOT-23; Package: SOT; Pins: 6; Temperature Range: 0°C to 70°C
LTC1799CS5#PBF Linear Technology LTC1799 - 1kHz to 33MHz Resistor Set SOT-23 Oscillator; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C

ARM11 instruction sets Datasheets Context Search

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2002 - ARM11 instruction sets

Abstract: ARM Architecture Reference Manual ARM11 CP15 VFP11 ARM11 processor FMAC ARM11 Architecture Reference Manual
Text: synchronized with the ARM11 LS pipeline for the duration of the instruction . Data written to the ARM11 , appears to the ARM11 processor as a single-cycle instruction and is retired in the ARM11 processor , result of a floating-point compare instruction can be stored in the ARM11 condition code flags using the , instruction with an ARM11 CMP or CMN can be faster for simple comparisons. See Comparisons on page 3-7 , . 3-19 Instruction Execution 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Chapter 5 Loading


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PDF VFP11 0274B ARM11 instruction sets ARM Architecture Reference Manual ARM11 CP15 ARM11 processor FMAC ARM11 Architecture Reference Manual
2002 - ARM11 processor

Abstract: ARM11 CP15 VFP11 IEEE-754 ARM11 "instruction set summary" ARM11 Architecture Reference Manual ARM11 instruction sets ARMv5TE instruction set
Text: ARM11 pipeline. When the ARM11 processor is in the Issue stage for a particular VFP instruction , the , duration of the instruction . Data written to the ARM11 processor is read from the VFP11 coprocessor , the ARM11 processor as a single-cycle instruction and is retired in the ARM11 processor before it , floating-point compare instruction can be stored in the ARM11 condition code flags using the FMSTAT instruction , . Loading operands from ARM11 registers .


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PDF VFP11 ARM11 processor ARM11 CP15 IEEE-754 ARM11 "instruction set summary" ARM11 Architecture Reference Manual ARM11 instruction sets ARMv5TE instruction set
2008 - ARM11 processor block diagram

Abstract: ARM11 instruction sets ARM11 instruction set architecture ARM11 CIS scanner Quatro 4230 Zoran DDR2-400 laser printer high voltage diagram Zoran 4100
Text: the best embedded development tool sets available. To these proven ARM11 tools Zoran integrates a , , the 4230 combines an embedded ARM11 RISC CPU core and dual Quatro SIMD DSP cores for high quality , highperformance ARM11 CPU core · · · · PostScript/PCL printing at 20+ ppm color Raster/GDI printing at , copies per minute at 600 dpi · · · · · · · · · · · · · · 400 MHz ARM11 CPU core with , OEMs to meet the stringent interoperability requirements of their customers. The ARM11 CPU core


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PDF ARM11 01/08-MM ARM11 processor block diagram ARM11 instruction sets instruction set architecture ARM11 CIS scanner Quatro 4230 Zoran DDR2-400 laser printer high voltage diagram Zoran 4100
2006 - Not Available

Abstract: No abstract text available
Text: recognized as one of the best embedded development tool sets available. To these proven ARM11 tools Zoran , • 400 MHz ARM11 CPU core with MMU and FPU Programmable platform for deploying innovative , -400) Specialized imaging DSP cores paired with high-performance ARM11 CPU • 32-bit 66 MHz PCI interface , stringent interoperability requirements of their customers. The ARM11 CPU core delivers high-performance , key elements: • • • • ARM11 32-bit RISC CPU core Quatro 4-datapath SIMD DSP cores


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PDF ARM11â 03/06-MMCP 4230-PB-1
2006 - ARM11 processor

Abstract: ARM11 "instruction set summary" Arm1176 arm1136 ARM11 instruction sets ARM1176 processor TrustZone ARM11 ARM11 processor data sheet ARM1176 input
Text: the execution of a Wait For Interrupt instruction and the ARM11 processor signals it is in Standby , information of the ARM11 processor core is saved, the user executes a Wait For Interrupt instruction . The , Understanding ARM11 Processor Power Saving Modes Application Note 143 Released on: October 2007 ARM DAI 0143C Copyright © 2006, 2007. All rights reserved. 1 Understanding ARM11 , Modes on the ARM11 Processors This document describes the power management modes available on the ARM11


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PDF ARM11 0143C ARM1136 ARM1176 arm1136-dormantMode-example arm1136-shutdownMode-example arm1176-dormantMode-example arm1176-shutdownMode-example ARM11 processor ARM11 "instruction set summary" ARM11 instruction sets ARM1176 processor TrustZone ARM11 processor data sheet ARM1176 input
2006 - common features of ARM11

Abstract: ARM11 ARM11 instruction sets Quatro 4230 ARM11 processor block diagram ZORAN CPU PM-1100 Zoran 4201 4230 DDR2-400
Text: recognized as one of the best embedded development tool sets available. To these proven ARM11 tools Zoran , · 400 MHz ARM11 CPU core with MMU and FPU Programmable platform for deploying innovative features , -400) Specialized imaging DSP cores paired with high-performance ARM11 CPU · 32-bit 66 MHz PCI interface , interoperability requirements of their customers. The ARM11 CPU core delivers high-performance system and control , . Programmable Platform At the heart of the Quatro architecture are four key elements: · · · · ARM11 32


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PDF ARM11TM 07/06-MMCP 4230-PB-1 common features of ARM11 ARM11 ARM11 instruction sets Quatro 4230 ARM11 processor block diagram ZORAN CPU PM-1100 Zoran 4201 4230 DDR2-400
2005 - advantage zx6 user manual

Abstract: advantage zx6 manual TNY176 advantage zx6 tny175 ARM11 TNY179 advantage zx6 user manual how do you reset the system TNY178 ARM11 processor data sheet
Text: Core Tile for ARM11 MPCore TM TM HBI-0146 User Guide Copyright © 2005-2010 ARM Limited. All rights reserved. ARM DUI 0318F Core Tile for ARM11 MPCore User Guide Copyright © 2005-2010 , . All rights reserved. ARM DUI 0318F Contents Core Tile for ARM11 MPCore User Guide Preface , . 3-2 About the ARM11 MPCore test chip . , 3.10 3.11 Chapter 4 ARM11 MPCore test chip overview


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PDF ARM11 HBI-0146 0318F advantage zx6 user manual advantage zx6 manual TNY176 advantage zx6 tny175 TNY179 advantage zx6 user manual how do you reset the system TNY178 ARM11 processor data sheet
2002 - pl192

Abstract: ARM11 instruction sets PL190 ARM11 processor ARM11 ARM1026EJ-S ARM946E-S ARM966E-S ARM966E-S microcontroller 0xFFFF0018
Text: support for the ARM v6 processor VIC port, compatible with ARM11 and ARM1026EJ processors. 1.1.1 , asynchronous mode, enabling faster interrupt servicing when connected to an ARM11 or ARM1026EJ processor , instruction . Reading the VICADDRESS Register updates the hardware priority register of the interrupt , PrimeCell VIC provides direct support for the VIC port on the ARM11 and ARM1026EJ processors. This , , and to clear a nested interrupt: · the processor sets the VICIRQACK signal HIGH to indicate that


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PDF PL192) ARM966E-S, pl192 ARM11 instruction sets PL190 ARM11 processor ARM11 ARM1026EJ-S ARM946E-S ARM966E-S ARM966E-S microcontroller 0xFFFF0018
2003 - ARM11

Abstract: common features of ARM11 ARM11 processor ARM1136 ARM11 instruction sets ARM1136JF-S ARM1136J-S ETB11
Text: . 2-6 ARM11 MBIST Controller Instruction Register 3.1 3.2 Appendix A Overview , ARM11 MBIST Controller. Chapter 3 ARM11 MBIST Controller Instruction Register Read this chapter for a description of the ARM11 MBIST Controller Instruction Register and associated bit assignments. Appendix A , uses a 40-bit instruction to control its operation. This is described in Chapter 3 ARM11 MBIST , . 2.1.2 Instruction load Figure 2-1 shows the method used to load an instruction into an ARM11 MBIST


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PDF ARM11 0289B common features of ARM11 ARM11 processor ARM1136 ARM11 instruction sets ARM1136JF-S ARM1136J-S ETB11
2006 - ARM11 mpcore

Abstract: T1Z20 Z214 T1Z207 ARM11 ARM11 instruction sets ARM11 Architecture Reference Manual CT11MPCore Z203 T1Z200
Text: dedicated I/O such as an interrupt signal Wait For Interrupt This ARM11 MPCore instruction makes the CPU , controller registers and includes example software. The current MPCore platform is an ARM11 MPCore Core , an Interrupt Distributor, which allocates interrupts to one or more of its CPUs. Figure 1 ARM11 MPCore block diagram For more information about this diagram see the ARM11 MPCore technical reference , interrupt controller is inside the ARM11 MPCore. The GIC in this test chip was implemented for 4 CPUs, with


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PDF 0176C CT11MPCore ARM11 ARM11 mpcore T1Z20 Z214 T1Z207 ARM11 instruction sets ARM11 Architecture Reference Manual Z203 T1Z200
MB86H60

Abstract: ARM11 hs spi 4x 4 keypad to 7 segment ARM11 processor block diagram ARM 7 processor pin configuration RGB888 HDMI Rx OSD scaler schematics dvb decoder ARM1176JZF-S ARM1176JZF-STM
Text: , ARM's Jazelle® technology and Thumb® instruction set extensions for compact code. The ARM11 provides , FACTSHEET MB86H60 HD MULTI-STANDARD DECODER HD MULTI-STANDARD DECODER Highly integrated SoC for HDTV receivers SPDIF 4x I2S JTAG HD L/R Stereo DAC ARM11 @ 324MHz Digital RGB Audio Decoder Processor Cache MMU HD Video Decoder MPEG-1/2 L1, 2, 3 MPEG-2/4 AAC , graphics - ideal for IDTV sets and set-top boxes. The MB86H60 incorporates the high performance ARM


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PDF MB86H60 ARM11 324MHz ITU-R656 ISO7816 ARM1176JZF-S FME-M16-0508 MB86H60 ARM11 hs spi 4x 4 keypad to 7 segment ARM11 processor block diagram ARM 7 processor pin configuration RGB888 HDMI Rx OSD scaler schematics dvb decoder ARM1176JZF-STM
2004 - ETM11

Abstract: AMBA AXI to APB BUS Bridge verilog code ARM11 processor ARM11 "instruction set summary" ARM11 mpcore ARM11 coresight CoreSight Architecture Specification ihi 0029 ARM1176 input
Text: Parallel instruction execution . 2-21 , ASIC that includes an ARM11 processor. These users can also consult the CoreSight ETM11 Integration , CoreSight ETM11 can be used stand-alone, that is, without a CoreSight subsystem, to trace a single ARM11 , Introduction 1.1 About CoreSight ETM11 CoreSight ETM11 provides instruction trace and data trace for the ARM11 family of microprocessors. CoreSight ETM11 supports all current ARM11 cores and is compatible


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PDF ETM11 0318E Glossary-10 ETM11 AMBA AXI to APB BUS Bridge verilog code ARM11 processor ARM11 "instruction set summary" ARM11 mpcore ARM11 coresight CoreSight Architecture Specification ihi 0029 ARM1176 input
2013 - ARM11 processor block diagram

Abstract: ARM11 processor NFP-3240
Text: . Paired microengines provide 16k word shared instruction stores for run-to-completion or pool-ofthreads programming model Integrated ARM11 , L1 cache (32 KB instruction cache, 32 KB data cache) plus L2 cache , each running up to 1.6 GHz • High-performance 32-bit ARM11 , plus L2 cache, for processing complex , Interface 6.25 GHz per lane (each of the 4 lanes supports 3.125-6.375 GHz operation) ARM11 Core , : ME Vdd Voltage 1.125 V ± 3% ARM11 Core Vdd Voltage 1.5 V ± 3% Memory I/O Voltage 1.5


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PDF SiNFP-32xx IXP28XX Mpps/20 70-million 64-byte SiNFP-3224-0-A2-BM10 SiNFP-3224-0-A2-CM10 SiNFP-3224-0-A2-DM10 SiNFP-3224-8-A2-AM10 SiNFP-3224-8-A2-BM10 ARM11 processor block diagram ARM11 processor NFP-3240
2007 - ARM DDI 0254

Abstract: PEX8114 arm11 nxp Z123 Diode PB11MPCore DVI-D Single Link Male Connector pinout 49mhz remote control transmitter circuit ARM11 ARM1176 Y12878
Text: RealView Platform Baseboard for ARM11 MPCore ® HBI-0159 HBI-0175 HBI-0176 User Guide , ARM11 MPCore User Guide Copyright © 2007-2010 ARM Limited. All rights reserved. Release Information , Baseboard for ARM11 MPCore User Guide Preface About this book , . 3-10 ARM11 MPCore test chip , ARM11 MPCore test chip overview . 5-2 Clocks


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PDF ARM11 HBI-0159 HBI-0175 HBI-0176 0351D ARM1176JZF-S ARM DDI 0254 PEX8114 arm11 nxp Z123 Diode PB11MPCore DVI-D Single Link Male Connector pinout 49mhz remote control transmitter circuit ARM1176 Y12878
ARM1156T2F-S

Abstract: AMBA AXI ARM1026EJ-S thumb2 instruction set arm11 dac adc
Text: test chip, the first silicon to implement the Thumb-2 instruction set. This device is based around a hardened ARM1156T2F-S CPU running at up to 360MHz. The ARM11 56T2F-S test chip has a 64-bit AXI master , 16KB instruction and data caches 64KB instruction and data TCMs ETM11CS and ETB11 CPU, caches and , ARM11 MPCore x4 MMU, Jazelle, arch v6 SMP 32KB I and D 1MB shared 200MHz CT1156T2F-S ARM1156T2F-S MPU , , ARM946E-S, ARM966E-S, ARM1020E, ARM1022E, ARM1026EJ-S, ARM11 , ARM1136J -S, ARM1136JF-S, ETK11, ETM, ETM7


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PDF ARM1156T2F-S CT1156T2F-S. CT1156T2F-S AMBA AXI ARM1026EJ-S thumb2 instruction set arm11 dac adc
2007 - arm1176

Abstract: ARM1136 ARM11 instruction sets ARM11 arm1176 reset ARM1136 confidential
Text: Application Note 199 ARM11 core simulation guidelines Document number: ARM DAI 199A Issued , . Open Access Application Note 199 ARM11 core simulation guidelines Copyright © 2007 ARM Limited , simulations in some circumstances (depending on the instruction sequence), so the recommended approach is to , two read ports of the ALU are uninitialized until used by an ALU instruction , so an ADD instruction , reset. The routine sets the Z bit and initialises the return stack entries by the use of three BL


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PDF ARM11 0x800 DAI0199A arm1176 ARM1136 ARM11 instruction sets arm1176 reset ARM1136 confidential
CNS3420

Abstract: CNS3410 RGMII to PCIe USB2.0 video controller BT656 ARM11 PCIe PHY ARM11 mpcore PCIe BT.656 sata phy block diagram of floating point dsp processors
Text: starting at less than 1 Watt. With up to two high-performance ARM11 cores and high-level of integration , ARM11 cores, 300 ­ 700 MHz, SMP support · Integrated support for DSP, Floating Point and Memory , Instruction and Data cache - 256K of L2 cache - Advanced cache coherency schemes Market leading , 1.7Gbps of IPSec and SSL · Up to 16 channels of G.729 voice support · Over 90% of a single ARM11 CPU , integration with best-of-breed 3rd party applications CNS3XXX - Block Diagram ARM11 MPCore DSP / VFP


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PDF ARM11 HSBGA-484 CNS3420 CNS3410 RGMII to PCIe USB2.0 video controller BT656 PCIe PHY ARM11 mpcore PCIe BT.656 sata phy block diagram of floating point dsp processors
2005 - arm11 benchmark

Abstract: arm11 fft ARM11 "instruction set summary" ARM11 atmel ARM11 AVR32 ARM926EJ-S architecture and programming ARM1136JF-S ARM926EJ difference arm9 arm11
Text: , such as SAD and iDCT, the AVR32 achieves 35% more throughput per instruction cycle than an ARM11 , milliwatts of power per second while doing so. The ARM11TM core, which includes Single Instruction Multiple , solution would be a new processor architecture with an instruction set that supports single-cycle , . Performing these operations on multiple data simultaneously (Single Instruction Multiple Data or SIMD , operation to complete before issuing a new instruction , the other resources in the pipeline will be


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PDF 32-bit AVR32 arm11 benchmark arm11 fft ARM11 "instruction set summary" ARM11 atmel ARM11 AVR32 ARM926EJ-S architecture and programming ARM1136JF-S ARM926EJ difference arm9 arm11
2007 - ARM11 processor

Abstract: ARM1176 ARM1156 ARM11 CP15 L210 ARM-11
Text: ARM11 PMU counts, since there is not a 1:1 correlation between counters. The number of L1 instruction , Application Note 195 ARM11 performance monitor unit Document number: ARM DAI 195B Issued: 15th , Access Application Note 195 ARM11 performance monitor unit Copyright © 2007 ARM Limited. All rights , . 2 3. Event 0x0: Instruction cache miss , Performance Monitor Registers 1. Performance Monitor Registers The ARM11 family of processors contain


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PDF ARM11 ARM11 processor ARM1176 ARM1156 CP15 L210 ARM-11
2012 - mindspeed femtocell

Abstract: ARM1176EJ pc3x PICOCHIP PC5300 ARM11 datasheet
Text: baseband, ARM11 processor, cryptographic engine, high-speed accelerators, and peripherals to support HSPA , DMA Controller 2 AXI Instruction AXI Data APB AXI Data Timer WatchDog Timer TRNG IPSEC , cell-FACH) Pin Compatible with PC302/PC312 and PC333 Glueless RF interface High performance 700MHz ARM11 , consists of a ARM11 processor 3GPP NodeB PHY, cryptographic engine, high-speed accelerators, and , ) processing. The PC323 ARM11 sub-system has been architected to aid RNC stack processing, security and the


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PDF PC323 ARM11 PC323-BRF-0012-A mindspeed femtocell ARM1176EJ pc3x PICOCHIP PC5300 ARM11 datasheet
2002 - arm9 processor architecture

Abstract: arm processor CP15 ARM946E-S ARM940T ARM926EJ-S ARM922T ARM920T ARM720T ARM1136J-S
Text: Instruction Coprocessor 15 ­ Register 0 ID code and shadow registers opcode_2 ARM720T 0 ID code register ARM920T 0 ID code register 1 Shadow register ­ Instruction & Data Cache type & size 0 ID code register 1 Shadow register ­ Instruction & Data Cache type & size 0 ID code register 1 Shadow register ­ Instruction & Data Cache type & size 0 ID code register 1 Shadow register ­ Instruction & Data Cache type & size 2 Shadow register ­ Tightly Coupled RAM type


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PDF 0099C ARM1136J-S ARM1136FJ-S owneARM720T IEEE1149 arm9 processor architecture arm processor CP15 ARM946E-S ARM940T ARM926EJ-S ARM922T ARM920T ARM720T ARM1136J-S
2009 - M83241

Abstract: M83261G-11 M83263G-11 M83263 M83241G-11 M83261 M83160G-11 M83262G M83261G m83241g
Text: , 533MHz, and 650MHz - ARMv6 architecture compatible, supporting ARM, Thumb, and Java instruction sets , the Comcerto 1000 family of processors includes single and dual ARM11 core devices from 450MHz to , leveraging ARM's leadership and experience in the handheld market - DSP instruction set extensions (including MAC ops) ·· High-performance coherent memory subsystem - 64KB data + 64KB instruction caches


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PDF 650MHz) M83xxx-BRF-001-G M83241 M83261G-11 M83263G-11 M83263 M83241G-11 M83261 M83160G-11 M83262G M83261G m83241g
CMOS Camera Module connector

Abstract: arm11 nxp sharp CMOS Camera Module ARM11 ARM926EJ-S AC97 PCM-038-0010REU mmc sd LCD-004 sharp LCD
Text: i.Evolution with i.MX27 Development Board with phyCORE-i.MX27 i.Evolution is the first low cost universal modular development board supporting Freescale's i.MX31 ( ARM11 ) and i.MX27 (ARM9) product family on same mother board. The full featured Base Board, included in the Kit, can be used with all , sets of the i.MX controllers some circuits on the baseboard can be bypassed. *Only a subset of , complete cable set power supply Tool CD QuickStart Instruction Every Kit includes Windows Embedded


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PDF ARM11) KPCM-038-Silica PCM-038-0010REU CMOS Camera Module connector arm11 nxp sharp CMOS Camera Module ARM11 ARM926EJ-S AC97 PCM-038-0010REU mmc sd LCD-004 sharp LCD
2012 - PICOCHIP

Abstract: Rake search accelerator IEEE1588 phy DesignWare SPI PC312
Text: functions to support zero-touch femtocell provisioning or OEM specific code High performance ARM11 , .820). The PC312 consists of a 3GPP NodeB PHY, ARM11 processor, cryptographic engine, highspeed , AXI Instruction AXI Data APB DL Sample PC312 Viterbi AXI2Pico2 UART picoBus , stack running on the integrated ARM11 sub-system. The API interface provides Iub FP framed data , . Figure 1 shows the software stacks needed to execute on the ARM11 to implement a TR25.820 compliant FAP


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PDF PC312 14Mbps ARM11 ARM1176JZ-S 400MHz PC312-BRF-0012-A PICOCHIP Rake search accelerator IEEE1588 phy DesignWare SPI
1986 - TAG 8926

Abstract: Lpg 899 SDC 2921 TF 6221 HEN LED display 12V+RELAY+1+C/8 pin ic sdc 3733
Text: 8-9 ARM11 Instruction and Data Caches (L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , ARM Powered logo are registered trademarks of ARM Limited. ARM1136JF-S, ARM11 , Embedded Trace Kit , . . . . . . . 1-5 1.2.2 ARM11 Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . 1-7 1.2.8 Applications Processor ( ARM11 Core) . . . . . . . . , : ARM11 Core and Interrupts Chapter 8 ARM11 Platform 8.1 8.1.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5


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PDF MCIMX31 MCIMX31L MCIMX31RM IOIS16 IOIS16/WP MCIMX31L TAG 8926 Lpg 899 SDC 2921 TF 6221 HEN LED display 12V+RELAY+1+C/8 pin ic sdc 3733
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