The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC1706EMS-61 Linear Technology LTC1706-61 - 5-Bit VID Voltage Programmer for AMD Opteron CPUs; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LTC1753CSW Linear Technology LTC1753 - 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium® II Processor; Package: SO; Pins: 20; Temperature Range: 0°C to 70°C
LTC3733CUHF-1 Linear Technology LTC3733 - 3-Phase, Buck Controllers for AMD CPUs; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C
LTC1706EMS-63#PBF Linear Technology LTC1706-63 - 5-Bit VID Voltage Programmer for Sun CPUs; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
LTC3733CG#TRPBF Linear Technology LTC3733 - 3-Phase, Buck Controllers for AMD CPUs; Package: SSOP; Pins: 36; Temperature Range: 0°C to 70°C
LTC3733CUHF-1#TR Linear Technology LTC3733 - 3-Phase, Buck Controllers for AMD CPUs; Package: QFN; Pins: 38; Temperature Range: 0°C to 70°C

ARM processor history Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2013 - Not Available

Abstract: No abstract text available
Text: extended commercial temperature grade . . . . . . . . . . . . . . . . . . . .3 Revision history . . . . . , Specifically, each processor has the ability to generate unique operating conditions depending upon the use , device which contains the processor . These conditions and assumptions on processor qualification level help define the expected active usage time of the processor . This document is intended to provide users with guidance on the duty cycle mix available to the processor to achieve a given maximum active


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PDF AN4726
2013 - Not Available

Abstract: No abstract text available
Text: .4 1.4 Industrial temperature grade . . . . . . . . . . . .5 Revision history . . . . . . . . . . . , , each processor has the ability to generate unique operating conditions depending upon the use case , which contains the processor . These conditions and assumptions on processor qualification level help define the expected active usage time of the processor . This document is intended to provide users with guidance on the duty cycle mix available to the processor to achieve a given maximum active usage. Each


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PDF AN4725
2013 - Not Available

Abstract: No abstract text available
Text: . .4 1.4 Industrial Temperature Grade . . . . . . . . . . . .5 Revision History . . . . . . . . . , , each processor has the ability to generate unique operating conditions depending upon the use case , which contains the processor . These conditions and assumptions on processor qualification level help define the expected active usage time of the processor . This document is intended to provide users with guidance on the duty cycle mix available to the processor to achieve a given maximum active usage. Each


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PDF AN4724
2005 - jazelle

Abstract: ARM926EJ-S ARM926EJ CP15 ARM926EJ-STM
Text: for improved DSP performance. The ARM926EJ-S processor supports the ARM debug architecture and , Features · ARM9EJ-S Based on ARM ® Architecture v5TEJ with Jazelle® Technology · Three Instruction Sets · · · · · · · · · ­ ARM ® High-performance 32-bit Instruction Set ­ , Implemented ARM926EJ-STM Processor Overview 6128AS­ATARM­11-Apr-05 Note: This is a summary document , ­ Makes System Architecture Mode Flexible 1. Description The ARM926EJ-STM processor is a member


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PDF 32-bit 16-bit 6128AS 11-Apr-05 jazelle ARM926EJ-S ARM926EJ CP15 ARM926EJ-STM
2000 - gps MTK command

Abstract: Basic ARM block diagram sirfstar II arm gsm MTC-30585 arm gsm GPS qualcomm chipsets at command qualcomm chipsets "at command" gsm modem with arm GSP2E
Text: Processor 7TDMI ARM Development Systems Available Today Several products that use Xilinx FPGAs and , White Paper: FPGAs R Using FPGAs with ARM Processors Author: Brant Soudan WP123 (v1.1) August 18, 2000 Summary This white paper discusses interfacing Xilinx FPGAs with off-the-shelf ARM processors. It covers some of the available ARM Application Specific Standard Products (ASSPs) and describes some of the Xilinx plus ARM development systems currently available for engineers to evaluate


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PDF WP123 CLK90 CLK180 CLK270 com/xapp/xapp132 gps MTK command Basic ARM block diagram sirfstar II arm gsm MTC-30585 arm gsm GPS qualcomm chipsets at command qualcomm chipsets "at command" gsm modem with arm GSP2E
2007 - Sony Imx 224

Abstract: IMX 224 Sony sony cmos sensor imx 222 freescale JTAG arm926 pinout i.MX27 HOW TO INTERFACE BP SENSOR TO ARM PROCESSOR Sony Imx 224 cmos sony IMX 222 sony IMX FS453 sony IMX 222 cmos
Text: i.MX27 processor is based on the ARM architecture. With high-frequency operation, the AP achieves , Document Revision History Table 1. i.MX27 Multimedia Applications Processor Digital and Analog Modules , Product Brief Multimedia Applications Processor The i.MX27 Multimedia Applications Processor , applications, the i.MX27 Multimedia Applications Processor provides design performance to spare, a high , Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Revision History . . . .


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PDF MCIMX27PB ARM926EJ-S Sony Imx 224 IMX 224 Sony sony cmos sensor imx 222 freescale JTAG arm926 pinout i.MX27 HOW TO INTERFACE BP SENSOR TO ARM PROCESSOR Sony Imx 224 cmos sony IMX 222 sony IMX FS453 sony IMX 222 cmos
2010 - emmc "boot mode"

Abstract: 8x8 keypad Encoder IC imx255 emmc emmc boot mx257 eMMC 4.5 freescale arm processor I.MX25 i.mx258 keypad 8x8
Text: i.MX27 processor according to the i.MX25 SDMA requirements. 5 Revision History Table 2 provides , The i.MX family has a few ARM 9 microprocessors. Among them, the most widely used is the i.MX27 processor and, one of the latest is the i.MX25 processor . This application note describes both these i.MX , . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . , i.MX27 processor . Figure 1. i.MX27 Block Diagram The features of the i.MX27 processor are as


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PDF AN3999 MX27L. emmc "boot mode" 8x8 keypad Encoder IC imx255 emmc emmc boot mx257 eMMC 4.5 freescale arm processor I.MX25 i.mx258 keypad 8x8
2008 - arm processor

Abstract: ntrst AT91SAM
Text: from the ARM Processor ­ Interrupt Generation Chip ID Registers ­ Identification of the Device , Prevent System Access Through the ARM Processor 's ICE ­ Prevention is Made by Asserting the NTRST Line of the ARM Processor 's ICE 32-bit Embedded ASIC Core Peripheral Debug Unit (DBGU) Summary 1 , Communication Channel (DCC) signals provided by the In-circuit Emulator of the ARM processor visible to the , to the ARM processor , making possible the handling of the DCC under interrupt control. Chip


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PDF 6059CS 23-Oct-08 arm processor ntrst AT91SAM
2009 - armv7-a

Abstract: ARMv7-M Architecture Reference Manual ARMv7 ARMv6 ARM processor history ARMv6 Architecture Reference Manual ARM processor ARMv7 Architecture Reference Manual ARM processor Armv4 instruction set architecture ARm cortexA9 GPIO
Text: 1.4 1.5 ARM DHT 0001A Unrestricted Access The ARM processor business model , contains the following sections: · The ARM processor business model on page 1-2 · Architecture on page 1-3 · Processor on page 1-5 · Device on page 1-6 · Putting it all together on page 1-8. ARM , 1-1 Architectures, Processors, and Devices 1.1 The ARM processor business model ARM does not manufacture processor hardware. Instead, ARM creates microprocessor designs that are licensed to


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2012 - Not Available

Abstract: No abstract text available
Text: i.MX 6SoloLite Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 , History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Overview of i.MX 6SoloLite Voltage , Measurement of the i.MX 6SoloLite Processor NOTE See the i.MX 6SoloLite datasheet, for the recommended , (IMX6SLRM). 2 Internal Power Measurement of the i.MX 6SoloLite Processor Several use cases , are taken mainly for the following power supply domains—VDDARM_IN, which is the ARM platform’s


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PDF AN4580
1995 - arm processor

Abstract: AGNT001 AGNT002 AREQ001 AREQ002 ARM processor history arbiter decoder -1996
Text: Description AGNTARM Out Grant signal to the ARM processor . When HIGH, this signal indicates that the , ARM processor indicating that it requires the bus. This signal must be set up to the falling edge of , the processor to be active. Note In systems that only have the ARM and the Test Interface , AMBA Arbiter Data Sheet Copyright © 1995-1997 ARM Limited. All rights reserved. ARM DDI 0041C AMBA Arbiter Data Sheet Copyright © 1995-1997 ARM Limited. All rights reserved. Release Information


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PDF 0041C arm processor AGNT001 AGNT002 AREQ001 AREQ002 ARM processor history arbiter decoder -1996
2010 - history honour

Abstract: BE32 ARM DS-5
Text: names. Also used for emphasis in descriptive lists, where appropriate, and for ARM ® processor signal , ARM DS-5 ® TM Version 5.2 Using the Debugger Copyright © 2010 ARM . All rights reserved. ARM DUI 0446B (ID100410) ARM DS-5 Using the Debugger Copyright © 2010 ARM . All rights reserved. Release Information The following changes have been made to this book. Change History Date Issue , or trademarks of ARM in the EU and other countries, except as otherwise stated below in this


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PDF 0446B ID100410) ID100410 history honour BE32 ARM DS-5
2007 - sony IMX 222

Abstract: sony IMX cmos Sony Imx 224 sony cmos sensor imx 222
Text: , the application processor in the i.MX27 processor is based on the ARM architecture. With , Product Brief Multimedia Applications Processor The i.MX27 multimedia applications processor , applications, the i.MX27 multimedia applications processor provides design performance to spare, a high , Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Revision History . . . . . , Application Examples The flexibility of the i.MX27 multimedia applications processor architecture enables


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PDF MCIMX27PB ARM926EJ-S sony IMX 222 sony IMX cmos Sony Imx 224 sony cmos sensor imx 222
2006 - ARM processor

Abstract: ntrst
Text: from the ARM Processor ­ Interrupt Generation Chip ID Registers ­ Identification of the Device , Prevent System Access Through the ARM Processor 's ICE ­ Prevention is Made by Asserting the NTRST Line of the ARM Processor 's ICE 32-bit Embedded ASIC Core Peripheral Debug Unit (DBGU) Summary 1 , Debug Communication Channel (DCC) signals provided by the In-circuit Emulator of the ARM processor , generate an interrupt to the ARM processor , making possible the handling of the DCC under interrupt


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PDF 6059BS 12-Jun-06 ARM processor ntrst
2011 - 6206a

Abstract: J-LINK GDB SERVER 20 pin JTAG CONNECTOR Atmel SAM-ICE
Text: causes the processor to call a programer-specified subroutine. Used by ARM ® to handle semihosting. TAP , . 2-1 Debugging Multiple ARM ® Cores with SAM-ICE , .1. 8-1 Section 9 Revision History . 9-1 9.1 AT91SAM-ICE User Guide Revision History , Overview SAM-ICE is a JTAG emulator designed for Atmel® AT91 ARM ® cores. It connects via USB to a PC


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PDF AT91SAM-ICE 6206C 13-Feb-12 AT91SAM-ICE 6206a J-LINK GDB SERVER 20 pin JTAG CONNECTOR Atmel SAM-ICE
2001 - SIMPLE SCROLLING LED DISPLAY verilog

Abstract: EPXA10 design of UART by using verilog ARM922T R0-R12 verilog code arm processor Copyright C Altera Corporation 2000-2001 excalibur Board altera board
Text: This document describes a simple hello_world.c program for the Altera® ARM ®-based embedded processor , when developing code for a new processor . A successful build and execution on the processor validates , device. For the ARMbased embedded processor PLDs, a successful build and execution also validates the , applications. Refer to "Revision History " on page 37 to see the changes made for this version of the document , Quartus® II software version 2.0 ARM Developer Suite for Altera (ADS-Lite) software version 1.1 EPXA10


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2005 - HSYNC GENERATE PIXEL CLOCK

Abstract: cmos sensor abstract AN2413 MC9328MX1 MC9328MXL MC9328MXS ARM processor history
Text: Situation . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . 1 2 2 , Edge Generation The pixel clock from the i.MX processor 's CSI module is continuous. The pixel clock , i.MX processor , these two signals are ANDed to generate valid pixel clock edges. Data is latched into , sensor, not the i.MX processor . There are two factors affecting the amount of drift allowed: · Relative , processor . This inhibits PIXCLK when HSYNC is low and is a more robust solution than either solution 1 or 2


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PDF AN2413 MC9328MX1, MC9328MXL, MC9328MXS HSYNC GENERATE PIXEL CLOCK cmos sensor abstract AN2413 MC9328MX1 MC9328MXL MC9328MXS ARM processor history
2012 - 1 to 2 MIPI buffer IC

Abstract: bt.656 to MIPI ttl to mipi MIPI DSI to RGB STPP0100 STPP0101 RGB MIPI 4 lanes STPP0101-AA "head up display" camera interface with arm microcontroller
Text: processor ­ Image scaler ­ Color space conversion ­ Image color adjustment ­ Geometrical compensation ARM , . MIPI Video Decoder Video Buffer Image Processing RBG ADC Secondary Bus I2C Master ARM CORE , , integrated video processor and application controllers designed for laser pico-projection systems and HD , input support Arm Cortex M3 Low power in mission mode (<375 mW typical for 720p) Low power MIPI standby , bits Supporting MEMS mirrors Integrated mirror/lasers Analog Front End (AFE) Integrated ARM Cortex-M3


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PDF STPP0100, STPP0101 24-bit 1 to 2 MIPI buffer IC bt.656 to MIPI ttl to mipi MIPI DSI to RGB STPP0100 STPP0101 RGB MIPI 4 lanes STPP0101-AA "head up display" camera interface with arm microcontroller
2008 - 6206a

Abstract: Atmel SAM-ICE ARM at91sam jlink 6206A datasheet multi-ice interface unit idc 20 pin data ribbon connector 6206a 4 pin arm9 pinout AT91SAM-ICE
Text: causes the processor to call a programer-specified subroutine. Used by ARM ® to handle semihosting. TAP , . 2-1 Debugging Multiple ARM ® Cores with SAM-ICE , .1. 8-1 Section 9 Revision History . 9-1 9.1 ii 6206B­ATARM­04-Mar-08 AT91SAM-ICE User Guide Revision History , emulator designed for Atmel® AT91 ARM ® cores. It connects via USB to a PC running Microsoft Windows2000 or


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PDF AT91SAM-ICE 6206B 04-Mar-08 AT91SAM-ICE 6206a Atmel SAM-ICE ARM at91sam jlink 6206A datasheet multi-ice interface unit idc 20 pin data ribbon connector 6206a 4 pin arm9 pinout
2010 - MX513

Abstract: MCIMX51 MX51-B 0x1FFE0000 0xFA100000 IMX51 IMX51* application note
Text: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Linux Booting Process , section describes the main objectives of the bootloader of a Linux system for an ARM device. It also , objectives of a Linux bootlader for ARM devices. There are five minimum elements that a bootloader needs to , depends on the processor and bootloader designs. 2. Initialize serial port (optional, but highly , type-The bootloader detects the type of the processor that is running on the system. This information is a


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PDF AN3980 MX513 MCIMX51 MX51-B 0x1FFE0000 0xFA100000 IMX51 IMX51* application note
1998 - ARM DDI 0062

Abstract: 300D pid code assembler
Text: the Angel Debug Agent. Application Note 54 2 ARM DAI 0054A Open Access Angel History 2 Angel History ARM initially designed and distributed the sources and images for a host resident debug , to initialize the MMU of an ARM 610 processor which includes MMU and cache. You must take care when , Application Note 54 Angel Porting Guide Document number: ARM DAI 0054A Issued: January 1998 Copyright Advanced RISC Machines Ltd ( ARM ) 1998 ENGLAND GERMANY Advanced RISC Machines Limited


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2002 - ESPC

Abstract: ETM10 ARM966E-S ARM946E-S ARM940T ARM926EJ-S ARM922T ARM920T ARM1022E ARM1020E
Text: cross-references, and citations. Highlights interface elements, such as menu names. Denotes ARM processor signal , , conversion from ARM AXD and armsd, and history lists to record previous actions. · Users can access a , @top_of_memory register. Note If you are using the default ARMulator to simulate an ARM processor , this is not , RealView Debugger TM Version 1.6.1 Essentials Guide Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DUI 0181D RealView Debugger Essentials Guide Copyright © 2002, 2003


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PDF 0181D 0181C ESPC ETM10 ARM966E-S ARM946E-S ARM940T ARM926EJ-S ARM922T ARM920T ARM1022E ARM1020E
2002 - ARM940T

Abstract: ETB11 ZSP400 ZSP500 dhrystone
Text: , such as menu names. Denotes ARM processor signal names. Also used for terms in descriptive lists , RealView Debugger ® Version 3.0 Essentials Guide Copyright © 2002-2006 ARM Limited. All rights reserved. ARM DUI 0181H RealView Debugger Essentials Guide Copyright © 2002-2006 ARM , . Change History Date Issue Change April 2002 A RealView Debugger v1.5 release September , registered trademarks or trademarks owned by ARM Limited. Other brands and names mentioned herein may be the


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PDF 0181H ARM940T ETB11 ZSP400 ZSP500 dhrystone
2009 - ARMv6-M

Abstract: ARMv6-M Architecture Reference Manual actrl fpga loader
Text: Introduction 1. Introduction The ARM Cortex-M1 processor was developed for use with FPGAs (Field , number: ARM DAI 0222A Issued: 4th June, 2009 Copyright ARM Limited 2009 Copyright 2009 ARM Limited , Considerations for System Designers Copyright © 2009 ARM Limited. All rights reserved. Release information Change history Date Issue Change June 2009 A First release Proprietary notice Words and logos marked with and are registered trademarks owned by ARM Limited, except as otherwise


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2010 - IMX51CEC

Abstract: Cortex-A8 video audio stream MC13892 registers IMX51 sd card IMX51AEC imx51 EVK AN4051 audio echo H.264 encoder chip
Text: Benchmark) In this use case, Dhrystone test is performed on an OS-less environment. The ARM processor , Internal Power Measurement of the i.MX51 Processor 3 Use Cases and Measurement Results . . . . . . . . . . , . . . . . . . . . . . . . . .16 5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . , 1.0 for Automotive 1.1 for Consumer Absolute Maximum (mA)2 VDDGP ARM core supply voltage , Measurement of the i.MX51 Processor Table 1. i.MX51 Supplies (continued) Supply Name Description


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PDF AN4051 IMX51CEC Cortex-A8 video audio stream MC13892 registers IMX51 sd card IMX51AEC imx51 EVK AN4051 audio echo H.264 encoder chip
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