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Part Manufacturer Description Datasheet Download Buy Part
TW6865-TA1-CRH Intersil Corporation 4-in-1 Video Decoders with PCI Express Media Bridge; TQFP144; Temp Range: See Datasheet
TW6869-TA1-CR Intersil Corporation 8-in-1 Video Decoders with PCI Express Media Bridge; TQFP144; Temp Range: See Datasheet
TW6869-TA1-CRH Intersil Corporation 8-in-1 Video Decoders with PCI Express Media Bridge; TQFP144; Temp Range: See Datasheet
TW6865-TA1-CR Intersil Corporation 4-in-1 Video Decoders with PCI Express Media Bridge; TQFP144; Temp Range: See Datasheet
XIO2221ZAY Texas Instruments PCI Express™ To 1394b OHCI With 1-Port PHY 167-NFBGA 0 to 70
TSB12LV22PZ Texas Instruments PCI-to-1394 Host Controller (OHCI-Lynx) 100-LQFP

AGP Host to PCI Bridge Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1997 - "full hd" mobile phone camera pinout

Abstract: Intel Pentium 82443DX 82443ZX 443ZX 82443dx 82443BX 82371EB 440ZX 82443zX hard disk MB63H
Text: request queuing for all three interfaces ( Host , AGP and PCI ). Host-initiated I/O cycles are decoded to , AGP address map. 1-2 82443ZX Host Bridge Datasheet Architectural Overview PCI and AGP , at 66MHz/100MHz, PCI at 33 MHz and AGP at 66/133 MHz. 82443ZX Host Bridge Datasheet 1-3 , Reads - Supports concurrent CPU, AGP and PCI transactions to main memory · AGP interface · · , Supports concurrent CPU, AGP and PCI transactions to main memory - AGP high-priority transactions


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PDF 440ZX 82443ZX "full hd" mobile phone camera pinout Intel Pentium 82443DX 443ZX 82443dx 82443BX 82371EB 82443zX hard disk MB63H
Not Available

Abstract: No abstract text available
Text: , AGP and PCI transactions to main memory • • — Supports single AGP compliant device , Functions — Stop Clock Grant and Halt special cycle translation ( host to PCI Bus) — Mobile and , Configuration Accesses to PCI or AGP .3-5 3.2.3 PCI Bus Configuration Mechanism Overview , MHz/3.3V supporting only a single PCI agent. The 82443BX is designed to support the PIIX4E I/O bridge , - VMI - Video Capture 2X AGP Bus Graphics Device 66/100 MHz 82443BX Host Bridge


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PDF 440BX 82443BX 04565-001-Sao USA/0498/PSA
1997 - AGP Host to PCI Bridge

Abstract: commands pci controller pci target gart
Text: addresses to the PCI target of a A.G.P . compliant master from the processor. The P2P bridge block is not , between the different ports ( Host Bus, A.G.P ., primary PCI bus segments and Main memory). (This also , . Section 6.1.2. A.G.P . Compliant Target Devices A typical host bus bridge (also known as corelogic) is illustrated in Figure 0-1. The host bus provides a port to the Processor, System Memory, the PCI bus and to , Compliant Master P2P Bridge AGP Request Queue Host Bridge Config Space 7 5 Memory


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PDF ECR-16. AGP Host to PCI Bridge commands pci controller pci target gart
mb63h

Abstract: 82443bx host bridge datasheet
Text: Reads - Supports concurrent CPU, AGP and PCI transactions to main memory · AGP interface - Supports , CPU, AGP and PCI transactions to main memory - AGP high-priority transactions ("expedite") support · Power Management Functions - Stop Clock Grant and Halt special cycle translation ( host to PCI Bus) - , MHz/3.3V supporting only a single PCI agent. The 82443BX is designed to support the PIIX4E I/O bridge , the processors front-side bus ( host bus), PCI bus, AGP and main memory. The 82443BX supports a 4


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PDF 440BX 82443BX mb63h 82443bx host bridge datasheet
1999 - SiS5595

Abstract: SiS chipset psl6 PCI33 SiS600 ID12-ID5 SILICON INTEGRATED SYSTEMS AAD27 intel desktop board SERVICE MANUAL
Text: . 8. DEVICE 0, FU NCTION 0 ( HOST - TO - PCI BRIDGE , system. The SiS600 AGP / PCI controller integrates the Host interface, Host-to-PCI bridge , the DRAM , Supports PCI-to-PCI bridge function for memory write from 33Mhz PCI bus to A.G.P . bus Fast PCI IDE , .55 33Mhz Host Bridge & PCI Arbiter , .55 A.G.P . and 66Mhz Host Bridge


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PDF SiS600 SiS600/SiS5595 SiS600 SiS5595 SiS chipset psl6 PCI33 ID12-ID5 SILICON INTEGRATED SYSTEMS AAD27 intel desktop board SERVICE MANUAL
Not Available

Abstract: No abstract text available
Text: all three interfaces ( Host , AGP and PCI ). Host-initiated I/O cycles are decoded to PCI , AGP or PCI , translation table. Other host cycles forwarded to AGP are defined by the AGP address map. PCI and AGP , interface signals conform to the PCI Rev 2.1 specification. 82443GX Host Bridge Datasheet 2-5 , support for PCI-DRAM Reads — Supports concurrent CPU, AGP and PCI transactions to main memory â , data buffering — Supports concurrent CPU, AGP and PCI transactions to main memory — AGP


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PDF 440GX 82443GX
1998 - SIS 5595

Abstract: Pentium 3 processor sis vga sis chipset SIS5595 sis 5600
Text: 5600 AGP / PCI controller integrates the Host interface, Host-to-PCI bridge , the DRAM controller, the , 5600 PCI A.G.P . CONTROLLER Supports Intel Pentium II CPU host bus up to 100MHz Integrated DRAM , . 56 33Mhz Host Bridge & PCI Arbiter . , . 56 A.G.P . and 66Mhz Host Bridge , Pentium II PCI / A.G.P . Chipset 1. SiS 5600/SiS 5595 OVERVIEW SiS 5600 SiS 5595 PCI / A.G.P ./ Host / Memory


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PDF 5600/SiS SIS 5595 Pentium 3 processor sis vga sis chipset SIS5595 sis 5600
1997 - 82443BX

Abstract: 443BX 82371EB 82443bx host bridge datasheet PIIX4E
Text: all three interfaces ( Host , AGP and PCI ). Host-initiated I/O cycles are decoded to PCI , AGP or PCI , translation table. Other host cycles forwarded to AGP are defined by the AGP address map. PCI and AGP , Transaction support for PCI-DRAM Reads - Supports concurrent CPU, AGP and PCI transactions to main memory , buffering - Supports concurrent CPU, AGP and PCI transactions to main memory - AGP high-priority , translation ( host to PCI Bus) - Mobile and "Deep Green" Desktop support for system suspend/resume (i.e


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PDF 440BX 82443BX 04565-001-Sao USA/0498/PSA 443BX 82371EB 82443bx host bridge datasheet PIIX4E
1997 - 82443BX

Abstract: 443BX 82371EB PIIX4E HA21C
Text: all three interfaces ( Host , AGP and PCI ). Host-initiated I/O cycles are decoded to PCI , AGP or PCI , translation table. Other host cycles forwarded to AGP are defined by the AGP address map. PCI and AGP , Transaction support for PCI-DRAM Reads - Supports concurrent CPU, AGP and PCI transactions to main memory , buffering - Supports concurrent CPU, AGP and PCI transactions to main memory - AGP high-priority , translation ( host to PCI Bus) - Mobile and "Deep Green" Desktop support for system suspend/resume (i.e


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PDF 440BX 82443BX 04565-001-Sao USA/0498/PSA 443BX 82371EB PIIX4E HA21C
2001 - STR W 5453 A

Abstract: VT8233 STR W 5453 STR W 5453 C via vt8235 user manual STR 5453 via vt8235 south bridge P4N266 VT8377 via vt8235 chipset south bridge
Text: scheme Independent GART lookup control for host / AGP / PCI master accesses Windows 95 OSR-2 VXD and , PCI bus that provides 2x / 4x / 8x bandwidth compared to previous generation PCI bridge chips. The , Single-Chip North Bridge for Pentium 4 CPUs with 533 / 400 MHz FSB and 8x / 4x / 2x AGP Bus plus , , feature bullets & overview to use VT8235 south bridge Updated strap definitions; Removed SDR support , ; Corrected typo in pin diagram in VCCVL pin names Updated block diagram to show six PCI slots for VT8235


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PDF PC2700 PC1600 MO-151 HSBGA-858 HSBGA-858 STR W 5453 A VT8233 STR W 5453 STR W 5453 C via vt8235 user manual STR 5453 via vt8235 south bridge P4N266 VT8377 via vt8235 chipset south bridge
3VF1

Abstract: 82443ZX PMB 3330 PMB 8815 intel AF 82801
Text: request queuing for all three interfaces ( Host , AGP and PCI ). Host-initiated I/O cycles are decoded to PCI , 82443ZX Host Bridge Datasheet Architectural Overview PCI and AGP initiated cycles that target the , support from PCI to DRAM - Delayed Transaction support for PCI-DRAM Reads - Supports concurrent CPU, AGP and PCI transactions to main memory · AGP interface - Supports single AGP compliant device ( AGP , data streams - AGP-specific data buffering - Supports concurrent CPU, AGP and PCI transactions to


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PDF 440ZX 82443ZX 82801AA 82801AB 3VF1 PMB 3330 PMB 8815 intel AF 82801
bridge 3417

Abstract: 82443GX
Text: document refers to the Host-to-PCI bridge PCI interface as PCI and the Host - AGP PCI interface as AGP , bridge function provides access to the AGP / PCI bus 0. This bus is below the primary bus in the PCI bus , to CONFDATA will result in the Host Bridge translating CONFADD into a PCI configuration cycle , #0 on the PCI bus segment. The Host - / AGP Bridge entity within the 82443GX is accessed as Device #1 , side of the "virtual" PCI-to-PCI bridge referred to as the 82443GX Host - AGP bridge . On the Primary bus


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PDF 82443GX 82443GX, 82443G 82443GX. bridge 3417
VT82C694X

Abstract: Dual Socket 370 VIA VT82C694X PRO133A Dual Socket 370 VIA VT82C694X clock generator gart AGP Host to PCI Bridge VCM driver mobile snoop ahead VT82C596B slot1
Text: Bridge for Desktop and Mobile PC Systems with AGP 4x and PCI plus Advanced ECC Memory Controller , 3.3V (5V tolerant) interface to system memory, AGP , and PCI bus - Modular power management and clock , : VT82C694X system controller and VT82C596B PCI to ISA bridge - Chipset includes UltraDMA-33/66 EIDE, USB , scheme Independent GART lookup control for host / AGP / PCI master accesses - Windows 95 OSR-2 VXD , are synchronous / pseudo-synchronous to host CPU bus - 33 MHz operation on the primary PCI bus - 66


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PDF 97support, Pro133A VT82C596B VT82C694X Dual Socket 370 VIA VT82C694X Dual Socket 370 VIA VT82C694X clock generator gart AGP Host to PCI Bridge VCM driver mobile snoop ahead slot1
1997 - SIS 5595

Abstract: nand 67-Ball bga SiS chipset AMD 700 chipset SIS 5592 SiS5591 SIS 672 SiS5595 SiS 671 SiS 651 chipset
Text: bridge function for memory write from 33Mhz PCI bus to A.G.P . bus s Integrated Posted Write Buffers , used as the PCI Bus Grant by programming the Register69h bit0 to 0 in Host to PCI bridge , SiS5591/5592 Pentium PCI A.G.P . Chipset PBSRAM CPU Host Address Host Data Bus TAG RAM MA Bus , Counters to Ensure Guaranteed Minimum Access Time for A.G.P ., CPU, and PCI accesses s Provides High , - Support Concurrency between CPU to 33Mhz PCI Access and 33Mhz PCI to A.G.P . Access - Support


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PDF SiS5591/5592 SiS5595 P54C/P55C, SiS5591/SiS5592 SIS 5595 nand 67-Ball bga SiS chipset AMD 700 chipset SIS 5592 SiS5591 SIS 672 SiS 671 SiS 651 chipset
1997 - 82443LX

Abstract: 440LX 82371SB AD11 AD12 A0000H-BFFFFH PAC 512 29056
Text: CPU-to-PCI Burst Writes Supports Concurrent Host , PCI , and A.G.P . Transactions to Main Memory System , masters in addition to the I/O bridge (PIIX4). PAC supports only synchronous PCI coupling to the host bus , host , A.G.P . and PCI interfaces). I/O APIC The I/O APIC is used to support dual processors. In , Coupling to the Host Bus Frequency PCI Bus Interface PCI Revision 2.1 Interface Compliant Greater , Arbitration Acceleration Hooks Five PCI Bus Masters are Supported in Addition to the Host and PCI-to-ISA


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PDF 440LX 82443LX 32-Bit 64/72-bit 64-Mbit 82371SB AD11 AD12 A0000H-BFFFFH PAC 512 29056
1997 - md2817

Abstract: 82443GX 440GX 82371EB "full hd" mobile phone camera pinout PIIX4E MD2716 2906380
Text: interfaces ( Host , AGP and PCI ). Host-initiated I/O cycles are decoded to PCI , AGP or PCI configuration space , Reads - Supports concurrent CPU, AGP and PCI transactions to main memory · · - Supports , concurrent CPU, AGP and PCI transactions to main memory - AGP high-priority transactions ("expedite") support Power management functions - Stop Clock Grant and Halt special cycle translation ( host to PCI , Configuration Accesses to PCI or AGP .3-5 3.2.3 PCI Bus Configuration Mechanism Overview


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PDF 440GX 82443GX md2817 82371EB "full hd" mobile phone camera pinout PIIX4E MD2716 2906380
Not Available

Abstract: No abstract text available
Text: Supports concurrent CPU, AGP and PCI transactions to main memory 82443GX Host Bridge D atash ee t m i , - AGP-specific data buffering - Supports concurrent CPU, AGP and PCI transactions to main memory - , Halt special cycle translation ( host to PCI Bus) - "Deep Green" Desktop support for system suspend , transfers between the processors system bus ( host bus), PCI bus, AGP and main memory. The 82443GX supports a , ). Host-initiated I/O cycles are decoded to PCI , AGP or PCI configuration space. Host-initiated


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PDF 440GX 82443GX
2001 - VT8233

Abstract: STR W 5453 C via vt8235 user manual vt8235 VT8233A P4N266 via vt8235 STR W 5453 via vt8235 chipset south bridge P4M266
Text: scheme Independent GART lookup control for host / AGP / PCI master accesses Windows 95 OSR-2 VXD and , Single-Chip North Bridge for Pentium 4 CPUs with 533 / 400 MHz FSB and 8x / 4x / 2x AGP Bus plus , 1.0 published 12/5/01 Updated cover, block diagram and feature bullets to add AGP 8x and DDR 333 , & overview to use VT8235 south bridge Updated strap definitions; Removed SDR support Updated , V-Link to 533 MB/sec in feature bullets and overview Fixed errors and typos (package pin count, # of PCI


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PDF PC2700 PC1600 MO-151 HSBGA-858 HSBGA-858 VT8233 STR W 5453 C via vt8235 user manual vt8235 VT8233A P4N266 via vt8235 STR W 5453 via vt8235 chipset south bridge P4M266
bridge 3417

Abstract: 430TX Configuration 82443bx 82443bx host bridge datasheet
Text: document refers to the Host-to-PCI bridge PCI interface as PCI and the Host - AGP PCI interface as AGP , PCI-to-PCI bridge function provides access to the AGP / PCI bus 0. This bus is below the primary bus in the PCI , to CONFDATA will result in the Host Bridge translating CONFADD into a PCI configuration cycle , #0 on the PCI bus segment. The Host - / AGP Bridge entity within the 82443BX is accessed as Device #1 , side of the "virtual" PCI-to-PCI bridge referred to as the 82443BX Host - AGP bridge . On the Primary bus


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PDF 82443BX 82443BX, 82443B 82443BX. bridge 3417 430TX Configuration 82443bx host bridge datasheet
VT82C693

Abstract: VT82C596A apollo proplus snoop ahead timing diagram cpu and bios VIA Apollo Master slot1 370CPU
Text: SDRAM, VCM, EDO, and FPG · AGP / PCI / ISA Mobile and Deep Green PC Ready - GTL+ compliant host bus , replacement scheme Independent GART lookup control for host / AGP / PCI master accesses - Windows 95 OSR , buses are synchronous / pseudo-synchronous to host CPU bus - 33 MHz operation on the primary PCI bus - 66 MHz PCI operation on the AGP bus - PCI-to-PCI bridge configuration on the 66MHz PCI bus - , controller (492 pin BGA) and the VT82C596A PCI to ISA bridge (324 pin BGA). The system controller provides


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PDF VT82C596A VT82C693 apollo proplus snoop ahead timing diagram cpu and bios VIA Apollo Master slot1 370CPU
1998 - m 3329 c1 video out pin

Abstract: A26 zener diode ZENER A26 cdqa2 AGP Host to PCI Bridge AD12 AD11 A0000H-BFFFFH 82443EX 440LX
Text: Host , PCI , and AGP Transactions to Main Memory · System Management Mode (SMM) Compliant · 492 , Supported - Synchronous Coupling to the Host Bus Frequency The Intel® 440EX AGPset, 82443EX PCI AGP , . Host cycles forwarded to AGP are defined by the AGP address map. PAC also receives requests from PCI , software. All accesses to the aperture, from the Host , PCI or AGP , are translated using the AGP address , the I/O bridge (PIIX4). PAC supports only synchronous PCI coupling to the host bus frequency. Read


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PDF 440EX 82443EX 04565-001-Sao USA/0498/PSA m 3329 c1 video out pin A26 zener diode ZENER A26 cdqa2 AGP Host to PCI Bridge AD12 AD11 A0000H-BFFFFH 440LX
VT8233

Abstract: VT8366 Socket-462 KT266 Diagram of memory slots on a desktop or notebook computer socket462 Athlon Processors VT8233 ram athlon pin configuration VIA Apollo Master
Text: PCI / ISA bridge chips. The VT8233 also provides a 266MB/sec bandwidth Host /Client V-Link interface , , 266 MB/sec high bandwidth V-Link NB/SB, and 32-bit AGP interfaces - V-Link south bridge chip , outstanding transaction queue for Host to V-Link Client accesses - Supports Defer/Defer-Reply transaction - Transaction assurance for V-Link Host to Client access. Eliminate V-Link Host-Client Retry cycles - , transaction both Host and Client have consistent view of transaction data depth and buffer size to avoid data


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PDF KT266 VT8366 KT266 Socket-462) PC133 PC100 PC2100 PC1600 VT8233 VT8366 Socket-462 Diagram of memory slots on a desktop or notebook computer socket462 Athlon Processors VT8233 ram athlon pin configuration VIA Apollo Master
rx69

Abstract: VT82C693A VT82C693 slot AGP pinout VT82C694 Rx68 VIA Apollo Master via vt82c693a snoop ahead Socket-370
Text: / pseudo-synchronous to host CPU bus - 33 MHz operation on the primary PCI bus - 66 MHz PCI operation on the AGP bus , Bridge for Desktop and Mobile PC Systems with AGP 2x and PCI plus Advanced ECC Memory Controller supporting SDRAM, VCM, EDO, and FPG · AGP / PCI / ISA Mobile and Deep Green PC Ready - GTL+ compliant host , VT82C596B PCI to ISA bridge - Chipset includes UltraDMA-33/66 EIDE, USB, and Keyboard / PS2-Mouse , GART lookup control for host / AGP / PCI master accesses - Windows 95 OSR-2 VXD and integrated


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PDF Pro133 VT82C596B rx69 VT82C693A VT82C693 slot AGP pinout VT82C694 Rx68 VIA Apollo Master via vt82c693a snoop ahead Socket-370
2000 - 443bx

Abstract: PME26605001AA pin configuration of i3 processor pin diagram i3 processor 74219
Text: the PCI bus, AGP bus, DRAM memory bus and some host bridge sideband signals. An onboard voltage , via a 3.3 V PCI bus, a 3.3 V AGP bus, a 3.3 V memory bus and the Intel 443BX Host Bridge /Controller , PCI DEVSEL#. Not used during AGP transactions. This signal is driven by the 443BX Host Bridge , Select: This signal is driven by the 443BX Host Bridge /Controller when a PCI initiator is attempting to , Host Bridge to grant PCI to the expansion bridge . The PHLDA# protocol has been modified to include


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PDF 64-bit 443BX PME26605001AA pin configuration of i3 processor pin diagram i3 processor 74219
1997 - 443BX

Abstract: 66-MHZ MMC-2 cpu northbridge circuit pentium 4 82443BX 243668 Pentium II MMC-2
Text: interfaces electrically to its host system via a 3.3V PCI bus, a 3.3V AGP bus, a 3.3V memory bus and the , write-back cacheable SMRAM up to 1 MB. The Intel 443BX Host Bridge system controller is a 3.3V PCI bus , function as PCI DEVSEL#. Not used during AGP transactions. This signal is driven by the 443BX Host Bridge , additional conduit to pass address and commands to the 443BX Host Bridge System Controller from the AGP , central resource (PIIX4) to start or maintain the PCI clock by asserting CLKRUN#. The 443BX Host Bridge


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PDF 64-bit AGP-66/133 443BX USA/96/POD/PMG 66-MHZ MMC-2 cpu northbridge circuit pentium 4 82443BX 243668 Pentium II MMC-2
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