The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
ACT20JH55HN [V001] (YACT20JH55HNV00100) TE Connectivity (YACT20JH55HNV00100) SQUARE FLANGE RECEPTACLE
ADS6149IRGZT Texas Instruments 14-Bit, 250-MSPS Analog-to-Digital Converter (ADC) 48-VQFN -40 to 85
ADS6149IRGZRG4 Texas Instruments 1-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL/PARALLEL ACCESS, PQCC48, 7 X 7 MM, GREEN, PLASTIC, QFN-48
ADS6149IRGZTG4 Texas Instruments Low power 14-bit, 250 MSPS ADC 48-VQFN -40 to 85
ADS6149IRGZ25 Texas Instruments 1-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL/PARALLEL ACCESS, PQCC48, 7 X 7 MM, GREEN, PLASTIC, QFN-48
ADS6149IRGZR Texas Instruments 14-Bit, 250-MSPS Analog-to-Digital Converter (ADC) 48-VQFN -40 to 85
SF Impression Pixel

Search Stock (2)

  You can filter table by choosing multiple options from dropdownShowing 2 results of 2
Part Manufacturer Supplier Stock Best Price Price Each Buy Part
ACT20JH55HN-6149 V001 TE Connectivity Ltd Heilind Electronics - - -
ACT20JH55HN-6149 V001 TE Connectivity Ltd Interstate Connecting Components - - -

No Results Found

Show More

ACT20JH55HN-6149+V001 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
Not Available

Abstract: No abstract text available
Text: . 8 Copyright © Azoteq (Pty) Ltd All Rights Reserved. AZD063 Azoteq RS100 Overview v0.01 , v0.01 Page 2 of 9 May 2012 IQ Switch® ProxSense® 2 Requirements and assembly In order to , Module Copyright © Azoteq (Pty) Ltd All Rights Reserved. AZD063 Azoteq RS100 Overview v0.01 , All Rights Reserved. AZD063 Azoteq RS100 Overview v0.01 Page 4 of 9 May 2012 IQ Switch , . AZD063 Azoteq RS100 Overview v0.01 Page 5 of 9 May 2012 IQ Switch® ProxSense® 3 Operating


Original
PDF AZD063 RS100
2003 - 4342414

Abstract: No abstract text available
Text: 150 5 ­15 15 6 140 130 5 ­20 20 7 110 100 5 Unit ns ns mA mA mA 6/30/03, v.0.0.1 Alliance , I/O13 I/O6 A14 A15 I/O14 I/O15 NC A8 A12 A13 A9 A10 WE A11 6/30/03, v.0.0.1 Alliance , (ISB, ISB1) 6/30/03, v.0.0.1 Alliance Semiconductor P. 3 of 11 AS7C34098A , conditions VIN = 0V VIN = VOUT = 0V Max 6 8 Unit pF pF 6/30/03, v.0.0.1 Alliance Semiconductor P. 4 , Previous data valid tAA Data valid tOH 6/30/03, v.0.0.1 Alliance Semiconductor P. 5 of 11


Original
PDF AS7C34098A AS7C34098 44-pin 400-mil 48-ball AS7C34098 AS7C34098A 4342414
2010 - Not Available

Abstract: No abstract text available
Text: HMC839LP6CE v001 .0410 FRACTIONAL-N SYNTHESIZER WITH INTEGRATED VCO 1050 - 1205, 2100 - 2410 , apps@hittite.com HMC839LP6CE v001 .0410 FRACTIONAL-N SYNTHESIZER WITH INTEGRATED VCO 1050 - 1205, 2100 - , ; 7 HMC839LP6CE v001 .0410 FRACTIONAL-N SYNTHESIZER WITH INTEGRATED VCO 1050 - 1205, 2100 - , Support: Phone: 978-250-3343 or apps@hittite.com HMC839LP6CE v001 .0410 FRACTIONAL-N SYNTHESIZER , Support: Phone: 978-250-3343 or apps@hittite.com HMC839LP6CE v001 .0410 FRACTIONAL-N SYNTHESIZER


Original
PDF HMC839LP6CE 24-bit HMC839LP6CE HMC860LP3E
2001 - AS7C34096A

Abstract: No abstract text available
Text: 160 150 5 ­15 15 6 140 130 5 ­20 20 7 110 100 5 Unit ns ns mA mA mA 6/30/03, v.0.0.1 Alliance , = Low, H = High 6/30/03, v.0.0.1 Alliance Semiconductor P. 2 of 9 AS7C34096A , , v.0.0.1 Alliance Semiconductor P. 3 of 9 AS7C34096A ® Read cycle (over the operating , current tPU 50% Data valid tPD 50% ICC ISB tOHZ tCHZ 6/30/03, v.0.0.1 Alliance Semiconductor P. 4 , tWP WE tAS DIN tWZ DOUT tDW Data valid tOW tDH tWR tAH 6/30/03, v.0.0.1 Alliance Semiconductor


Original
PDF AS7C34096A AS7C34096 36-pin 44-pin AS7C34096A) AS7C34096A
2006 - SG-BGA-6149

Abstract: No abstract text available
Text: 11 10 6 Customer's BGA IC 5 11 Customer's Target PCB 12 SG-BGA- 6149 Drawing , Date: 3/23/05 File: SG-BGA- 6149 Dwg Modified: 6/2/09 Socket base nut: 18-8 Stainless steel , PCB Pad height: Same or higher than solder mask SG-BGA- 6149 Drawing © 2006 IRONWOOD ELECTRONICS , : Released Scale: 4:1 Rev: B Drawing: H. Hansen Date: 3/23/05 File: SG-BGA- 6149 Dwg , mark on top surface of package. A Z 0.12 Z Side View SG-BGA- 6149 Drawing © 2006 IRONWOOD


Original
PDF 225mm M-1994. SG-BGA-6149
MP7695AD

Abstract: MP7695AN HP5082-2835 diode hp5082 HP5082-2835 MP7695 MP7695AS MP7695SD V3FF
Text: V001 V002 V3fe V3ff Vofw Vrefh Figure 7. Ideal A/D Transfer Function The overflow transition (Vofw , take place at: Vin = V001 = Vrefh + 0.5 * LSB Vin - V3ff Vrefh - 1.5 * LSB LSB - Vref /1024 - (V3ff - V001 ) / 1022 Note that the overflow transition is af lag and has no impact on the data bits. DIGITAL CODES 0.5 * LSB 1.5 * LSB Vrefh V001 V002 V3fe V3ff Vrefw Figure 8. Real A/D Transfer Curve , V002 - V001 - LSB DNL (3FE) = V3ff - V3fe - LSB Efs (full scale error) - Vrefw -1 -5 * LSB - V3ff


OCR Scan
PDF MP7695 10-Bit MP7695 MP7695. MP7695AD MP7695AN HP5082-2835 diode hp5082 HP5082-2835 MP7695AS MP7695SD V3FF
Not Available

Abstract: No abstract text available
Text: DNL(N) = [V (n+1)- V (n)]-L S B — r V r e f h V001 V002 V 3f E 1 V 3f f i Figure , - V001 - LSB V in = Vofw = V ref(+) “ 0-5 * LSB The first and the last transitions for the data bits take place at: DNL (3FE) = V3ff - V3FE - LSB V|N = V001 = V r e f h + 0 5 * LSB Epg , scale error) = V ref(-) + 0.5 * LSB - V001 LSB = V ref / 1024 = (V3ff - V001 ) / 1022 Note that the , 3-349 V001 V002 V 3 fe V 3 f f v REF(+) Figure 6. Real A/D Transfer Curve Figure 8


OCR Scan
PDF MP8799 10-Bit, 10-Bit
Not Available

Abstract: No abstract text available
Text: VREF(–) V001 φS Latch VTAP φB φS COARSE COMPARATOR φS V3FF V0FW VREF(+ , the last transitions for the data bits take place at: VIN = V001 = VREF(–) + 0.5 ∗ LSB VIN = V3FF = VREF(+) – 1.5 ∗ LSB LSB = VREF / 1024 = (V3FF – V001 ) / 1022 Note that the overflow , φB 3FE 001 FINE COMPARATOR 000 Figure 6. MP7695 Comparators VREF(–) V001 V002 , Non-Linearity (INL) and zero and full scale errors (EZS, EFS) are: DNL (001) = V002 – V001 – LSB


Original
PDF MP7695 10-Bit MP8795 25kHz
BECKMAN 332

Abstract: DDD7003 HP5082-2835 MP8799 MP8799AE
Text: 001 000 ! LSB I 002 J- 3FDj~ 3FE r T = 1 Vrefh V001 V002 V3FE V3FF V0FW VREF(+) Figure 4 , * LSB The first and the last transitions for the data bits take place at: V|N = V001 = VREFH + 0.5 * LSB Vin = V3FF = VRef(-)-1.5*LSB LSB = VREF / 1024 = (V3FF - V001 ) / 1022 Note that the overflow , and full scale errors (Ezs, EFS) are: DNL (001) = V002 - V001 - LSB DNL (3FE) = V3FF - V3FE - LSB Efs (full scale error) = V3FF - [VREF(+) -1.5 * LSB] Ezg (zero scale error) = V001 - [VREF(_) + 0.5


OCR Scan
PDF MP8799 10-Bit MP87L99 3422blfl 3422bl6 BECKMAN 332 DDD7003 HP5082-2835 MP8799 MP8799AE
PC ladder diagram

Abstract: HP5082-2835 MP87L98AN MP87L98AQ MP87L98AS
Text: MP87L98 vREFH V001 V002 V3FE V3FF V0FW VREF(+) Figure 4. Ideal A/D Transfer Function The overflow , the data bits take place at: V|N = V001 = VREF{_) + 0.5 * LSB V|N = V3FF = VrEF(+)-1.5*LSB LSB = VREF / 1024 = (V3FF - V001 )/1022 Note that the overflow transition is a flag and has no impact on the , : DNL (001) = V002- V001 - LSB DNL (3FE) = V3FF - V3FE - LSB Efs (full scale error) = V3FF - [VREF(+) -1.5 * LSB] Ezs (zera scale error) = V001 - [Vref(-) + 0.5 * LSB] DIGITAL CODES 0.5 * LSB 1.5* LSB


OCR Scan
PDF MP87L98 10-Bit, 10-Bit DACMP7641 3422blfl PC ladder diagram HP5082-2835 MP87L98AN MP87L98AQ MP87L98AS
ofw g 3203

Abstract: ofw g 3201 ofw 3203
Text: that the following relations apply: R ref = 1024 * R IMPS 0004b77 8DS klE C VREF(_) V001 , V001 = V re F(_j + 0.5 * LSB V|n = V 3 ff = V REF(+) - 1.5 * LSB LSB = V REF /1 0 2 4 = (V3 ff - V001 , I c 1 II_i_J JcL " V001 V002 —! - H -V3fe V3ff VREF(+ , Non-Linearity (INL) and zero and full scale errors (Ezs. EFs ) are: DNL (001) = V002 - V001 - LSB Accuracy , (zero scale error) = V R£F(_) + 0.5 * LSB - V001 MICRO POIilER SYSTEMS INC b lE » b017MMM O O


OCR Scan
PDF DDDHb72 MP7695 10-Bit MP7695 MP7695. ofw g 3203 ofw g 3201 ofw 3203
2013 - Not Available

Abstract: No abstract text available
Text: Microwave 6149 40 GHz Pulse Generator and Modulator Low cost microwave pulse generator and , The IFR 6149 Pulse Generator and Modulator is an adapter unit which works in conjunction with the , €¢ Store/Recall of pulse patterns on separate memory card The 6149 comprises two parts a pulse , €¢ The 6149 is connected to the MTS through power and data connections at the rear, and RF input at the , test system. In addition, pulse sync and video outputs are provided on the rear of the 6149 for


Original
PDF 6204B 6204B
1993 - V002

Abstract: No abstract text available
Text: Tester V VREF(–) V001 N V002 V3FE V3FF V0FW VREF(+) Figure 4. Ideal A/D Transfer , full scale errors (EZS, EFS) are: DNL (001) = V002 – V001 – LSB The overflow transition (VOFW , €“ [VREF(+) –1.5 ∗ LSB] VIN = V001 = VREF(–) + 0.5 ∗ LSB EZS (zero scale error) = V001 – [VREF(–) + 0.5 ∗ LSB] VIN = V3FF = VREF(–) – 1.5 ∗ LSB LSB = VREF / 1024 = (V3FF – V001 , 2.25 and 6.75 mV. VREF(–) V001 V002 V3FE V V3FF VREF(+) Figure 6. Real A/D


Original
PDF MP8796 10-Bit 10-Bit V002
MP7695

Abstract: MP7695AD MP7695AN MP7695AS MP7695SD MP8795
Text: 3FE I r I T I T = 1 VREF(_, V001 V002 V3FE V3ff Vofw Vref(+) Figure 7. Ideal A/D Transfer , the last transitions forthe data bits take place at: V|N = V001 = VREFH + 0.5 * LSB V|N = V3FF = VREF(+)-1.5*LSB LSB = VREF / 1024 = (V3FF - V001 ) / 1022 Note that the overflow transition is a flag and , VREFH V001 V002 V3FE V3ff VREF(t) Figure 8. Real A/D Transfer Curve In a "real" converter, the , (Ezs, EFs) are: DNL (001) = V002 - V001 - LSB DNL (3FE) = V3ff - V3FE - LSB Efs (full scale error) =


OCR Scan
PDF MP7695 10-Bit MP8795 25kHz MP7695 MP7695. 3422b MP7695AD MP7695AN MP7695AS MP7695SD
Not Available

Abstract: No abstract text available
Text: DNL,n) = [ V (n +1)- V (n )] - L S B I V r e f(-) v001 V 002 V 3fe V 3f f i , ) takes place at: DNL (001) = V002 - V001 - LSB = V ref(+) - 0.5 * LSB The first and the last transitions for the data bits take place at: DNL (3FE) = V3ff - V3FE - LSB V|N = V001 = VREFH + 0.5 , (zero scale error) = VREF(_) + 0.5 * LSB - V001 LSB = VREF / 1024 = (V3FF - V001 ) /1022 Note that


OCR Scan
PDF MP87099 10-Bit, 10-Bit
2004 - electromagnetic pulse generator

Abstract: electromagnetic pulse generator kit 6204B electromagnetic pulse kit K/panasonic pri card
Text: 6149iss1.qxd 07/Dec/2004 10:19 Page 1 Microwave 6149 40 GHz Pulse Generator and , placement resolution The IFR 6149 Pulse Generator and Modulator is an adapter unit which works in , function · Store/Recall of pulse patterns on separate memory card The 6149 comprises two parts - a , MTS. The MTS acts as the system controller, RF source and user interface. Benefits The 6149 is , addition, pulse sync and video outputs are provided on the rear of the 6149 for visual inspection of


Original
PDF 6149iss1 07/Dec/2004 6204B 6204B electromagnetic pulse generator electromagnetic pulse generator kit electromagnetic pulse kit K/panasonic pri card
1993 - Not Available

Abstract: No abstract text available
Text: Tester V VREF(–) V001 V002 V3FE V3FF V0FW VREF(+) Figure 4. Ideal A/D Transfer , €“ V001 – LSB VIN = VOFW = VREF(+) – 0.5 ∗ LSB : : : The first and the last transitions for the data bits take place at: DNL (3FE) = V3FF – V3FE – LSB VIN = V001 = VREF(–) + 0.5 â , ˆ— LSB EZS (zero scale error) = V001 – [VREF(–) + 0.5 ∗ LSB] LSB = VREF / 1024 = (V3FF – V001 ) / 1022 DIGITAL CODES 0.5 ∗ LSB Note that the overflow transition is a flag and has no


Original
PDF MP8795 10-Bit 10-Bit
2001 - Not Available

Abstract: No abstract text available
Text: VOFW = VREF(+) The first and the last transitions for the data bits take place at: VIN = V001 = VREF(- , / 1024 = (V3FF - V001 ) / 1022 NOTE: The overflow transition is a flag and has no impact on the data bits , 2.5 mV and every code width is within 1.25 and 3.75 mV. 000 LSB V VREF(-) V001 V002 , ), Integral Non-Linearity (INL) and zero and full scale errors (EZS, EFS) are: DNL (001) = V002 - V001 - LSB , error) = V001 - [VREF(-) + 0.5 * LSB] FIGURE 8. REAL A/D TRANSFER CURVE Output Codes 7 Real Transfer


Original
PDF XRD87L99 10-BIT, 10-Bit 100kHz
694-3-R10K

Abstract: T 3108 001 HP5082-2835 MP87L99AE
Text: I r vrefh V001 V002 V3FE V3FF V0FW Vref(+) Figure 4. Ideal A/D Transfer Function The overflow , the data bits take place at: V|N = V001 = VREF(_) + 0.5 * LSB Vin = V3FF = VREF(+) - 1.5 * LSB LSB = VHEF / 1024 = (V3FF - V001 ) / 1022 Note that the overflow transition is aflag and has no impact , scale errors (Ezs, EFS) are: DNL (001) = V002 - V001 - LSB DNL (3FE) = V3FF - V3FE - LSB EFS (full scale error) = V3FF - [VREF(+) -1.5 * LSB] Ezs (zero scale error) = V001 - [VREFH + 0.5 * LSB] DIGITAL


OCR Scan
PDF MP87L99 10-Bit, 10-Bit 3422fci 0007S53 342Zbia 0007SS4 694-3-R10K T 3108 001 HP5082-2835 MP87L99AE
Not Available

Abstract: No abstract text available
Text: INFORMATION 04/28/98 N V001 -0A 1 IS23SC4418/4428 ISSI RESET, BLOCKADE LOGIC HIGH-VOLTAGE GENERATOR , . Integrated Silicon Solution, Inc. ADVANCE INFORMATION 04/28/98 N V001 -0A 3 IS23SC4418/4428 ISSI , 04/28/98 N V001 -0A 5 IS23SC4418/4428 ISSI 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 RST , Silicon Solution, Inc. ADVANCE INFORMATION 04/28/98 N V001 -0A 7 IS23SC4418/4428 ISSI , 10. Writing Error Counter Integrated Silicon Solution, Inc. ADVANCE INFORMATION 04/28/98 N V001


OCR Scan
PDF IS23SC4418/4428 V001-0A IS23SC4418/4428 IS23SC4418-X IS23SC4428-X IS23SC4418-XI IS23SC4428-XI NV001-0A
2001 - HP5082-2835

Abstract: MP5010 MP7641 XRD8799 XRD87L99 XRD87L99AIQ
Text: = V001 = VREF(-) + 1.0 * LSB VIN = V3FF = VREF(-) - 1.0 * LSB VREF = VREF(+) - VREF(-) LSB = VREF / 1024 = (V3FF - V001 ) / 1022 DIGITAL CODES NOTE: The overflow transition is a flag and has no , fractions of LSBs. 3FD 001 000 LSB V VREF(-) V001 V002 V3FE V3FF V0FW = VREF(+ , (001) = V002 - V001 - LSB : 5 EFS DNL (3FE) = V3FF - V3FE - LSB INL 4 EFS (full scale error) = V3FF - [VREF(+) -1.5 * LSB] EZS (zero scale error) = V001 - [VREF(-) + 0.5 * LSB] 3


Original
PDF XRD87L99 10-BIT, 10-Bit 100kHz HP5082-2835 MP5010 MP7641 XRD8799 XRD87L99 XRD87L99AIQ
1993 - Not Available

Abstract: No abstract text available
Text: Tester V VREF(–) V001 V002 V3FE V3FF V0FW VREF(+) Figure 4. Ideal A/D Transfer , €“ V001 – LSB VIN = VOFW = VREF(+) – 0.5 ∗ LSB : : : The first and the last transitions for the data bits take place at: DNL (3FE) = V3FF – V3FE – LSB VIN = V001 = VREF(–) + 0.5 â , ˆ— LSB EZS (zero scale error) = V001 – [VREF(–) + 0.5 ∗ LSB] LSB = VREF / 1024 = (V3FF – V001 ) / 1022 DIGITAL CODES 0.5 ∗ LSB Note that the overflow transition is a flag and has no


Original
PDF MP87L99 10-Bit, 10-Bit
2003 - x 2933

Abstract: RX2 1027 VH46 1294 vh50 VL47 FPD33584 UPD176 VH29 VL61
Text: 01H VL1 VGMA9-(VGMA9-VGMA10)x 5747/ 6149 21H VL33 VGMA7-(VGMA7-VGMA8)x 2040/2174 02H VL2 VGMA9-(VGMA9-VGMA10)x 5345/ 6149 22H VL34 VGMA7-(VGMA7-VGMA8)x 1906/2174 03H VL3 VGMA9-(VGMA9-VGMA10)x 4943/ 6149 23H VL35 VGMA7-(VGMA7-VGMA8)x 1772/2174 04H VL4 VGMA9-(VGMA9-VGMA10)x 4541/ 6149 24H VL36 VGMA7-(VGMA7-VGMA8)x 1638/2174 05H VL5 VGMA9-(VGMA9-VGMA10)x 4139/ 6149 25H VL37 VGMA7-(VGMA7-VGMA8)x 1504/2174


Original
PDF FPD33584 FPD33584 18-bit 85MHz x 2933 RX2 1027 VH46 1294 vh50 VL47 UPD176 VH29 VL61
HP5082-2835 diode

Abstract: HP5082-2835 1N4148 MICRO POWER SYSTEMS diode v001 MP7696AS MP7696AN MP7696 MP5010 2N2222
Text: an ideal A/D converter is shown in Figure 7. M Micro Power Systems 0 .5 * LSB Vrefh V001 V002 V1 , at: ViN = V001 = Vrefh + 0.5 * LSB Vin - V1ff - Vrefh - 1-5 * LSB LSB = Vref / 512 = (V1 ff - V001 ) / 512 Note that the overflow transition isaflag and has no impact on the data bits. Vrefh V001 V002 , Non-Linearity (INL) and zero and full scale errors (Ezs, Efs) are: DNL (001) = V002 - V001 - LSB DNL (1 fe) = , Vrefh + 0.5 * LSB - V001 3-156 This Material Copyrighted By Its Respective Manufacturer M Micro


OCR Scan
PDF MP7696 MP7696 P7696. HP5082-2835 diode HP5082-2835 1N4148 MICRO POWER SYSTEMS diode v001 MP7696AS MP7696AN MP5010 2N2222
V002

Abstract: HP5082-2835 MP7226 MP7641 MP8796 MP8796AS XICX
Text: ) V001 V002 V3FE V3FF V0FW Vref(+) Figure 4. Ideal A/D Transfer Function 3FF_|_ I The overflow , the data bits take place at: V|N = V001 = VREF(_) + 0.5 * LSB V|n = V3ff = Vref(+)-1-5*LSB LSB = VREF/1024 = (V3FF - V001 ) / 1022 Note that the overflow transition is a flag and has no impact on the , Non-Linearity (INL) and zero and full scale errors (Ezs> Eps) are: DNL (001) = V002 - V001 - LSB DNL (3FE) = V3FF - V3FE - LSB Eps (full scale error) = V3FF - [VREF(+) -1.5 * LSB] Ezs (zero scale error) = V001


OCR Scan
PDF MP8796 10-Bit 20-Pin DDD7771 V002 HP5082-2835 MP7226 MP7641 MP8796 MP8796AS XICX
Supplyframe Tracking Pixel