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S-8338ACIA-P8T1G ABLIC Inc Switching Controller, Voltage-mode, 0.16A, 1246.3kHz Switching Freq-Max, CMOS, PDSO8, LEAD FREE, SON-8
S-8337ACIA-T8T1G ABLIC Inc Switching Controller, Voltage-mode, 0.16A, 1246.3kHz Switching Freq-Max, CMOS, PDSO8, TSSOP-8
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F68B50P

Abstract:
Text: the bus-programmed master reset, which must be applied prior to operating the ACIA. After master , over the ACIA. ACIA Bidirectional Data (D0 - D 7) The bidirectional data lines (Do- 6 7 ) allow for , buffers and clocks data to and from the ACIA. This signal normally is a derivative of the F6800 < t> 2 , , the R/W signal is used to select read-only or write-only registers within the ACIA. Chip Select (CSo, CS-|, CS2 ) These three high-impedance, TTL-compatible input lines are used to address the ACIA.


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PDF F6850/F68A50/F68B50 F6850 F6800 F6850/F68A50/F68B50 F6850P F6850CP F6850DL F6850DM F68B50P schlumberger 5220
z854

Abstract:
Text: reset, which must be applied prior to operating the ACIA. After master resetting the ACIA , the , output, permit the MPU to have complete control overthe ACIA. - - ^ - ACIA Bidirectional Data (D0-D7 , , TTL-compatible input that enables the bus input/output data buffers and clocks data to and from the ACIA. This , input/output databus interface. When R/W is HIGH (MPU readcycle), ACIA-output drivers are turned on and , registers within the ACIA. Chip Select (CS0, CS1, CS2) These three high-impedance, TTL-compatible input


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PDF F6850 F6800 856A-09^ F6850/F68A50/F68B50 F6850P F6850CP F6850DL F6850DM F68A50P z854 and64
ACIA

Abstract:
Text: reset, which must be applied prior to operating the ACIA. After master resetting the ACIA , the , , permit the MPU to have complete control over the ACIA. ACIA Bidirectional Data (D0-D7) The , that enables the bus input/output data buffers and clocks data to and from the ACIA. This signal , registers within the ACIA. Chip Select (CS0, CS1, CS2) These three high-impedance, TTL-compatible input lines are used to address the ACIA. The ACIA is selected when CSo and CS1 are HIGH and CS2 is LOW


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PDF F6850/F68A50/F68B50 F6850 F6800 F6850P F6850CP F6850DL F6850DM F68A50P ACIA F68B50 F68A50C F68A50 F6850DM F6850C
MC6850P

Abstract:
Text: Status Register either as a result of an interrupt or in the ACIA's turn in a polling sequence. A , line, and enable line. These signals permit the MPU to have complete control over the ACIA. ACIA , to and from the ACIA. This signal will normally be a derivative of the MC6800 2 Clock or MC6809 E , used to control the direction of data flow through the ACIA's input/output data bus interface. When , . Therefore, the Read/Write signal is used to select read-only or write-only registers within the ACIA. Chip


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PDF MC6850 MC6850 MC6800 MC6850S MC6850CS MC68A50S MC68A50CS MC68B50S MC6850P MC6850P MC68A50P MC68B50P MC6860L MC6860 MC6850CP MC68B50 d715
CS 5211

Abstract:
Text: the ACIA. After master resetting the ACIA , the programmable control register can be set for a number , , permit the MPU to have complete control over the ACIA. ACIA Bidirectional Data (D0-D7) The , that enables the bus input/output data buffers and clocks data to and from the ACIA. This signal , ACIA. Chip Select (CS0, CS^ CS2) These three high-impedance, TTL-compatible input lines are used to address the ACIA. The ACIA is selected when CSo and CS, are HIGH and CS2 is LOW. Transfers of data to and


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PDF F6850/F68A50/F68B50 F6850 F6800 F6850/F68A50/F68B50 F6850P F6850CP F6850DL F6850DM F68A50P CS 5211 schlumberger 5220 F68B50 F68A50C F68A50 F6850DM F6850C
65c51

Abstract:
Text: DSR inputs to tr ACIA. A 0 indicates a low level (true condition) and a 1 indicate a high level (false , slave other circuits to the ACIA. Figure 3 shows the Transmitter and Receiver layout. RECEIVER SHIFT , . Data Bus (D0-D7) The eight data line (D0-D7) pins transfer data between the processor and the ACIA. , clocks all data trans-'S between the system microprocessor and the ACIA. ead/Write (R/W) "e R/W inout , ocessor to read the data suoplied by the ACIA. a low allows write to the ACIA. Table 1. ACIA Register


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PDF R65C5 R65C51 R65C51 65C51 28-PIN 65c51 Rockwell 65C51 R6551 Rockwell R65C51 74157 direct replacement a45a8 74157 pin diagram R6551* rockwell
R6551 27

Abstract:
Text: ) These bits reflect the levels of the DCD and DSR inputs to the ACIA. A 0 indicates a low level (true , slave other circuits to the ACIA. Figure 3 shows the Transmitter and Receiver layout. Figure 3 , data supplied by the ACIA , a low allows a write to the ACIA. Interrupt Request (IRQ) The IRQ pin is , processor and the ACIA. These lines are bi-directional and are normally high-impedance except during Read , microprocessor and the ACIA. NOTE: The specified maximum cycle time for the signal on this input is 40 fts. This


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PDF R6551 R6551 28-PIN R6551 27 ic R6551 acia CTS 1.8432 R6500 r6522 R6551* rockwell R65C00
R6551* rockwell

Abstract:
Text: line (D0-D7) pins transfer data between the processor and the ACIA. These lines are bi-directional and , microprocessor and the ACIA. The Command Register controls parity, receiver echo mode, transmitter interrupt , R/W pin allows the processor to read the data supplied by the ACIA , a low allows a write to the ACIA. , ACIA. A 0 indicates a low level (true condition) and a 1 indicates a high level (false). Whenever , circuits to the ACIA. Figure 4 shows the Transmitter and Receiver layout. The Control Register selects


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PDF R65C51 R65C51 R6551 28-pin R6551* rockwell dud 1237 Rockwell R65C51 IFF16 R6551 27
acia 6850

Abstract:
Text: the bus-programmed master reset which must be applied prior to operating the ACIA. After master , of an interrupt or in the ACIA's turn in a polling sequence. A character may be written into the , control over the ACIA. ACIA Bi-Directional Data (D0-D7) - The bi-directional data lines (D0-D7) allow for , /output data buffers and clocks data to and from the ACIA. This signal will normally be a derivative of , compatible and is used to control the direction of data flow through the ACIA's input/output data bus


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PDF EF6850 EF68A50 EF68B50 EF6850 EF6800 CB-68 acia 6850 EF68850 EF68B50 68a50 EF68A50CV 6850 acia 6850 EF6885
Rockwell R65C51

Abstract:
Text: between the system microprocessor and the ACIA. Read/Write (R/W) The R/W input, generated by the , data supplied by the ACIA , a low allows a write to the ACIA. Interrupt Request (IRQ) The IRQ pin is , processor and the ACIA. These lines are bi-directional and are normally high-impedance except during Read , ACIA. A 0 indicates a low level (true condition) and a 1 indicates a high level (false). Whenever , becomes an output (at 16x the baud rate) and can be used to slave other circuits to the ACIA. Figure 4


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PDF R65C51 R65C51 28-PIN Jx45c Rockwell R65C51 6200 rockwell THH20 R65C21 R6551 R6500 DSR 505 74157 pin diagram TTL catalog
R6551* rockwell

Abstract:
Text: Ready (Bit 6) These bits reflect the levels of the DCD and DSR inputs to the ACIA. A 0 indicates a low , rate as the transmitter, then RxC becomes an output and can be used to slave other circuits to the ACIA. , to the ACIA. Figure 4 shows the ACIA interface signals associated with the microprocessor and the , eight data line (D0-D7) pins transfer data between the proc essor and the ACIA. These lines are , microprocessor and the ACIA. NOTE: The specified maximum cycle time for the signal on this input is 40 ¡¿s. This


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PDF R6551 R6551 28-pin R6500, R6500/' R6551* rockwell R6551 27 R6551AC
HD63B50P

Abstract:
Text: , Receive Register and Transmit Register. 24-pin dual-in-line type package is used for the ACIA. Internal , mask bit of MPU should be released after the master reset of ACIA. (MPU interrupt should be prohibited until MPU program completes the master reset of ACIA. ) Transmit Data Register (TDR) and Receive Data , reading the ACIA Status Register either as a result of an interrupt or in the ACIA's turn in a polling , (CROandCRl) determine the divide ratios utilized in both the transmitter and receiver section of the ACIA.


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PDF D6350/H D6850 HD6350/HD6850 HMCS6800 IHD6350 HD63B50P hitachi marking format h063 HD63A50P HD6350P HD6850 HD6350 MC6850 HD6850P Hitachi HD63B50
EF6850CM

Abstract:
Text: addresslng the ACIA_and selecting the Receive Data Register with RS and R/W high when the ACIA is enabled , means of the bus-programmed master reset which must be applied prior to operating the ACIA. After master , an interrupt or in the ACIA's turn in a polling sequence. A character may be written into the , complete control over the ACIA. ACIA Bidirectional Data (DO-D7I — The bidirectional data lines (D0-D7 , high-Impedance input that is TTL compatible and is used to control the direction of data flow through the ACIA's


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PDF EF6860 EF6800 EF6850 MIL-STD-883C CB-68 CB-520 CB-707 EF6850CM IR receiver TK 19 205 EF6850C EF6BB50 ef68b50 EF6S50JM EF6850CV LCCC28
A6551

Abstract:
Text: inputs to tt ACIA. A 0 indicates a low level (true condition) and a 1 indicate a high level (false). , as the transmitter, then RxC becomes an output and can be used to slave other circuits to the ACIA. , data between the processor and the ACIA. These lines are bi-directional and are normally high-impedance , system microprocessor and the ACIA. i Read/Write Only the Command and Control registers can both be , Xocessor to read the data supplied by the ACIA , a low allows i a write to the ACIA. 2-301


Original
PDF R65C51 R65C51 R6551 DO-07 A6551 R6551* rockwell Rockwell R65C51 R65C21 R6500 cI 74157 ats 2300 74157 ttl
Not Available

Abstract:
Text: reflect the levels of the DCD and DSR inputs to the ACIA. A 0 indicates a low level (true condition) and , transmitter, then RxC becomes an output and can be used to slave other circuits to the ACIA. Figure 3 shows , ACIA. 00-07 - O O DATA BUS BUFFERS INTERRUPT LOGIC CSO - I/O C S Ï- CONTROL , between the proc­ essor and the ACIA. These lines are bi-directional and are nor­ mally high-impedance , the system microprocessor and the ACIA. NOTE! The specified maximum cycle time for the signal on this


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PDF 11D73 D013203 R6551 R6551 DD13SSB R6551_
68B50

Abstract:
Text: bus-programmed master reset which must be applied prior to operating the ACIA. After master resetting the ACIA , of an interrupt or in the ACIA's turn in a polling sequence. A character may be written into the , the ACIA. ACIA Bidirectional Data (D0-D7) - The bidirectional data lines (D0-D7) allow for data , data buf fers and clocks data to and from the ACIA. This signal will normally be a derivative of the EF , that is TTL compatible and is used to control the direction of data flow through the ACIA's input


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PDF
1981 - 65c51

Abstract:
Text: ) and Data Set Ready (Bit 6) These bits reflect the levels of the DCDB and DSRB inputs to the ACIA. A 0 , to the ACIA. Figure 3 shows the Transmitter and Receiver layout. Figure 3 Transmitter/Receiver , system microprocessor and the ACIA. Read/Write (RWB) The RWB input, generated by the microprocessor , supplied by the ACIA , a low allows a write to the ACIA. 13 Interrupt Request (IRQB) The IRQB pin is , processor and the ACIA. These lines are bidirectional and are normally high-impedance except during Read


Original
PDF W65C51N 65c51 Rockwell 65C51 W65C51N 6551 rockwell CPD65C51 i/65c51
1981 - W65C51S

Abstract:
Text: ACIA. A 0 indicates a low level (true condition) and a 1 indicates a high level (false). Whenever , used to slave other circuits to the ACIA. Figure 3 shows the Transmitter and Receiver layout , REGISTERS VCC VSS The eight data line (D0-D7) pins transfer data between the processor and the ACIA. , between the system microprocessor and the ACIA. H H Table 1 ACIA Register Selection Register , allows the processor to read the data supplied by the ACIA , a low allows a write to the ACIA. Interrupt


Original
PDF W65C51S W65C51S W65C51 74157 3 bit shift register R6551 TIC1 W65C21 W65C22S W65C51S-14
MC68B50P

Abstract:
Text: of an interrupt or in the ACIA's turn in a polling sequence. A character may be written into the , . These signals permit the MPU to have complete control over the ACIA. ACIA Bidirectional Data (D0-D7) - , TTL-compatible input that enables the bus input/output data buffers and clocks data to and from the ACIA. This , of data flow through the ACIA's input/output data bus interface. When Read/Write is high (MPU Read , signal is used to select read-only or write-only registers within the ACIA. Chip Select (CSO, CS1, CS2


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PDF MC6850 MC6800 MC6850/D A11225-9 MC6850/D MC68B50P MC6850P SSC 9500 ACIA MC6809 MC68850P MC6850D MC6850CL MC68B50 MC6860L
R6551 27

Abstract:
Text: and DSR inputs to the ACIA. A 0 indicates a low level (true condition) and a 1 indicates a high level , circuits to the ACIA. Figure 3 shows the Transmitter and Receiver layout. RECEIVER SHIFT REGISTER , between the system microprocessor and the ACIA. NOTE: The specified maximum cycle time for the signal on , R/W pin allows the processor to read the data supplied by the ACIA , a low allows a write to the ACIA. , ) pins transfer data between the processor and the ACIA. These lines are bi-directional and are normally


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PDF R6551 R6551 28-PIN IS50I R6551 27 DCW 150 R6522 R6551* rockwell R65C00 B432 r6520 R6500 car transmitter & Reciever diagrams
R6551 27

Abstract:
Text: for these conditions These bits reflect the levels of the DCD and DSR inputs to the ACIA. A 0 , between the processor and the ACIA. These lines are bi-directional and are normally high-impedance except , system 02 clock and clocks all data transfers between the system microprocesscr and the ACIA. NOTE: The , receiving. Reception will resume only after a Stop Bit is encountered by the ACIA. Figure 17 shows the , IRQ (Bit 7) in the data read from the Status Register If not set, the interrupt source is not the ACIA.


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PDF R6551 R6551 R6551 27 R6522 R6551* rockwell 74157 74157 pin diagram R6500 R6520 R65C00
6551 acia

Abstract:
Text: the ACIA. 5-32 This Material Copyrighted By Its Respective Manufacturer ISO-CMOS MD65SC51B , MD65SC51B to allow fast response from the pP to the ACIA. The serial port provides signals which may be , other words, "negated") the ACIA's transmitter is disabled. Data Terminal Ready . The DTR signal , disables echo mode (for echo to be enabled, COMb2 and COMb3 must both be 0). When in echo mode, the ACIA's , for the ACIA. The SR contains several error bits, two bits to display the state of the transmit and


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PDF MD65SC51B 1/16th t/16th 6551 acia MD65SC51BE MD65SC51BP SRB-4 6551acia MMD6150
1981 - 65c51

Abstract:
Text: DCDB and DSRB inputs to the ACIA. A 0 indicates a low level (true condition) and a 1 indicates a high , can be used to slave other circuits to the ACIA. Figure 3 shows the Transmitter and Receiver layout , microprocessor and the ACIA. Read/Write (RWB) The RWB input, generated by the microprocessor controls the , ACIA , a low allows a write to the ACIA. Interrupt Request (IRQB) 12 The IRQB pin is an , processor and the ACIA. These lines are bidirectional and are normally high-impedance except during Read


Original
PDF W65C51N 65c51 W65C51N 6551 acia Synertek W65C51S acia 6850 cpd65c51 R6551 R6551 27 G65SC51
1981 - Not Available

Abstract:
Text: bits reflect the levels of the DCDB and DSRB inputs to the ACIA. A 0 indicates a low level (true , becomes an output and can be used to slave other circuits to the ACIA. Figure 4 shows the Transmitter and , between the system microprocessor and the ACIA. Read/Write (RWB) The RWB input, generated by the , data supplied by the ACIA , a low allows a write to the ACIA. 13 Interrupt Request (IRQB) The , data between the processor and the ACIA. These lines are bidirectional and are normally high-impedance


Original
PDF W65C51S
1981 - W65C51S

Abstract:
Text: bits reflect the levels of the DCDB and DSRB inputs to the ACIA. A 0 indicates a low level (true , transmitter, then RxC becomes an output and can be used to slave other circuits to the ACIA. Figure 4 shows , microprocessor and the ACIA. Read/Write (RWB) The RWB input, generated by the microprocessor controls the , ACIA , a low allows a write to the ACIA. 13 Interrupt Request (IRQB) The IRQB pin is an , processor and the ACIA. These lines are bidirectional and are normally high-impedance except during Read


Original
PDF W65C51S W65C51S W65C51S Asynchronous Communications Interface Adapter (ACIA) 65c51 acia 6850 6551 acia R6551* rockwell acia 6850 baud rate generator cpd65c51 G65SC51 W65C51S6TPG-14
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