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CCH75K3 GE Critical Power CCH Series, 75 Watt Swithing Power Supply
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AC-75CD700UV-QS AC Electronics Bristol Electronics 305 - -

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AC-75CD700UV-QS Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2013 - Not Available

Abstract: No abstract text available
Text: TM Model Number AC-75CD700UV-QS TM POWER DESIGNS Type: Constant Current LED Driver Input Voltage: 120-277V Input Frequency: 50/60Hz MultiCurrent Switching and Dimming ELECTRICAL SPECIFICATIONS: Output Input Power Power Max. Input Current Minimum Max. PF THD (full load) (full load) Output Voltage Output Current T case Max. Minimum Eficiency Dimming Dimming IP Starting Up To Protocol Range Rating Temp. 37W 43W 0.36A @ 120V 0.15A @ 277V


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PDF AC-75CD700UV-QS 20-277V 50/60Hz 5-107V 350mAÂ 410mAÂ
TC59LM818DMB

Abstract: TC59LM818DMB-33
Text: CMOS 301,989,888 (FCRAMTM)TC59LM818DMB 4,194,304 ×4 ×18 DS/ QS 600M / FCRAMTM DDR SDRAM , (DDR) DS/ QS (/)/ · (CLK & CLK ) CS , FN CLK (DQ & QS ) CLK CLK CLK CLK · · , FN PD CLK, CLK DS / QS / VDD (+2.5 V) VSS () VDDQ (+1.5 , VDDQ DQ7 H DQ9 DS QS DQ8 J VREF VSS VDD A14 K CLK CLK FN , / DS QS DQ DQ0~DQ17 : TC59LM818DMB 4 32768 × 128 × 18 DQ Rev 1.4


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PDF TC59LM818DMB-33 TC59LM818DMB 300MHz 333MHz 666Mbps TC59LM818DMB
1990 - TC59LM836DKG-33

Abstract: ba1 46 bl 9 a2
Text: TC59LM836DKG CMOS 301,989,888 (FCRAMTM)TC59LM836DKG 2,097,152 4 36bit DS/ QS 600M / FCRAMTM DDR , () () 95 mA 90 mA 15 mA 15 mA lDD6 · () · (DDR) DS/ QS (/)/ · (CLK & CLK ) CS FN CLK (DQ & QS ) CLK CLK CLK CLK · : · : 600 M / · 4 · & · , minIRC = minIOUT = 0mA Burst Length = 4CAS Latency = 6Free running QS mode 0 V VIN VIL (AC) (max)VIH , 1, 2 IDD2P () : tCK = min PD = VIL () CAS Latency = 6Free running QS mode 0 V VIN VIL


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PDF TC59LM836DKG-33 TC59LM836DKG 36bit TC59LM836DKG P-TFBGA144-1119-0 15MIN ba1 46 bl 9 a2
TC59LM818DMG-33

Abstract: P-BGA60-0917-1
Text: TC59LM818DMG CMOS 301,989,888 (FCRAMTM)TC59LM818DMG 4,194,304 ×4 ×18 DS/ QS 600M / FCRAMTM DDR , 210 mA 60 mA 15 mA · (DDR) DS/ QS (/)/ · · 5.0 ns 3.75 ns 3.33 ns 22.5 ns 22.5 ns , () () lDD6 () tCK -40 4.5 ns CL = 4 (CLK & CLK ) CS , FN CLK (DQ & QS ) CLK CLK CLK CLK , CS FN PD CLK, CLK DS / QS / VDD (+2.5 V) VSS () VDDQ , VSSQ VDDQ DQ7 H DQ9 DS QS DQ8 J VREF VSS VDD A14 K CLK CLK


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PDF TC59LM818DMG-33 TC59LM818DMG 300MHz 15MIN TC59LM818DMB 333MHz P-BGA60-0917-1
1990 - TC59LM836DKB

Abstract: TC59LM836DKB-33
Text: 301,989,888 (FCRAMTM)TC59LM836DKB 2,097,152 4 36bit DS/ QS 600M / FCRAMTM DDR SDRAM , 15 mA 15 mA lDD6 · () · (DDR) DS/ QS (/)/ · (CLK & CLK ) CS FN CLK (DQ & QS ) CLK CLK CLK CLK · : · : 600 M / · 4 · & · · , minIRC = minIOUT = 0mA Burst Length = 4CAS Latency = 6Free running QS mode 0 V VIN VIL (AC) (max)VIH , 1, 2 IDD2P () : tCK = min PD = VIL () CAS Latency = 6Free running QS mode 0 V VIN VIL


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PDF TC59LM836DKB-33 TC59LM836DKB 36bit TC59LM836DKB 36DKB-33 TC59LM836DMB 333MHz
2005 - TC59LM818DMG-33

Abstract: No abstract text available
Text: with both edges of DS / QS . · Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and QS ) is aligned to the crossings of , Down Control CLK, CLK Clock Input DS / QS Write/Read Data Strobe VDD Power (+2.5 V , DS QS DQ8 J VREF VSS VDD A14 K CLK CLK FN A13 L A12 PD , COLUMN DECODER READ DATA BUFFER WRITE ADDRESS LATCH/ ADDRESS COMPARATOR DS QS WRITE


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PDF TC59LM818DMG-33 288Mbits 304-WORDS 18-BITS TC59LM818DMG
2004 - TC59LM818DMB

Abstract: TC59LM818DMB-30
Text: Operation · Double Data Rate (DDR) Data input/output are synchronized with both edges of DS / QS . · , edge of CLK. Output data (DQs and QS ) is aligned to the crossings of CLK and CLK . Fast clock cycle , Function Control PD Power Down Control CLK, CLK Clock Input DS / QS Write/Read Data , VSSQ VDDQ DQ7 H DQ9 DS QS DQ8 J VREF VSS VDD A14 K CLK CLK , LATCH/ ADDRESS COMPARATOR DS QS WRITE DATA BUFFER DQ BUFFER DQ0~DQ17 Note: The


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PDF TC59LM818DMB-30 288Mbits 304-WORDS 18-BITS TC59LM818DMB
2005 - TC59LM836DKB

Abstract: TC59LM836DKB-33
Text: Operation · Double Data Rate (DDR) Data input/output are synchronized with both edges of DS / QS . · , edge of CLK. Output data (DQs and QS ) is aligned to the crossings of CLK and CLK . Fast clock cycle , operation ; tCK = min; IRC = min, IOUT = 0mA ; Burst Length = 4, CAS Latency = 6, Free running QS mode , ; tCK = min, PD = VIL (power down) ; CAS Latency = 6, Free running QS mode ; 0 V VIN VIL (AC) (max , QS mode ; 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ ; Address inputs change once per


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PDF TC59LM836DKB-33 288Mbits 152-WORDS 36-BITS TC59LM836DKB
2005 - TC59LM818DMB-33

Abstract: TC59LM818DMB
Text: Operation · Double Data Rate (DDR) Data input/output are synchronized with both edges of DS / QS . · , edge of CLK. Output data (DQs and QS ) is aligned to the crossings of CLK and CLK . Fast clock cycle , Function Control PD Power Down Control CLK, CLK Clock Input DS / QS Write/Read Data , VSSQ VDDQ DQ7 H DQ9 DS QS DQ8 J VREF VSS VDD A14 K CLK CLK , / ADDRESS COMPARATOR DS QS WRITE DATA BUFFER DQ BUFFER DQ0~DQ17 Note: The TC59LM818DMB


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PDF TC59LM818DMB-33 288Mbits 304-WORDS 18-BITS TC59LM818DMB
2002 - Not Available

Abstract: No abstract text available
Text: synchronized with both edges of DS / QS . · Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and QS ) is aligned to the , Input DS / QS Write/Read Data Strobe VDD Power (+2.5 V) VSS Ground VDDQ Power , VSSQ VDDQ DQ7 H DQ9 DS QS DQ8 J VREF VSS VDD A14 K CLK CLK , COLUMN DECODER READ DATA BUFFER WRITE ADDRESS LATCH/ ADDRESS COMPARATOR DS QS WRITE


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PDF TC59LM818DMGI-40 304-WORDS 18-BITS TC59LM818DMGI
2002 - TC59LM818DMG-30

Abstract: TC59LM8
Text: Data Rate (DDR) Data input/output are synchronized with both edges of DS / QS . · Differential Clock , . Output data (DQs and QS ) is aligned to the crossings of CLK and CLK . Fast clock cycle time of 3.0 ns , Select FN Function Control PD Power Down Control CLK, CLK Clock Input DS / QS , G DQ10 V SSQ VDD Q DQ7 H DQ9 DS QS DQ8 J VREF V SS VDD A14 , COLUMN DECODER READ DATA BUFFER WRITE A DDRESS LATCH/ ADDRESS COMPARATOR DS QS WRITE


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PDF TC59LM818DMG-30 304-WORDS 18-BITS TC59LM818DMG TC59LM818DMG TC59LM8
2003 - unidirectional current controller circuit

Abstract: SSTL-18 TC59LM836DMB-30
Text: Operation · Double Data Rate (DDR) Data input/output are synchronized with both edges of DS / QS . · , edge of CLK. Output data (DQs and QS ) is aligned to the crossings of CLK and CLK . Fast clock cycle , ; Burst Length = 4, CAS Latency = 6, Free running QS mode ; 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN , = 6, Free running QS mode ; 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ ; Other input , min, IRC = min ; Burst Length = 4, CAS Latency = 6, Free running QS mode ; 0 V VIN VIL (AC) (max


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PDF TC59LM836DMB-30 152-WORDS 36-BITS TC59LM836DMB unidirectional current controller circuit SSTL-18
2005 - Not Available

Abstract: No abstract text available
Text: ) Data input/output are synchronized with both edges of DS / QS . · Differential Clock (CLK and CLK , and QS ) is aligned to the crossings of CLK and CLK . Fast clock cycle time of 3.0 ns minimum Clock , VDDQ QS VDD FN 6 VDD DQ1 DQ2 DQ3 DQ5 DQ6 DQ7 DQ8 A14 A13 NC BA0 A10 A1 VDD FN PD C D E F G H J K L M N P R CLK, CLK DS / QS VDD VSS VDDQ VSSQ VREF NC A12 A11 A8 A5 VSS CS A9 A7 A6 , READ DATA BUFFER WRITE DATA BUFFER DS QS DQ BUFFER DQ0~DQ17 Note: The TC59LM818DMB


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PDF TC59LM818DMB-30 288Mbits 304-WORDS 18-BITS TC59LM818DMB
2003 - Not Available

Abstract: No abstract text available
Text: revision from D-die to F-die - Corrected typo - Corrected DQS to DS and QS (DQS -> DS and QS ) in AC timing , Synchronous Operation - Double Data Rate (DDR) - Data input/output are synchronized with both edges of DS / QS , positive edge of CLK. - Output data (DQs and QS ) is aligned to the crossings of CLK and CLK. Fast clock , K4C89183AF Pin Names Pin A0 ~ A14 BA0, BA1 DQ0 ~ DQ17 CS FN PD CLK, CLK DS/ QS VDD VSS VDDQ VSSQ VREF NC , A7 A6 A4 QS VDD FN CS BA1 A0 A2 A3 DQ8 A14 A13 NC BA0 A10 A1 VDD F G DQ12 DQ11 DQ10 VssQ VDDQ VssQ


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PDF K4C89183AF 288Mb 800Mbps 400Mhz) 8K/32ms 800Mbps/pin 400MHz, 667Mbps/pin 333MHz,
2005 - Not Available

Abstract: No abstract text available
Text: Data Rate (DDR) Data input/output are synchronized with both edges of DS / QS . · Differential Clock , . Output data (DQs and QS ) is aligned to the crossings of CLK and CLK . Fast clock cycle time of 3.0 ns , DQ4 VDDQ VSSQ VDDQ QS VDD FN 6 VDD DQ1 DQ2 DQ3 DQ5 DQ6 DQ7 DQ8 A14 A13 NC BA0 A10 A1 VDD FN PD C D E F G H J K L M N P R CLK, CLK DS / QS VDD VSS VDDQ VSSQ VREF NC A12 A11 A8 A5 VSS CS , READ DATA BUFFER WRITE DATA BUFFER DS QS DQ BUFFER DQ0~DQ17 Note: The TC59LM818DMG


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PDF TC59LM818DMG-30 288Mbits 304-WORDS 18-BITS TC59LM818DMG
2005 - Not Available

Abstract: No abstract text available
Text: synchronized with both edges of DS / QS . · Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and QS ) is aligned to the , Function Control PD Power Down Control CLK, CLK Clock Input DS / QS Write/Read Data , VSSQ VDDQ DQ7 H DQ9 DS QS DQ8 J VREF VSS VDD A14 K CLK CLK , / ADDRESS COMPARATOR DS QS WRITE DATA BUFFER DQ BUFFER DQ0~DQ17 Note: The TC59LM818DMGI


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PDF TC59LM818DMGI-37 288Mbits 304-WORDS 18-BITS TC59LM818DMGI
2003 - K4C89093AF

Abstract: No abstract text available
Text: Data input/output are synchronized with both edges of DS / QS . - Differential Clock (CLK and CLK , (DQs and QS ) is aligned to the crossings of CLK and CLK. Fast clock cycle time of 2.5 ns minimum - , DS/ QS Write/Read Strobe VDD Power (+2.5V) VSS Ground VDDQ Power (+1.8V) (for I , VssQ VDDQ NC H DQ8 DS QS DQ4 J VREF Vss VDD A14 K CLK CLK , BURST COUNTER READ DATA BUFFER WRITE ADDRESS LATCH ADDRESS COMPARATOR DS QS WRITE DATA


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PDF K4C89093AF 800Mbps 400Mhz) 800Mb1 8K/32ms 800Mbps/pin 400MHz, 667Mbps/pin 333MHz, K4C89093AF
2003 - Not Available

Abstract: No abstract text available
Text: edges of DS / QS . • Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and QS ) is aligned to the crossings of CLK , Input DS / QS Write/Read Data Strobe VDD Power (+2.5 V) VSS Ground VDDQ Power , DQ11 VDDQ VSSQ DQ6 G DQ10 VSSQ VDDQ DQ7 H DQ9 DS QS DQ8 J , READ DATA BUFFER WRITE ADDRESS LATCH/ ADDRESS COMPARATOR DS QS WRITE DATA BUFFER DQ


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PDF TC59LM818DMB-30 304-WORDS 18-BITS TC59LM818DMB
2005 - TC59LM836DKB

Abstract: TC59LM836DKB-30 DQ159
Text: Operation · Double Data Rate (DDR) Data input/output are synchronized with both edges of DS / QS . · , edge of CLK. Output data (DQs and QS ) is aligned to the crossings of CLK and CLK . Fast clock cycle , ; tCK = min; IRC = min, IOUT = 0mA ; Burst Length = 4, CAS Latency = 6, Free running QS mode ; 0 V , state ; tCK = min, PD = VIL (power down) ; CAS Latency = 6, Free running QS mode ; 0 V VIN VIL (AC , Latency = 6, Free running QS mode ; 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ ; Address inputs


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PDF TC59LM836DKB-30 288Mbits 152-WORDS 36-BITS TC59LM836DKB DQ159
2004 - TC59LM836DKB

Abstract: TC59LM836DKB-30
Text: Data Rate (DDR) Data input/output are synchronized with both edges of DS / QS . · Differential Clock , . Output data (DQs and QS ) is aligned to the crossings of CLK and CLK . Fast clock cycle time of 3.0 ns , = 6, Free running QS mode ; 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ, Address inputs , running QS mode ; 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ ; Other input signals change one , = min ; Burst Length = 4, CAS Latency = 6, Free running QS mode ; 0 V VIN VIL (AC) (max), VIH


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PDF TC59LM836DKB-30 288Mbits 152-WORDS 36-BITS TC59LM836DKB
2004 - Not Available

Abstract: No abstract text available
Text: (DDR) Data input/output are synchronized with both edges of DS / QS . · Differential Clock (CLK and CLK , and QS ) is aligned to the crossings of CLK and CLK . Fast clock cycle time of 3.0 ns minimum Clock , , CAS Latency = 6, Free running QS mode ; 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ, Address , ) ; CAS Latency = 6, Free running QS mode ; 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ ; Other , = 4, CAS Latency = 6, Free running QS mode ; 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ


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PDF TC59LM836DMB-30 288Mbits 152-WORDS 36-BITS TC59LM836DMB
2004 - Not Available

Abstract: No abstract text available
Text: (DDR) Data input/output are synchronized with both edges of DS / QS . · Differential Clock (CLK and CLK , and QS ) is aligned to the crossings of CLK and CLK . Fast clock cycle time of 3.0 ns minimum Clock , , CAS Latency = 6, Free running QS mode ; 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ, Address , ) ; CAS Latency = 6, Free running QS mode ; 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ ; Other , = 4, CAS Latency = 6, Free running QS mode ; 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ


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PDF TC59LM836DKB-30 288Mbits 152-WORDS 36-BITS TC59LM836DKB
2003 - SSTL-18

Abstract: TC59LM818DMB TC59LM818DMB-30
Text: Operation · Double Data Rate (DDR) Data input/output are synchronized with both edges of DS / QS . · , edge of CLK. Output data (DQs and QS ) is aligned to the crossings of CLK and CLK . Fast clock cycle , Function Control PD Power Down Control CLK, CLK Clock Input DS / QS Write/Read Data , VSSQ VDDQ DQ7 H DQ9 DS QS DQ8 J VREF VSS VDD A14 K CLK CLK , COMPARATOR DS QS WRITE DATA BUFFER DQ BUFFER DQ0~DQ17 Note: The TC59LM818DMB configuration is


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PDF TC59LM818DMB-30 304-WORDS 18-BITS TC59LM818DMB SSTL-18
2003 - Not Available

Abstract: No abstract text available
Text: Data Rate (DDR) Data input/output are synchronized with both edges of DS / QS . • Differential Clock , . Output data (DQs and QS ) is aligned to the crossings of CLK and CLK . Fast clock cycle time of 3.75 ns , , CLK Clock Input DS / QS Write/Read Data Strobe VDD Power (+2.5 V) VSS Ground , DQ11 VDDQ VSSQ DQ6 G DQ10 VSSQ VDDQ DQ7 H DQ9 DS QS DQ8 J , BUFFER WRITE ADDRESS LATCH/ ADDRESS COMPARATOR DS QS WRITE DATA BUFFER DQ BUFFER DQ0


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PDF TC59LM818DMBI-37 304-WORDS 18-BITS TC59LM818DMBI
2003 - SSTL-18

Abstract: TC59LM818DMBI TC59LM818DMBI-40
Text: ) Data input/output are synchronized with both edges of DS / QS . · Differential Clock (CLK and CLK , and QS ) is aligned to the crossings of CLK and CLK . Fast clock cycle time of 4.0 ns minimum Clock , , CLK Clock Input DS / QS Write/Read Data Strobe VDD Power (+2.5 V) VSS Ground , DQ5 F DQ11 VDDQ VSSQ DQ6 G DQ10 VSSQ VDDQ DQ7 H DQ9 DS QS , READ DATA BUFFER WRITE ADDRESS LATCH/ ADDRESS COMPARATOR DS QS WRITE DATA BUFFER DQ


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PDF TC59LM818DMBI-40 304-WORDS 18-BITS TC59LM818DMBI SSTL-18 TC59LM818DMBI-40
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