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Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
LTC2364HMS-16#TRPBF Linear Technology LTC2364-16 - 16-Bit, 250ksps, Pseudo-Differential Unipolar SAR ADC with 94.7dB SNR; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C
LTC2364IMS-18#TRPBF Linear Technology LTC2364-18 - 18-Bit, 250ksps, Pseudo-Differential Unipolar SAR ADC with 97dB SNR; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C
LTC2367HMS-16#TRPBF Linear Technology LTC2367-16 - 16-Bit, 500ksps, Pseudo- Differential Unipolar SAR ADC with 94.7dB SNR; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C
LTC2367IMS-18#TRPBF Linear Technology LTC2367-18 - 18-Bit, 500ksps, Pseudo-Differential Unipolar SAR ADC with 97dB SNR; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C
LTC2368HMS-16#TRPBF Linear Technology LTC2368-16 - 16-Bit, 1Msps, Pseudo- Differential Unipolar SAR ADC with 94.7dB SNR; Package: MSOP; Pins: 16; Temperature Range: -40°C to 125°C
LTC2368IMS-18#TRPBF Linear Technology LTC2368-18 - 18-Bit, 1Msps, Pseudo-Differential Unipolar SAR ADC with 97dB SNR; Package: MSOP; Pins: 16; Temperature Range: -40°C to 85°C

AAL5 SAR Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2006 - 3G ATM

Abstract: No abstract text available
Text: CPU Interface Add LANE AAL5 SAR Port A as MII Port A as POS-PHY Port A as UTOPIA T RTP in HDLC D M HDLC Process UDP/RTP Disassembly Packet Routing AAL5 SAR Remove LANE TxA FIFO Packet Assembly HDLC Process TX Path TxB FIFO AAL5 SAR Port B Port A as MII Port A as POS-PHY Port A as UTOPIA xxPCM B U S RTP Assembly RTP in HDLC AAL5 SAR Port B Figure 1 - MT922x0 Block Diagram 1 , discarded, sent to CPU as AAL0 cell, looped back to Port A or Port B, or reassembled by an AAL5 SAR engine


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PDF ZLAN-15 MT922x0 MT92220 MT92210 3G ATM
2002 - pacemaker

Abstract: VSC2400-30 VSC2400-30UY PB-VSC2400-30-001
Text: Management and SAR Engine AAL5 SAR 4OC-48 AAL5 SAR supporting 256K sessions 4Enhanced interworking , Overall 4OC-48 throughput 4Enhanced AAL5 SAR improves multiservice interworking 4Manages 256K input , , congestion control, a wire By provisioning for both rate and delay guarantees for packet speed AAL5 SAR , requirements. capabilities for multiservice applications: · AAL5 SAR · Unified Packet and Cell buffer and , VSC2400-30UY OC-48 Traffic Management and SAR Engine UTOPIA/POS PHY Interface OC-48 AAL5 SAR


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PDF VSC2400-30) OC-48 4OC-48 VSC2400-30UY OC-48 pacemaker VSC2400-30 VSC2400-30UY PB-VSC2400-30-001
2002 - AAL5 SAR

Abstract: TAAD08JU21BCLS2-DB TR008 2032 oam AF-VTOA-0113 voice control vc 200 RF limited
Text: Product Brief, Rev. 1 April 2002 TAAD08JU21BCLS2-DB SAR -2K AAL2/ AAL5 SAR Engine Features s , .363.2. Provides AAL5 SAR functionality per ITU I.363.5. Provides quality of service (QoS) connection identifier , and AAL5 conversion Description SAR -2K provides a flexible network-interface solution for , whereby AAL5 VCs are routed through to the system interface toward their destinations. SAR -2K provides support for up to 2032 bidirectional AAL5 VCs via an internal context memory. Communication with SAR


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PDF TAAD08JU21BCLS2-DB PB02-055ATM-1 PB02-055ATM) AAL5 SAR TR008 2032 oam AF-VTOA-0113 voice control vc 200 RF limited
2003 - TAAD08JU2

Abstract: voice control vc 200 RF limited APC 2020 B TR008 AF-VTOA-0113
Text: Product Brief May 2003 TAAD08JU21BCLSL3A-DB ( SAR -1K) AAL2/ AAL5 SAR Engine, Versions 2.1 and , .363.2. s Provides AAL5 SAR functionality per ITU I.363.5. s Provides quality of service (QoS , Agere Systems Inc. 0.16 µm CMOS technology, the chip implements AAL2 and AAL5 SAR functions. Support , 2032 bidirectional AAL5 VCs via an internal context memory. Communication with SAR -1K is accomplished , cross connect s AAL2 and AAL5 conversion SAR -1K provides a complete ATM adaptation layer


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PDF TAAD08JU21BCLSL3A-DB PB03-109ATM-1 PB03-109ATM) TAAD08JU2 voice control vc 200 RF limited APC 2020 B TR008 AF-VTOA-0113
2003 - SAR-500

Abstract: AF-VTOA-0113 TAAD08JU2 TR008 voice control vc 200 RF limited
Text: Product Brief May 2003 TAAD08JU21BCLSU3A-DB ( SAR -500) AAL2/ AAL5 SAR Engine, Versions 2.1 and , .363.2. s Provides AAL5 SAR functionality per ITU I.363.5. s Provides quality of service (QoS , AAL2 cross connect s AAL2 and AAL5 conversion Description SAR -500 provides a flexible , implements AAL2 and AAL5 SAR functions. Support for AAL2 is provided via an AAL/CPS function that maps , destinations. SAR -500 provides support for up to 2032 bidirectional AAL5 VCs via an internal context memory


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PDF TAAD08JU21BCLSU3A-DB SAR-500) PB03-110ATM-1 PB03-110ATM) SAR-500 AF-VTOA-0113 TAAD08JU2 TR008 voice control vc 200 RF limited
2003 - Not Available

Abstract: No abstract text available
Text: Product Brief May 2003 TAAD08JU21BCLS2-DB ( SAR -2K) AAL2/ AAL5 SAR Engine, Versions 2.1 and 3.1 , per ITU I.363.2. Provides AAL5 SAR functionality per ITU I.363.5. Provides quality of service (QoS , Inc. 0.16 µm CMOS technology, the chip implements AAL2 and AAL5 SAR functions. Support for AAL2 is , bidirectional AAL5 VCs via an internal context memory. Communication with SAR -2K is accomplished through , to area, power, and function. TAAD08JU21BCLS2-DB ( SAR -2K) AAL2/ AAL5 SAR Engine, Versions 2.1 and


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PDF TAAD08JU21BCLS2-DB PB02-055ATM-2 PB02-055ATM-1)
2002 - AAL5 SAR

Abstract: VSC2401-25 pacemaker OC-48 pacemaker cross reference
Text: OC-48 Throughput Wire-speed AAL5 SAR Weighted Random Early Detection (WRED) with per-flow , Required AAL5 SAR : A P P L I C AT I O N S : OC-48 AAL5 SAR supporting 256K sessions Part of , classification, policing, as well as wire speed AAL5 SAR functions. OSCAR delivers flexible per-flow policing , complete packet and cell interworking capabilities for multiservice applications: AAL5 SAR : Unified , OSCAR (VSC2401-25) OC-48 SAR Engine F E AT U R E S : Overall: OC-48 throughput Manages up to 256K


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PDF VSC2401-25) OC-48 AAL5 SAR VSC2401-25 pacemaker pacemaker cross reference
2001 - pacemaker

Abstract: digital pacemaker VSC2400-25UY VSC2400-25
Text: Early packet discard/Partial packet discard AAL5 SAR · OC-48 AAL5 SAR supporting 256K sessions , cell classification, policing, wire speed AAL5 SAR , a dual leaky bucket shaper, and an optimum , provides complete packet and cell interworking capabilities for multiservice applications: · AAL5 SAR · , congestion management solution · Wire-speed AAL5 SAR enables Multi-Service applications · Unmatched QoS , PaceMaker 2.5TM (VSC2400-25) OC-48 Traffic Management and SAR Engine Traffic Management Family


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PDF VSC2400-25) OC-48 pacemaker digital pacemaker VSC2400-25UY VSC2400-25
2002 - digital pacemaker

Abstract: pacemaker VSC2400-30 VSC2400-30UY
Text: Management and SAR Engine AAL5 SAR !OC-48 AAL5 SAR supporting 256K sessions !Enhanced interworking , Overall !OC-48 throughput !Enhanced AAL5 SAR improves multiservice interworking !Manages 256K input , , congestion control, a wire By provisioning for both rate and delay guarantees for packet speed AAL5 SAR , requirements. capabilities for multiservice applications: · AAL5 SAR Specifications: · Unified Packet , VSC2400-30UY OC-48 Traffic Management and SAR Engine UTOPIA/POS PHY Interface OC-48 AAL5 SAR


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PDF VSC2400-30) OC-48 VSC2400-30UY OC-48 digital pacemaker pacemaker VSC2400-30 VSC2400-30UY
2002 - Not Available

Abstract: No abstract text available
Text: Preliminary Data Sheet April 2002 TAAD08JU21BCLS2-DB SAR -2K AAL2/ AAL5 SAR Engine 1 Features s , Agere Systems Inc. 0.16 µm CMOS technology, the chip implements AAL2 and AAL5 SAR functions. Support for , bidirectional AAL5 VCs via an internal context memory. Communication with SAR -2K is accomplished through three , AAL5 SAR functionality per ITU I.363.5. Provides quality of service (QoS) connection identifier (CID , , power, and function. TAAD08JU21BCLS2-DB SAR -2K AAL2/ AAL5 SAR Engine Table of Contents Contents


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PDF TAAD08JU21BCLS2-DB DS02-128ATM
2003 - Not Available

Abstract: No abstract text available
Text: Preliminary Data Sheet May 9, 2003 TAAD08JU21BCLS2-DB SAR -2K AAL2/ AAL5 SAR Engine, Versions , data or voice traffic per ITU I.363.2. s Provides AAL5 SAR functionality per ITU I.363.5. s , Systems’ 0.16 µm CMOS technology, the chip implements AAL2 and AAL5 SAR functions. s –40 oC , area, power, and function. TAAD08JU21BCLS2-DB SAR -2K AAL2/ AAL5 SAR Engine, Versions 2.1 and 3.1 , / AAL5 SAR Engine, Versions 2.1 and 3.1 Table of Contents (continued) Contents Page 11.4.12


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PDF TAAD08JU21BCLS2-DB DS03-128ATM-3 DS03-128ATM-2)
2003 - Not Available

Abstract: No abstract text available
Text: Preliminary Data Sheet May 9, 2003 TAAD08JU21BCLSU3A-DB AAL2/ AAL5 SAR Engine, Versions 2.1 and , AAL2 and AAL5 SAR functions. Support for AAL2 is provided via an AAL/CPS function that maps/demaps , support of low-speed data or voice traffic per ITU I.363.2. Provides AAL5 SAR functionality per ITU I , area, power, and function. TAAD08JU21BCLSU3A-DB AAL2/ AAL5 SAR Engine, Versions 2.1 and 3.1 Table of , / AAL5 SAR Engine, Versions 2.1 and 3.1 Table of Contents (continued) Contents 11.4.12 11.4.13


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PDF TAAD08JU21BCLSU3A-DB nu-2448, DS03-110ATM
2003 - A9KX

Abstract: TAAD08JU21BCLSL3A-DB
Text: Preliminary Data Sheet May 9, 2003 TAAD08JU21BCLSL3A-DB AAL2/ AAL5 SAR Engine, Versions 2.1 and , AAL2 and AAL5 SAR functions. Support for AAL2 is provided via an AAL/CPS function that maps/demaps , support of low-speed data or voice traffic per ITU I.363.2. Provides AAL5 SAR functionality per ITU I , area, power, and function. TAAD08JU21BCLSL3A-DB AAL2/ AAL5 SAR Engine, Versions 2.1 and 3.1 Table of , / AAL5 SAR Engine, Versions 2.1 and 3.1 Table of Contents (continued) Contents 11.4.12 11.4.13


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PDF TAAD08JU21BCLSL3A-DB n-2448, DS03-109ATM A9KX
2002 - APP550

Abstract: APP550TM APP530TM APP550TM and APP530TM APP550TM and APP530TM traffic manager
Text: . The APP550TM and APP530TM are standalone processors that provide AAL5 SAR and Traffic Management , through the embedded AAL5 segmentation and reassembly ( SAR ) functionality in the APP550TM and APP530TM , you build multiservice applications. These include: I Wire-Rate Bidirectional AAL5 SAR (APP550) AAL5 SAR capabilities are embedded in the APP550TM and APP530TM. This enables the flexible hardware , Product Brief Product Brief May 2003 May 2003 ATM SAR and Traffic Manager Processor


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PDF APP550TM APP530TM APP530TM. APP530TM PB03-138NP APP550 APP550TM and APP530TM APP550TM and APP530TM traffic manager
2000 - pacemaker

Abstract: AAL5 SAR traffic heart rate monitor
Text: providing packet and cell classification, policing, wire speed AAL5 SAR , ATM/ Frame Relay network , unrestricted number of multicast leaves, VC merging, and label swapping. · · · · · AAL5 SAR OC-48 AAL5 SAR supporting 256K sessions · FRF-5 Interworking FRF-5 compliant ATM/Frame Relay network , · Features: Frame Relay/ATM interworking AAL5 SAR Unified Packet and Cell buffer and


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PDF OC-48 OC-48c pacemaker AAL5 SAR traffic heart rate monitor
2003 - M27483

Abstract: AAL5 segmentation
Text: PortMaker®III AAL5 Firmware TSP3 Traffic Stream Processors AAL5 SAR with ATM-to-MPLS , applications for the TSP3 family of devices. The PortMakerIII AAL5 SAR with ATM-to-MPLS interworking , with CBWFQ > ITU I.363.5 compliant AAL5 SAR > ATM-to-MPLS interworking support based on , CBWFQ access · Ingress policing · ITU I.363.5 AAL5 SAR · Congestion control · Auto-VC , applications. > Independent shaping and policing profiles for up to 256K connections AAL5 Segmentation


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PDF OC-48 MXAPM3A5-BRF-001-A M03-0778 M27483 AAL5 segmentation
2003 - AB29

Abstract: AE13 AF29 AG29 MT90500 MT90503 wy28 application note utopia
Text: , which is shown with less detail below. Transmit AAL5 SAR Secondary UTOPIA Primary Transmit , the bus (such as a second MT90500 or an AAL5 SAR ). In this setup it is likely that the PRXEN of the , device via its Primary port. Another device is present on the Primary receive bus, such as an AAL5 SAR , to the output enb of the AAL5 SAR . The MT90500 Primary port is operating in 8-bit ATM mode and the Secondary port is operating in 8-bit PHY mode. Primary Receive AAL5 SAR Secondary UTOPIA Primary


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PDF MSAN-205 MT90500 MT90500 MT90503 AB29 AE13 AF29 AG29 wy28 application note utopia
2002 - AF-VTOA-0113

Abstract: BTS G29 TAAD08JU2 transistor w2d AG10 AH11 AJ11 TAAD08JU21BCLS2-DB 31N40
Text: Preliminary Data Sheet July 2002 TAAD08JU21BCLS2-DB SAR -2K AAL2/ AAL5 SAR Engine 1 Features s , ) function for support of low-speed data or voice traffic per ITU I.363.2. s Provides AAL5 SAR , implements AAL2 and AAL5 SAR functions. Support for AAL2 is provided via an AAL/CPS function that maps , destinations. SAR -2K provides support for up to 2032 bidirectional AAL5 VCs via an internal context memory , function. TAAD08JU21BCLS2-DB SAR -2K AAL2/ AAL5 SAR Engine Preliminary Data Sheet July 2002 Table


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PDF TAAD08JU21BCLS2-DB DS02-128ATM-1 DS02-128ATM) AF-VTOA-0113 BTS G29 TAAD08JU2 transistor w2d AG10 AH11 AJ11 31N40
2004 - Not Available

Abstract: No abstract text available
Text: for implementing Multi service Traffic Management, Switching and ATM SAR for the access market. The Porto-100's novel, high performance, scalable chip architecture with its built in ATM AAL5 SAR can , AAL5 SAR and MPLS Switch § Flexible Congestion and Buffer Management Schemes § TM 4.1 Compliant , transparently between them. The built in line rate AAL5 SAR and OAM processor combined with ATM and MPLS , an integrated, wire-speed SAR engine. FEATURES Introduction 1M Simultaneously Queued and


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PDF CS5331 Porto-100 2xOC12 Porto-100 CS5331, 2xOC-12 F5331001204
2002 - CP12

Abstract: CP14 CP15 CRC-32 MPC750
Text: AAL-5 SAR Application Guide C-WARE SOFTWARE TOOLSET, VERSION 2.3 CSTAA5-UG/D Rev 01 , GUIDE Guide Overview This document describes the design and features of the C-Ware AAL-5 SAR , Documentation Set DOCUMENT NAME PURPOSE DOCUMENT ID AAL-5 Fabric Port SAR to Gigabit Ethernet Switch , AAL-5 SAR Application Guide Describes the key characteristics of the oc3SarQ application. CSTAA5-UG AAL-5 SAR to Gigabit Ethernet Switch Application Guide Describes the key characteristics of


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PDF
2004 - CS533

Abstract: CS5333
Text: -200's novel, high performance, scalable chip architecture with its built in ATM AAL5 SAR can aggregate, switch , integrated, wire-speed SAR engine. FEATURES Introduction 1M Simultaneously Queued and Scheduled Virtual Connections (VCs) § ATM VC/VP Switching, Queuing and Traffic Management § Integrated ATM AAL5 SAR and MPLS , rate AAL5 SAR and OAM processor combined with ATM and MPLS protocol awareness, makes Porto-200 an ideal , CS5333 Porto-200 ­ OC-48 Multi Service Traffic Manager and SAR OVERVIEW The Porto-200 CS5333, a


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PDF CS5333 Porto-200 OC-48 Porto-200 CS5333, F5333001204 CS533
2006 - msan configuration

Abstract: AB29 AE13 AF29 AG29 MT90500 MT90503
Text: , which is shown with less detail below. Transmit AAL5 SAR Secondary UTOPIA Primary Transmit , the bus (such as a second MT90500 or an AAL5 SAR ). In this setup it is likely that the PRXEN of the , device via its Primary port. Another device is present on the Primary receive bus, such as an AAL5 SAR , to the output enb of the AAL5 SAR . The MT90500 Primary port is operating in 8-bit ATM mode and the Secondary port is operating in 8-bit PHY mode. Primary Receive AAL5 SAR Secondary UTOPIA Primary


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PDF MSAN-205 MT90500 MT90500 MT90503 msan configuration AB29 AE13 AF29 AG29
2001 - verilog code design of error detection and data r

Abstract: MXT4400 CX29704 block code error management, verilog
Text: TM A CONEXANT BUSINESS PortMakerI AAL5 Firmware MXT4400 Traffic Stream Processor OC-12 AAL5 SAR PortMakerI firmware provides proven, reliable and fully > K E Y F E AT U R E S , .363.5 SAR , traffic shaping and a rich set of other features. AAL5 Segmentation and Reassembly ( SAR ) The , Forum PICS Proforma for the AAL Type 5 tests. The > ITU I.363.5 compliant AAL5 SAR > ATM Forum TM , bus · ITU I.363.5 AAL5 SAR ­ UBR.2 · Host routing for control packets · OC-12 throughput


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PDF MXT4400 OC-12 OC-12 verilog code design of error detection and data r CX29704 block code error management, verilog
2003 - Not Available

Abstract: No abstract text available
Text: Connections (VCs) • ATM VC/VP Switching, Queuing and Traffic Management • Integrated ATM AAL5 SAR and , novel, high performance, scalable chip architecture with its built in ATM AAL5 SAR can aggregate , in line rate AAL5 SAR and OAM processor combined with ATM and MPLS protocol awareness, makes , Scimitar AZ61100 OC-48 Multi Service Traffic Manager and SAR Product Brief Applications , €¢ Pre-Classified IP Datagram Processing for SAR • Packet and Cell-Based Scheduling and Statistics Traffic


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PDF AZ61100 OC-48 AZ61100
2001 - tms 3631 an

Abstract: ONU block diagram AF-VTOA-0085 PM4354 PM73123 PM73124 PM7329 PM7347 tms 3631
Text: PM4354 COMET-QUAD PM7328 S/UNI-ATLAS1K800 ATM Interworking Function, AAL5 SAR ATM OPTICAL , 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 ATM Interworking Function, AAL5 SAR To , PM73123 AAL1gatorTM-8 8 Link CES/DBCES AAL1 SAR TRANSMIT SECTION · Provides individually , OAM cells as well as any other user-generated cells such as AAL5 cells for ATM signaling , PMC-Sierra, Inc. 2001 PM73123 AAL1gatorTM-8 8 Link CES/DBCES AAL1 SAR · Queues are added by making


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PDF PM73123 PM7328 S/UNI-ATLAS1K800 PMC-1991272 tms 3631 an ONU block diagram AF-VTOA-0085 PM4354 PM73123 PM73124 PM7329 PM7347 tms 3631
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