The Datasheet Archive

Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
SN74AHC125NSRG4 SN74AHC125NSRG4 ECAD Model Texas Instruments Quadruple Bus Buffer Gates With 3-State Outputs 14-SO -40 to 125
SN74F125NSR SN74F125NSR ECAD Model Texas Instruments Quadruple Bus Buffer Gate With 3-State Outputs 14-SO 0 to 70
SN74HC125NSRG4 SN74HC125NSRG4 ECAD Model Texas Instruments Quadruple Bus Buffer Gates With 3-State Outputs 14-SO -40 to 85
SN74LVTH125NSRG4 SN74LVTH125NSRG4 ECAD Model Texas Instruments LVT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, GREEN, PLASTIC, SOP-14
SN74F125NSRG4 SN74F125NSRG4 ECAD Model Texas Instruments Quadruple Bus Buffer Gate With 3-State Outputs 14-SO 0 to 70
SN74ABT125NSR SN74ABT125NSR ECAD Model Texas Instruments Quadruple Bus Buffer Gates With 3-State Outputs 14-SO -40 to 85

A0805T-125nS-B datasheet (1)

Part ECAD Model Manufacturer Description Type PDF
A0805T-125nS-B A0805T-125nS-B ECAD Model RCD Components ACTIVE (DIGITAL) DELAY LINE Original PDF

A0805T-125nS-B Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2005 - Not Available

Abstract: No abstract text available
Text: TO RT RECEIVE ONE WORD (PART B ) NBGT 125ns DTREQ 0ns MIN 2.1µs MAX DTGRT 100ns MAX DTACK 635ns , DATA BUS A DUAL TRANSCEIVER DATA BUS B ENCODER/ DECODER MIL-STD-1553B PROTOCOL AND BIT I/O , Differential input impedance DC to 1MHz, Point B , Figure 2 Differential voltage range Input common mode voltage , CHARACTERISTICS (TRANSMITTER SECTION) Parameter/Conditions Differential output level at Point B , Figure 2 (145 , (DDIP). VCC = 5.5V A. @ VIL = 0.4V B . @ VIH = 2.4V All remaining INPUTS other than in Note 1. VCC = 5.5V


Original
PDF CT2542 CT2543 MIL-STD-1553B BUS-65142 BUS-65144 BUS-65143 BUS-65145 MIL-PRF-38534
1999 - Not Available

Abstract: No abstract text available
Text: Figure 5 ­ Timing Diagram, RT to RT Receive One Word (Part B ) NBGT 125ns DTREQ 0ns MIN 2.1µs MAX , TECHNOLOGY www.aeroflex.com A E RO F LE X LA C ISO 9001 E RT IFIED B S I NC . , DATA BUS B ENCODER/ DECODER MIL-STD-1553B PROTOCOL AND BIT I/O INTERFACE DB0-DB15 A0-A11 ERROR , /Conditions Differential input impedance DC to 1MHz, Point B , Figure 1 Differential voltage range Input , Electrical Characteristics (Transmitter Section) Parameter/Conditions Differential output level at point B


Original
PDF CT2543 MIL-STD-1553B CT2542 BUS-65142 BUS-65144 BUS-65143 BUS-65145 MIL-STD-883
2000 - BUS-65142

Abstract: BUS-65143 BUS-65144 BUS-65145 CT2542 CT2543
Text: One Word (Part B ) 4.5 ± 0.5µs 0 9.5µs ±0.75µs NBGT 125ns 0ns MIN DTREQ 2.1µs MAX , CIRCUIT TECHNOLOGY LE X LA S ISO 9001 E I NC . C F B A E RO www.aeroflex.com , TRANSCEIVER DATA BUS B MIL-STD-1553B I/O A0-A11 ERROR FLAG INTERFACE PROCESSING LOGIC , input impedance DC to 1MHz, Point B , Figure 2 Differential voltage range Threshold , pp Differential output level at point B , Figure 2 (145 ohm load) Rise and Fall times (10% to 90


Original
PDF CT2543 MIL-STD-1553B CT2542 BUS-65142 BUS-65144 CT2543 BUS-65143 BUS-65145 CT2543-FP BUS-65144 BUS-65145
15AX2

Abstract: UR1620C RURP880 RURP840CC
Text: RURD410CCS RURD610CCS 35ns 1,0V 35ns 35ns 1.0V 1.0V 35ns 1,0V B Y W 51100 M UR3010PT RURH1510CC 0.95V 35nst 1.05V 35ns MUR1610CT RURP810CC 0.975V 35ns B Y W 51150 MUR3015PT RURH1515CC 0.95V 35ns+ 1.05 V , RURG1560CC RURG3060CC 60ns 1 5V 60ns 1.5V 60ns 1.5 V RURH3070CC RURG1570CC RURG3070CC 125ns 1.5V 150ns 1.8V 150ns 1.5V RURH3080CC RURG1580CC RURG3080CC 125ns 1.5V 150ns 1.8V 150ns 1.5V RURH3090CC RURG1590CC RURG3090CC 1 8V 150ns 1.5V 125ns 1.5V 150ns RURH30100CC RURG15100CC RURG30100CC 125ns 1.5V 150ns 1.8V 150ns


OCR Scan
PDF O-251AA O-252AA O-220AB O-218AC O-247 15Ax2 30Ax2 RURG3010CC 15AX2 UR1620C RURP880 RURP840CC
1998 - ct2542-701

Abstract: No abstract text available
Text: Plainview NY (516) 694-6700 Figure 5 ­ Timing Diagram, RT to RT Receive One Word (Part B ) NBGT 125ns , SCDCT2542 REV B 3/5/98 Plainview NY (516) 694-6700 Aeroflex Circuit Technology DTSTB 125ns TYP 125ns , Manufacturer. DATA BUS A DUAL TRANSCEIVER DATA BUS B ENCODER/ DECODER MIL-STD-1553B PROTOCOL AND BIT I , Future © SCDCT2542 REV B 3/5/98 Absolute Maximum Ratings Parameter Power Supply Voltage (VEE) (Pins , REV B 3/5/98 Plainview NY (516) 694-6700 Electrical Characteristics (Receiver Section) Parameter


Original
PDF MIL-STD-1553B BUS-65142 BUS-65143 CT2542 CT2542-FP CT2542-701 CT2542-FP-701
BUS-65142

Abstract: BUS-65143 CT2542 5962-8979803YA
Text: One Word (Part B ) 4.5 ± 0.5µs 0 9.5µs ±0.75µs NBGT 125ns 0ns MIN DTREQ 2.1µs MAX , ISO 9001 S C F B A E RO www.aeroflex.com RTIFIED General Description The , TRANSCEIVER DATA BUS B MIL-STD-1553B I/O A0-A11 ERROR FLAG INTERFACE PROCESSING LOGIC , , Point B , Figure 1 Common mode rejection ratio (from point A, Figure 1) Threshold characteristics , Circuit Technology 26 Tr Differential output level at point B , Figure 1 (145 ohm load) Min


Original
PDF MIL-STD-1553B BUS-65142 BUS-65143 CT2542 MIL-STD-883 CT2542 8979803XA 8979803XC CT2542-FP BUS-65143 5962-8979803YA
Not Available

Abstract: No abstract text available
Text: Transfer BITEN I« *- 375 ns 125ns DTSTB 125ns - ! I I« « - - \ TRISTATE 75ns-*j D B , , Data to Subsystem DTREQ 0ns MINDTGRT 100ns MAXDTACK 125ns TYPDTSTB 125ns TYPR/W 50ns MIN-^ D BO -D B , eceiver Section) Parameter/Conditions Differential input impedance DC to 1MHz, Point B , Figure 1 , /Conditions Differential output level at point B , Figure 1 (145 ohm load) Symbol Vo Min 26 Typ , Note 1 For INPUT pins 12,13,14,15, 53, 54, 55. VCC= 5.5V A. @ VIL = 0.4V B . @ VIH = 2.4V Note 2


OCR Scan
PDF -1553B BUS-65142 BUS-65143 5962-8979803XA 5962-8979803XC 5962-8979803YA 5962-8979803YC CT2542 CT2542-FP CT2542-701
2007 - MT29F32G08

Abstract: MT29F8G08MAA MT29F32G08TAA MT29F16G08QAA Micron NAND MT29F32 Micron MT29F8G08 MT29F32G MT29F16G08 MT29F8G08M
Text: 62 126 R/ B # LOW (tCBSY) MLC SLC SLC MLC 3.12 MB/s 25ns 125ns 52.8µs 25ns , : 09005aef82cfa647 tn2925_imp_perf_two_plane_cmds.fm - Rev. B 9/08 EN 1 Micron Technology, Inc., reserves the , tn2925_imp_perf_two_plane_cmds.fm - Rev. B 9/08 EN 2 Micron Technology, Inc., reserves the right to change products or , / Source: 09005aef82cfa647 tn2925_imp_perf_two_plane_cmds.fm - Rev. B 9/08 EN 3 Micron Technology , READ 00h-30h Command latch (00h) Address latch Command latch (30h or 35h) R/ B # LOW (tR) 1 5 1


Original
PDF TN-29-25: MT29F4G08AAA, MT29F8G08BAA, MT29F8G08DAA, MT29F16G08FAA, MT29F8G08MAA, MT29F16G08QAA, MT29F32G08TAA 80h-11h-80h-15h, 09005aef82cfa5d5 MT29F32G08 MT29F8G08MAA MT29F32G08TAA MT29F16G08QAA Micron NAND MT29F32 Micron MT29F8G08 MT29F32G MT29F16G08 MT29F8G08M
2005 - BUS-65142

Abstract: BUS-65143 BUS-65144 BUS-65145 CT2542 CT2543 CT2542-FP-701
Text: /O AND BIT TRANSCEIVER DATA BUS B MIL-STD-1553B ENCODER/ DECODER A0-A11 ERROR FLAG , Differential input impedance DC to 1MHz, Point B , Figure 2 Common mode rejection ratio (from Point A , VNOI - - 10 mVPK-PK Differential output level at Point B , Figure 2 (145-ohm load) Rise , ,15, 53, 54, 55 (DDIP). VCC = 5.5V A. @ VIL = 0.4V B . @ VIH = 2.4V Note 2: All remaining INPUTS other than in Note 1. VCC = 5.5V A. @ VIL = 0.4V B . @ VIH = 2.4V Note 3: For OUTPUT pins


Original
PDF CT2542 CT2543 MIL-STD-1553B BUS-65142 BUS-65144 CT2543 BUS-65143 BUS-65145 MIL-PRF-38534 BUS-65144 BUS-65145 CT2542-FP-701
0909NS

Abstract: GDDR5 10x10mm, LGA, 44 pin 60-LGA 170-FBGA MARKING CL4 FBGA DDR3 x32 170FBGA 60-FBGA POP-SAC105
Text: . Small Classification A : Advanced Dram Technology B : DDR3 SDRAM C : Network-DRAM D : DDR SGRAM E , -400F (Lead-Free) T : TSOP2 Z : FBGA (Lead-Free) - DDR SDRAM 6 : STSOP2 (Halogen-Free, Lead-Free) B : FBGA , : FBGA (Lead-Free) - GDDR3 SDRAM A : 136-FBGA, FBGA B : 136-FBGA, FBGA (Lead-Free) G : FBGA H : 136 , : FBGA, FBGA (Lead-Free) 9 10 11 12 13 14 15 16 17 18 - GDDR4 SDRAM A : 136-FBGA, FBGA B : 136-FBGA, FBGA (Lead-Free) H : 136-FBGA, FBGA (Halogen-Free, Lead-Free) - GDDR5 SDRAM A : 170-FBGA B : 170


Original
PDF 16K/16ms 4K/32ms 8K/64ms 16K/32ms 8K/32ms 2K/16ms 4K/64ms 429ns 667ns 0909NS GDDR5 10x10mm, LGA, 44 pin 60-LGA 170-FBGA MARKING CL4 FBGA DDR3 x32 170FBGA 60-FBGA POP-SAC105
2000 - Not Available

Abstract: No abstract text available
Text: generation - B : 2nd generation Example:KMM383L3223AT 1-3. Modified binning policy From - 0 (100Mhz , delay on write tQCSW Write burst end to QFC delay on write tQCHW 1.25ns 0.5tCK 1.25ns 0.5tCK 1.25ns 0.5tCK Write burst end to QFC delay on write interrupted by Precharge tQCHWI 1.25ns 1.5tCK 1.25ns 1.5tCK 1.25ns 1.5tCK 4.0 4.0 4.0 Revision 0.5 (April , end to QFC delay on write tQCHW 1.25ns 0.5tCK 1.25ns 0.5tCK 1.25ns 0.5tCK 5


Original
PDF M383L3223BT0 184pin 256MB 32Mx72 32Mx8 72-bit 133Mhz)
2000 - Not Available

Abstract: No abstract text available
Text: Blank: 1st generation -A : 2nd generation - B : 2nd generation Example:KMM383L6423AT 1-3. Modified , tCLmin or tCH0.9 0.4 1.1 0.6 4.0 1.1 0.6 4.0 1.1 0.6 4.0 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK Revision 0.5 (April. 2000) 1 , 1.1 0.6 4.0 tCK tCK ns 5 6 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK Note : 1. Maximum burst refresh of 8 2. tHZQ transitions occurs in the


Original
PDF M383L6423BT1 184pin 512MB 64Mx72 32Mx72 32Mx8 72-bit
2000 - PC200

Abstract: No abstract text available
Text: generation - B : 2nd generation Example:KMM383L6420AT 1-3. Modified binning policy From - 0 (100Mhz , delay on write tQCSW Write burst end to QFC delay on write tQCHW 1.25ns 0.5tCK 1.25ns 0.5tCK 1.25ns 0.5tCK Write burst end to QFC delay on write interrupted by Precharge tQCHWI 1.25ns 1.5tCK 1.25ns 1.5tCK 1.25ns 1.5tCK 4.0 4.0 4.0 Revision 0.5 (April , delay on write tQCSW 4.0 ns Write burst end to QFC delay on write tQCHW 1.25ns


Original
PDF M383L6420BT0 184pin 512MB 64Mx72 64Mx4 72-bit 133Mhz) PC200
2000 - Not Available

Abstract: No abstract text available
Text: generation -A : 2nd generation - B : 2nd generation Example:KMM383L3223AT 1-3. Modified binning policy From - , 0.6 4.0 1.1 0.6 4.0 1.1 0.6 4.0 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK Revision 0.5 (April. 2000) 1. Changed from A-die to B-die , 1.1 0.6 4.0 tCK tCK ns 5 6 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK Note : 1. Maximum burst refresh of 8 2. tHZQ transitions occurs in the


Original
PDF M383L3223BT1 184pin 256MB 32Mx72 32Mx8 72-bit 133Mhz)
2000 - PC200

Abstract: No abstract text available
Text: : 2nd generation - B : 2nd generation Example:KMM383L6423AT 1-3. Modified binning policy From - 0 , delay on write tQCSW Write burst end to QFC delay on write tQCHW 1.25ns 0.5tCK 1.25ns 0.5tCK 1.25ns 0.5tCK Write burst end to QFC delay on write interrupted by Precharge tQCHWI 1.25ns 1.5tCK 1.25ns 1.5tCK 1.25ns 1.5tCK 4.0 -2- 4.0 4.0 Rev. 0.4 April , QFC delay on write tQCHW 1.25ns 0.5tCK 1.25ns 0.5tCK 1.25ns 0.5tCK 5 Write


Original
PDF M383L6423AT0 184pin 512MB 64Mx72 32Mx72 32Mx8 72-bit PC200
2000 - PC200

Abstract: No abstract text available
Text: : 2nd generation - B : 2nd generation Example:KMM383L6423AT 1-3. Modified binning policy From - 0 , delay on write tQCSW Write burst end to QFC delay on write tQCHW 1.25ns 0.5tCK 1.25ns 0.5tCK 1.25ns 0.5tCK Write burst end to QFC delay on write interrupted by Precharge tQCHWI 1.25ns 1.5tCK 1.25ns 1.5tCK 1.25ns 1.5tCK 4.0 4.0 4.0 Revision 0.5 (April , delay on write tQCSW 4.0 ns Write burst end to QFC delay on write tQCHW 1.25ns


Original
PDF M383L6423BT0 184pin 512MB 64Mx72 32Mx72 32Mx8 72-bit PC200
2000 - PC200

Abstract: No abstract text available
Text: . PCB Revison From - Blank: 1st generation -A : 2nd generation - B : 2nd generation Example , write tQCHW 1.25ns 0.5tCK 1.25ns 0.5tCK 1.25ns 0.5tCK Write burst end to QFC delay on write interrupted by Precharge tQCHWI 1.25ns 1.5tCK 1.25ns 1.5tCK 1.25ns , delay on write tQCSW 4.0 ns Write burst end to QFC delay on write tQCHW 1.25ns 0.5tCK 1.25ns 0.5tCK 1.25ns 0.5tCK 5 Write burst end to QFC delay on write interrupted


Original
PDF M368L1713BT0 184pin 128MB 16Mx64 16Mx8 64-bit 133Mhz) PC200
2000 - PC200

Abstract: No abstract text available
Text: generation - B : 2nd generation Example:KMM381L3223AT 1-3. Modified binning policy From - 0 (100Mhz , write tQCHW 1.25ns 0.5tCK 1.25ns 0.5tCK 1.25ns 0.5tCK Write burst end to QFC delay on write interrupted by Precharge tQCHWI 1.25ns 1.5tCK 1.25ns 1.5tCK 1.25ns , delay on write tQCSW 4.0 ns Write burst end to QFC delay on write tQCHW 1.25ns 0.5tCK 1.25ns 0.5tCK 1.25ns 0.5tCK 5 Write burst end to QFC delay on write interrupted


Original
PDF M381L3223BT0 184pin 256MB 32Mx72 32Mx8 72-bit 133Mhz) PC200
2000 - Not Available

Abstract: No abstract text available
Text: generation - B : 2nd generation Example:KMM368L914BT 1-3. Modified binning policy From - 0 (100Mhz/200Mbps , by Precharge tQH tHP tQCS tDQCH tQCSW tQCHW tQCHWI 1.25ns 1.25ns tHPmin -0.75ns tCLmin or tCH0.9 0.4 , 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK < Page 12> 15. Changed from 1450mil , 1.1 0.6 4.0 0.9 0.4 1.1 0.6 4.0 0.9 0.4 1.1 0.6 4.0 tCK tCK ns 5 6 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK Note : 1. Maximum


Original
PDF M368L0914BT1 184pin 8Mx64 8Mx16 64-bit 133Mhz) 133Mhz/266Mbps
2000 - Not Available

Abstract: No abstract text available
Text: Blank: 1st generation -A : 2nd generation - B : 2nd generation Example:KMM368L3223AT 1-3. Modified , tQCSW tQCHW tQCHWI 1.25ns 1.25ns tHPmin -0.75ns tCLmin or tCH0.9 0.4 Max -B0(PC266@CL=2.5) Min tHPmin , 1.1 0.6 4.0 0.5tCK 1.5tCK 1.1 0.6 4.0 1.1 0.6 4.0 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK < Page 12> 15. Changed from 1450mil to 1250mil in Package dimension , 1.1 0.6 4.0 0.9 0.4 1.1 0.6 4.0 0.9 0.4 1.1 0.6 4.0 tCK tCK ns 5 6 1.25ns 1.25ns


Original
PDF M368L3223BT1 184pin 256MB 32Mx64 32Mx8 64-bit 133Mhz)
2000 - PC200

Abstract: No abstract text available
Text: - B : 2nd generation Example:KMM381L6423AT 1-3. Modified binning policy From - 0 (100Mhz/200Mbps , write tQCHW 1.25ns 0.5tCK 1.25ns 0.5tCK 1.25ns 0.5tCK Write burst end to QFC delay on write interrupted by Precharge tQCHWI 1.25ns 1.5tCK 1.25ns 1.5tCK 1.25ns , 4.0 ns Write burst end to QFC delay on write tQCHW 1.25ns 0.5tCK 1.25ns 0.5tCK 1.25ns 0.5tCK 5 Write burst end to QFC delay on write interrupted by Precharge tQCHWI


Original
PDF M381L6423BT0 184pin 512MB 64Mx72 32Mx72 32Mx8 72-bit PC200
2000 - Not Available

Abstract: No abstract text available
Text: : 2nd generation - B : 2nd generation Example:KMM383L3313BT 1-3. Modified binning policy From - 0 (100Mhz , 4.0 1.1 0.6 4.0 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK Revision 0.6 (June. 2000) 1. Changed PCB version from T0 to T1. -2- Rev , tCK ns 5 6 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns , degrade accordingly. 5. The value of tQCSW min. is 1.25ns from the last low going data strobe edge to QFC


Original
PDF M383L3313BT1 184pin 256MB 32Mx72 16Mx72 16Mx8 72-bit
2000 - Not Available

Abstract: No abstract text available
Text: generation -A : 2nd generation - B : 2nd generation Example:KMM383L6420AT 1-3. Modified binning policy From - , 0.6 4.0 1.1 0.6 4.0 1.1 0.6 4.0 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK Revision 0.5 (April. 2000) 1. Changed from A-die to B-die , 1.1 0.6 4.0 tCK tCK ns 5 6 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK 1.25ns 1.25ns 0.5tCK 1.5tCK Note : 1. Maximum burst refresh of 8 2. tHZQ transitions occurs in the


Original
PDF M383L6420BT1 184pin 512MB 64Mx72 64Mx4 72-bit 133Mhz)
MUR1520 equivalent

Abstract: MUR850 RURP810 RURD610S RURD610 RURD410 MUR810 MUR1510 MUR880 MUR1550
Text: 125ns 1.8V 150ns 1.8V 150ns 1.9V 200ns 1.9V 200ns 1.9V 200ns 1.9V 200ns RURU150120 1200V , RURG8090 RURU5090 RURU8090 RURP890 1.8V 110ns 1.8V 125ns 1.8V 150ns 1.8V 150ns 1.9V 200ns 1.9V , RURP880 1.8V 110ns 1.8V 125ns 1.8V 150ns 1.8V 150ns 1.9V 200ns 1.9V 200ns 1.9V 200ns 1.9V 200ns , RURG8070 RURU5070 RURU8070 RURP870 1.8V 110ns 1.8V 125ns 1.8V 150ns 1.8V 150ns 1.9V 200ns 1.9V , 30Ax2 15Ax2 RURH1590CC RURH3090CC RURG1590CC 1.8V 125ns 1.8V 150ns 1.5V 125ns RURH1580CC


Original
PDF 5A/80A MUR1550 RURP3050 RURG3050 RURG5050 RURG8050 RURU5050 RURU8050 RURU10050 RURU15050 MUR1520 equivalent MUR850 RURP810 RURD610S RURD610 RURD410 MUR810 MUR1510 MUR880 MUR1550
2000 - PC200

Abstract: No abstract text available
Text: : 2nd generation - B : 2nd generation Example:KMM368L3223AT 1-3. Modified binning policy From - 0 , Write burst end to QFC delay on write tQCHW 1.25ns 0.5tCK 1.25ns 0.5tCK 1.25ns 0.5tCK Write burst end to QFC delay on write interrupted by Precharge tQCHWI 1.25ns 1.5tCK 1.25ns 1.5tCK 1.25ns 1.5tCK 4.0 4.0 4.0 < Page 12> 15. Changed from 1450mil to , delay on write tQCSW 4.0 ns Write burst end to QFC delay on write tQCHW 1.25ns


Original
PDF M368L3223AT0 184pin 256MB 32Mx64 32Mx8 64-bit 133Mhz) PC200
Supplyframe Tracking Pixel