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Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
5962-8515522SA 5962-8515522SA ECAD Model Texas Instruments OT PLD, 10ns, CDFP20, CERAMIC, DFP-20
TIBPAL20R8-10CFN TIBPAL20R8-10CFN ECAD Model Texas Instruments OT PLD, 10ns, PQCC28, PLASTIC, CC-28
SN74V263-15GGM SN74V263-15GGM ECAD Model Texas Instruments 8KX18 OTHER FIFO, 10ns, PBGA100, PLASTIC, BGA-100
SN74V273-15GGM SN74V273-15GGM ECAD Model Texas Instruments 16KX18 OTHER FIFO, 10ns, PBGA100, PLASTIC, BGA-100
SN74V283-15GGM SN74V283-15GGM ECAD Model Texas Instruments 32KX18 OTHER FIFO, 10ns, PBGA100, PLASTIC, BGA-100
SN74V293-15GGM SN74V293-15GGM ECAD Model Texas Instruments 64KX18 OTHER FIFO, 10ns, PBGA100, PLASTIC, BGA-100

A03-10nS-B datasheet (1)

Part ECAD Model Manufacturer Description Type PDF
A03-10nS-B A03-10nS-B ECAD Model RCD Components ACTIVE (DIGITAL) DELAY LINE Original PDF

A03-10nS-B Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2008 - 400KHZ

Abstract: AS3336G SSOP-28
Text: PHASE2 I/O Current Balance Outputs. It is generated by PHASE B and F signal. 14 PHASEF I , topen Test Circuit A PHASE1,2,3,4 C B 33pF 300Ohm PWM1,2,3,4 20 Rev. A.03 AME , . Measured Pass Max 10ns Result 18.36ns Min Waveform CH1 - CH2 PWM1 CH3 PHASE1 CH4 - PHASE2 t op e n Spec. Measured Min 10ns Result 16.48ns Pass Max , Min 10ns Result 18.54ns Pass Max Waveform CH1 - CH2 PWM3 CH3 PHASE3


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PDF AS3336G AS3336 On-Resistanc41 025BASIC 015BASIC ATT-DSAS3336G-A 400KHZ AS3336G SSOP-28
2007 - Not Available

Abstract: No abstract text available
Text: . Height (H) Code ±0.05 ns 7.50 max B ±0.05 ns ±0.10 ns 12.00 max F ±0.25 ns 3.0 Electrical , dB min 0.5 ohm max 1.0 ohm max 0.1~ 1.0ns : 0.8 ohm max 2.0 ohm max 1.1~ 10ns : 0.8 ohm max/1ns , -40°C to +85°C -55°C to +155°C DL1L8 ( B , F) 0.1~2.6 ns (0.1 ns step) 3.0~5.0 ns (0.5 ns step


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PDF ISO9001 ISO14001
2000 - "Digital Delay Lines"

Abstract: RCD Components MIL-D-83532 SA01
Text: Economical cost, prompt delivery! r Wide varieties of values, 10nS to 500nS. r TTL compatible. r Operating , (Also available in SIP package) .015[.38] Min. A01 - 100nS - B .800[20.3] Max. 14 VCC


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PDF MIL-D-23859. 500nS. "Digital Delay Lines" RCD Components MIL-D-83532 SA01
2003 - RCD Components

Abstract: MIL-D-83532 SA01
Text: ACTIVE (DIGITAL) DELAY LINES RESISTORS #CAPS & COILS #DELAY LINES A01 SERIES (SINGLE DELAY) A03 SERIES (TRIPLE DELAY) FEATURES ! Economical cost, prompt delivery! ! Wide range of values, 10nS to 500nS. ! TTL compatible ! Operating temperature: 0°C to 70°C ! Single output SIP delay line now available-consult factory for data sheet on SA01 Series OPTIONS ! Non-standard delay times ! , Time Packaging: B=Bulk A01 - 100nS - B .800[20.3] Max. 8 Output .295[7.5] Max


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PDF 500nS. MIL-D-83532 RCD Components MIL-D-83532 SA01
Not Available

Abstract: No abstract text available
Text: 7 4 B b 3 4 b G 0 Q G 7 b c bl4 ■RCD i ACTIVE (DIGITAL) DELAY LINES SERIES A01 - SINGLE DELAY SERIES A03 - TRIPLE DELAY ■■■■■Economical cost, prompt delivery! Wide varieties of values, 10nS to 500nS TTL compatible Operating temperature: 0 °C to 7 0°C New! Single output SIP delay line now available Consult factory for data sheet on SA01 series. RC D ’s digital delay lines have been designed to provid precise fixed delays with all the necessary drive and pickoff


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PDF 500nS 250nS 100nS
SF1004C

Abstract: SF1006C SF1005C
Text: TIME BASE FOR 50 / 10ns / cm 200 2. Rise Time= 10ns max., Source Impedance= 50 ohms. 100 0


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PDF SF1001C SF1008C O-220AB 2002/95/EC 25Vdc SF1004C SF1006C SF1005C
SFM104FL

Abstract: SFM108FL SMD MARKING E5
Text: 50 / 10ns / cm 20 2. Rise Time= 10ns max., Source Impedance= 50 ohms. 10 0 0 1 10 100


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PDF SFM101FL SFM108FL OD-123F 25Vdc SFM104FL SFM108FL SMD MARKING E5
SF1006FC

Abstract: SF1008FC SF10
Text: . Rise Time= 7ns max., Input Impedance= 1 megohm.22pF. -1.0A 1cm SET TIME BASE FOR 50 / 10ns / cm 200 2. Rise Time= 10ns max., Source Impedance= 50 ohms. 100 0 0 1 10 100 REVERSE VOLTAGE (V


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PDF SF1001FC SF1008FC ITO-220AB 2002/95/EC ITO-220AB MIL-STD-202, 25Vdc SF1006FC SF1008FC SF10
Not Available

Abstract: No abstract text available
Text: the package. 4. 2. 3. 2b S l Sb l O D O E b S b TOT Though the ADS-944's digital , (MSB) B IT 1 (MSB) B IT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 , . 70ns max. 10ns typ. I t INTERNAL S/H COMMAND Hold OUTPUT DATA I I Hold , : 10ns /division Figure 3. Typical ADS-944 Timing Diagram TIMING The ADS-944 is an edge-triggered , output pins. This device actually guarantees that digital output data will be valid for 10ns prior to


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PDF 14-Bit 14-Bit 32-pin ADS-944 14-bit, -77dB 8B0-444 2b515bl 0D02bbl
Not Available

Abstract: No abstract text available
Text: Propagation Delay. 14.5ns (Max), 10ns (Typ) AE AM B 04 B 02 ^ AI4 [ 8 B01 , . >300K RAD (Si) Single Event Upset (SEU) Immunity: <1 x 10'10 Errors/Bit/Day AM [2 B 04 [3 AI2 Q B 03 [5 AI3 Q OY p ) SEU LET Threshold. >100


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PDF ACTS244MS MIL-STD-1835 CDIP2-T20, MIL-PRF-38535 ACTS244MS 125kA
Not Available

Abstract: No abstract text available
Text: range. <> Typical +5V and -5.2V current drain breakdowns are as follows: B +5VAnalog +5Vojgital = , SUPPLY ADS-945 ANALOG INPUT b -1 a a a +10V REFERENCE O U T - w •c JI Ui — i , conversion. 1 50ns typ. 10ns typ. Hold | Acquisition Tim e 40ns typ. 2 . A start convert pulse , : I 55ns typ. i 1 D ATA N-1 VALID 10ns typ. i DATA N VALID ? DATA N+1 VALID 1 4. 90ns typ. • 10ns typ. Scale: 10ns /division I Invalid Data For a sam pling rate


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PDF ADS-945 14-Bit, 10MHz 14-Bit 10MHz ADS-945 S-945 S-945E
ADS-944

Abstract: ADS-944MC ADS-944MM ADS-B944 SG10
Text: multiple start convert pulses to bring valid digital data to its output pins. Approximately 10ns after the , for 10ns prior to the falling edge of EOC. Therefore, EOC can be used to latch data into external , additional information. © START CONVERT - INTERNAL S/H N - 80ns typ.- N+1 - 10ns typ. -115ns typ , max.- Hold ■60ns typ., ± 10ns 50ns typ., 60ns max." DATA (N-1) VALID INVALID DATA 140ns min., 150ns typ. DATA N VALID Note: Scale is approximately 10ns per division. © START CONVERT pulse width


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PDF 14-bit 32-pin, MIL-STD-883 ADS-944 14-bit, -77dB 32-pin complete2857 ADS-944MC ADS-944MM ADS-B944 SG10
2002 - Not Available

Abstract: No abstract text available
Text: OE A0 I/O0 BHE I/O1 6 A1 A2 NC A A3 A4 CE I/O8 B I/O 2 , : 38-05134 Rev. *C Page 4 of 12 CY7C1041CV33 AC Test Loads and Waveforms[10] 8-, 10-ns Devices , ENVIRONMENT R 317Ω 3.3V OUTPUT 30 pF* OUTPUT R2 351Ω 30 pF 1.5V ( b ) (a , characteristics (except High-Z) for all 8-ns and 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown in Figure ( b ). High-Z characteristics


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PDF CY7C1041CV33 I/O15) CY7C1041BV33 CY7C1041CV33 CY7C1042CV33
2005 - Not Available

Abstract: No abstract text available
Text: ) 10nS (0.5 to 25MHz) 5nS (25.1 to 70MHz) 4nS (70.1 to 120MHz) 10nS (0.5 to 20 MHz) 5nS (20.1 to 70


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PDF 120MHz 100MHz 100ppm 25MHz) 70MHz) 100MHz) 120MHz)
Digital Delay Lines

Abstract: No abstract text available
Text: ACTIVE (DIGITAL) DELAY LINES SERIES A01 - SINGLE DELAY SERIES A03 - TRIPLE DELAY Economical cost, prompt delivery! Wide varieties of values, 10nS to 500nS TTL compatible Operating temperature: 0 °C to 70°C New! Single output SIP delay line now available Consult factory for data sheet on SA01 series. Non-standard delay times ECL and High Speed CM OS available Increased operating temperature range Tighter tolerances, faster rise times Trailing edge measurement Low power design Military screening per M


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PDF 500nS IL-D-83532 100nS Digital Delay Lines
Not Available

Abstract: No abstract text available
Text: codes. The dynamic performance of the ADS-944 has been optimized to achieve a THD of -7 7 d B and a SNR , BIT 14 (LSB) 31 B IT 7 23 B IT 8 22 B IT 9 B IT 10 C IR C U IT (§> FLASH A 2 C IR C U IT B IT 11 19 B IT 12 18 OFFSET 5 20 p/ ADC O FFSET A D JU S T B IT 6 21 7 B IT 5 24 G A IN G A IN A D J U S T B IT 4 25 1 B IT 3 26 ADC B IT 2 28 A FLASH B IT 1 (M S B ) 29 3 B T H (M S B ) 30


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PDF ADS-944 14-Bit, 14-bit 32-pin, MIL-STD-883 ADS-944 o4334-0
2003 - Not Available

Abstract: No abstract text available
Text: ) 10nS (0.5 to 25MHz) 5nS (25.1 to 70MHz) 4nS (70.1 to 120MHz) 10nS (0.5 to 20 MHz) 5nS (20.1 to 70


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PDF 120MHz 100MHz 100ppm 25MHz) 70MHz) 100MHz) 120MHz)
Digital Delay Lines

Abstract: No abstract text available
Text: ACTIVE (DIGITAL) DELAY LINES SERIES A01 - SINGLE DELAY SERIES A03 - TRIPLE DELAY Economical cost, prompt delivery! Wide varieties of values, 10nS to 500nS TTL compatible Operating temperature: 0 °C to 70°C New! Single output SIP delay line now available Consult factory for data sheet on SA01 series. Non-standard delay times ECL and High Speed C M O S available Increased operating temperature range Tighter tolerances, faster rise times Trailing edge measurement Low power design Military


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PDF 500nS IL-D-83532 100nS Digital Delay Lines
2014 - Not Available

Abstract: No abstract text available
Text: satisfaction, that: a.) the risk of injury or damage has been minimized; b .) the user assume all such risks , IS62/65WV20488EBLL PIN CONFIGURATION (2M x 8 Low Power) 48-pin mini BGA ( B ) (6mm x 8mm) PIN , (min) = -1.0V AC (pulse width < 10ns ). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns , V V V V V V V V µA µA Notes: 1. VILL(min) = -2.0V AC (pulse width < 10ns ). Not 100% tested. VIHH (max) = VDD + 2.0V AC (pulse width < 10ns ). Not 100% tested. Integrated Silicon Solution


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PDF IS62/65WV20488EALL IS62/65WV20488EBLL 62/65WV20488EALL) 62/65WV20488EBLL) -40oC 125oC) IS62WV20488EALL/BLL IS65WV20488EALL/BLL IS62WV20488EBLL-45BI
2014 - Not Available

Abstract: No abstract text available
Text: satisfaction, that: a.) the risk of injury or damage has been minimized; b .) the user assume all such risks , IS62/65WV20488EBLL PIN CONFIGURATION (2M x 8 Low Power) 48-pin mini BGA ( B ) (6mm x 8mm) PIN , 0.2 0.4 1 1 Unit V V V V µA µA Notes: 1. VILL(min) = -1.0V AC (pulse width < 10ns ). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns ). Not 100% tested. IS62(5 , . VILL(min) = -2.0V AC (pulse width < 10ns ). Not 100% tested. VIHH (max) = VDD + 2.0V AC (pulse width


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PDF IS62/65WV20488EALL IS62/65WV20488EBLL 62/65WV20488EALL) 62/65WV20488EBLL) -40oC 125oC) IS62WV20488EALL/BLL IS65WV20488EALL/BLL IS62WV20488EBLL-45BI
Not Available

Abstract: No abstract text available
Text: ACTIVE (DIGITAL) DELAY LINES R ESSTO RS *CM>S&COILS -DELAY LINES A01 SERIES (SINGLE DELAY) A03 SERIES (TRIPLE DELAY) FEATURES □ □ □ □ □ Economical cost, prompt delivery! Wide range of values, 10nS to 500nS. TTL compatible Operating temperature: 0°C to 70°C Single output SIP delay line now available-consult factory for data sheet on SA01 Series OPTIONS □ □ □ □ □ □ □ Non-standard delay times ECL and high speed CMOS available Increased


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PDF 500nS. MIL-D-83532 250nS 100nS
2013 - Not Available

Abstract: No abstract text available
Text: satisfaction, that: a.) the risk of injury or damage has been minimized; b .) the user assume all such risks , /65WV20488EALL IS62/65WV20488EBLL PIN CONFIGURATION (2M x 8 Low Power) 48-pin mini BGA ( B ) (6mm x 8mm) PIN , 0.2 0.4 1 1 Unit V V V V µA µA Notes: 1. VILL(min) = -1.0V AC (pulse width < 10ns ). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns ). Not 100% tested. IS62(5 , . VILL(min) = -2.0V AC (pulse width < 10ns ). Not 100% tested. VIHH (max) = VDD + 2.0V AC (pulse width


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PDF IS62/65WV20488EALL IS62/65WV20488EBLL 62/65WV20488EALL) 62/65WV20488EBLL) -40oC 125oC) IS62WV20488EALL/BLL IS65WV20488EALL/BLL IS62WV20488EBLL-45BI
2014 - Not Available

Abstract: No abstract text available
Text: satisfaction, that: a.) the risk of injury or damage has been minimized; b .) the user assume all such risks , IS62/65WV20488EBLL PIN CONFIGURATION (2M x 8 Low Power) 48-pin mini BGA ( B ) (6mm x 8mm) PIN , 0.2 0.4 1 1 Unit V V V V µA µA Notes: 1. VILL(min) = -1.0V AC (pulse width < 10ns ). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns ). Not 100% tested. IS62(5 , . VILL(min) = -2.0V AC (pulse width < 10ns ). Not 100% tested. VIHH (max) = VDD + 2.0V AC (pulse width


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PDF IS62/65WV20488EALL IS62/65WV20488EBLL 62/65WV20488EALL) 62/65WV20488EBLL) -40oC 125oC) IS62WV20488EALL/BLL IS65WV20488EALL/BLL IS62WV20488EBLL-45BI
2014 - Not Available

Abstract: No abstract text available
Text: written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b , -pin mini BGA ( B ) (6mm x 8mm) PIN DESCRIPTIONS A0-A20 Address Inputs Chip Enable 1 Input CS2 , Unit V V V V µA µA Notes: 1. VILL(min) = -1.0V AC (pulse width < 10ns ). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns ). Not 100% tested. IS62(5)WV20488EBLL DC ELECTRICAL , -2.0V AC (pulse width < 10ns ). Not 100% tested. VIHH (max) = VDD + 2.0V AC (pulse width < 10ns ). Not


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PDF IS62/65WV20488EALL IS62/65WV20488EBLL 62/65WV20488EALL) 62/65WV20488EBLL) IS62WV20488EALL/BLL IS65WV20488EALL/BLL IS62WV20488EBLL-45BI IS62WV20488EBLL-45BLI IS62WV20488EBLL-55BI IS62WV20488EBLL-55BLI
2014 - IS61WV1288EEBLL

Abstract: No abstract text available
Text: .) the risk of injury or damage has been minimized; b .) the user assume all such risks; and c , Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. B 03/12/2014 IS61/64WV1288EEBLL PIN , 48-mini BGA ( B ) (6 mm x 8 mm) 1 2 3 4 5 6 A NC OE A2 A6 A7 NC B I/O0 NC A1 A5 CE I/O7 C I/O1 NC A0 A4 NC I/O6 D GND , Integrated Silicon Solution, Inc. — www.issi.com Rev. B 03/12/2014 IS61/64WV1288EEBLL ABSOLUTE


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PDF IS61WV1288EEBLL IS64WV1288EEBLL IS61/64WV1288EEBLL 576-bit MS-027. IS61/64WV1288EEBLL MO-207 IS61WV1288EEBLL
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