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BQ4011MA-100 BQ4011MA-100 ECAD Model Texas Instruments 32KX8 NON-VOLATILE SRAM MODULE, 100ns, PDIP28

A03-100nS-B datasheet (1)

Part ECAD Model Manufacturer Description Type PDF
A03-100nS-B A03-100nS-B ECAD Model RCD Components ACTIVE (DIGITAL) DELAY LINE Original PDF

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ktk mentor

Abstract: na2a3 tfk bb 204 UT43 Tfk 680 "CMOS GATE ARRAY" rohm tfk U 264 GD02 BU1202 stk 4211
Text: , 40 28, 40 28, 40 SIP 10 c M 0 , S • f 1 h y -f B U 1 2 0 0 / B U 1 2 0 0 L y V I , / t—•> a > P-À BU1200 tf— )AfflP (74HC/LS/400Û B ) it-ÎK3 i&4 BU1200/BU1200L -bfty-Cfy U , 4» -f 5 > jt&ft Stgli, m^J-b^i K-7-r 5 ti 6 7? 10ns (0U) 0 (4) f*3gg-trJK7)^Se^Ai) B , 'ib-f Vdd&3^ B , riWlfflfff rigi"mi'!-'iir ÌTTìTI ttlTMITl 4QE ]) B VfiaûW 0004101 7 CMOS y- KTU-f/CMOS Gate Arrays IRHM , €” 100ns T'to bkif-oX 1 - h Ii 100ns UT < tcà ^o li, 8000 XT'-y 7iX'äimX't (v 9 Ù 7 Jl>it L £ 8000


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PDF BU1200/BU1200L BU1200 BU1200/BU1200L BU1205/BU1205L BU1202/ BU1202L SIM38, liDIP16ping) ktk mentor na2a3 tfk bb 204 UT43 Tfk 680 "CMOS GATE ARRAY" rohm tfk U 264 GD02 BU1202 stk 4211
2000 - "Digital Delay Lines"

Abstract: RCD Components MIL-D-83532 SA01
Text: (Also available in SIP package) .015[.38] Min. A01 - 100nS - B .800[20.3] Max. 14 VCC


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PDF MIL-D-23859. 500nS. "Digital Delay Lines" RCD Components MIL-D-83532 SA01
2003 - RCD Components

Abstract: MIL-D-83532 SA01
Text: Time Packaging: B=Bulk A01 - 100nS - B .800[20.3] Max. 8 Output .295[7.5] Max


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PDF 500nS. MIL-D-83532 RCD Components MIL-D-83532 SA01
2013 - Not Available

Abstract: No abstract text available
Text: 3.3V CMOS Oscillator GXO-7531 Specifications Product Parameters GXO-7531 0.50 ~ 200MHz ï®ï€ Â±100ppm ±50ppm ±25ppm ±20ppm ï®ï€ ï°   B A D Operating , connected) Standard tristate, no power saving (E/D times 100ns / 100ns ) Power-saving, standby current 10μA (E/D times 10ms / 100ns )   N  ï€ P  Standard.  Optional - , DC A B C D E F G H J K L M Y 1 2 3 4 5 6 7 8 9 0 M Jan Feb Mar Apr May Jun


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PDF GXO-7531 200MHz 100ppm 50ppm 25ppm 20ppm
2011 - Not Available

Abstract: No abstract text available
Text: 5V CMOS Oscillator GXO-7551 Specifications Product Parameters GXO-7551 Option Codes Frequency range: 0.50 ~ 107MHz Frequency stability: ࡯ ˿ ˿ ˿ B A D ࡯ ˿ I Storage temperature range: -55 to +125°C 5.20 (max) ±100ppm ±50ppm ±25ppm  , 100ns / 100ns ) Power-saving, standby current 10µA (E/D times 10ms / 100ns ) Ceramic package with , FREQUENCY • PARTNO DC A B C D E F G H J K L M Y 1 2 3 4 5 6 7 8 9 0 M Jan Feb Mar


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PDF GXO-7551 107MHz 100ppm 50ppm 25ppm 20ppm 107MHz)
2013 - Not Available

Abstract: No abstract text available
Text: 5V CMOS Oscillator GXO-7551 Specifications Product Parameters GXO-7551 Option Codes 0.50 ~ 107MHz ï®ï€ Â±100ppm ±50ppm ±25ppm ±20ppm ï®ï€ ï°   B A , 1 not connected) Standard tristate, no power saving (E/D times 100ns / 100ns ) Power-saving, standby current 10μA (E/D times 10ms / 100ns )   N  ï€ P  Standard. ï , DC A B C D E F G H J K L M Y 1 2 3 4 5 6 7 8 9 0 M Jan Feb Mar Apr May Jun


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PDF GXO-7551 107MHz 100ppm 50ppm 25ppm 20ppm
2015 - Not Available

Abstract: No abstract text available
Text: ° B A D Operating temperature range: -10 to +70°C -40 to +85°C ï®ï€ ï°ï€ I , 1 not connected) Standard tristate, no power saving (E/D times 100ns / 100ns ) Power-saving, standby current 10μA (E/D times 10ms / 100ns )   N  ï€ P  Standard. ï , €ˆ= Date code in YM, eg “EC” = Mar 2015 GOLLEDGE FREQUENCY  PARTNO DC A B C D E F G H


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PDF GXO-7551 2011/65/EU 107MHz 100ppm 50ppm 25ppm 20ppm
2011 - S 7531

Abstract: No abstract text available
Text: 3.3V CMOS Oscillator GXO-7531 Specifications Product Parameters GXO-7531 Option Codes Frequency range: 0.50 ~ 200MHz Frequency stability: ࡯ Ë¿ Ë¿ Ë¿ B A D ࡯ Ë , function: None (pad 1 not connected) Standard tristate, no power saving (E/D times 100ns / 100ns ) Power-saving, standby current 10µA (E/D times 10ms / 100ns ) Enable / disable tristate function Power , 2003 GOLLEDGE FREQUENCY • PARTNO DC A B C D E F G H J K L M Y 1 2 3 4 5 6 7 8


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PDF GXO-7531 200MHz 100ppm 50ppm 25ppm 20ppm 125MHz) 165MHz) S 7531
2015 - Not Available

Abstract: No abstract text available
Text: 3.3V CMOS Oscillator GXO-7531 Specifications Product Parameters GXO-7531 0.50 ~ 200MHz ï®ï€ Â±100ppm ±50ppm ±25ppm ±20ppm ï®ï€ ï°   B A D Operating , connected) Standard tristate, no power saving (E/D times 100ns / 100ns ) Power-saving, standby current 10μA (E/D times 10ms / 100ns )   N  ï€ P  Standard.  Optional - , €ˆ= Date code in YM, eg “EC” = Mar 2015 GOLLEDGE FREQUENCY  PARTNO DC A B C D E F G H


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PDF GXO-7531 200MHz 100ppm 50ppm 25ppm 20ppm
Not Available

Abstract: No abstract text available
Text: 7 4 B b 3 4 b G 0 Q G 7 b c bl4 ■RCD i ACTIVE (DIGITAL) DELAY LINES SERIES A01 - SINGLE DELAY SERIES A03 - TRIPLE DELAY ■■■■■Economical cost, prompt delivery! Wide varieties of values, 10nS to 500nS TTL compatible Operating temperature: 0 °C to 7 0°C New! Single output SIP delay line now available Consult factory for data sheet on SA01 series. RC D ’s digital , @25°C HOW TO ORDER A01 RCD Type (A01, A01 S, A03) Delay Time - 100nS 1


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PDF 500nS 250nS 100nS
3BZ61

Abstract: ISR154-400 1SR150 1SR149 1SR139-400 1SR139-200 1SR139-100 1SR139 1SR133-600 3BZ6
Text: 1 40 1.1 1 10 600 19E 1SR149 HÄ 100 3 60L 70 1503 1. 3 3 25L 10 100 25L trr< 100ns 114C , 2NU41 MS 1000 2 70 3 3 100 1000 trr< 100ns . Ioli7' 89J 3BH41 ms 100 3 140 1. 2 3 10 100 , 100 200 trr<35ns. Io«7" 89J 3DU41 MS 200 3 30a 80 1. 5 3 300 200 trr< 100ns . Io«7' 89J


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PDF 1SR133-600 1S8133-600R lSR133-600 1SR139-100 1SR139-200 1SR139-400 1SR139â 1SR149 100ns 1SR150 3BZ61 ISR154-400 1SR139 1SR133-600 3BZ6
MS 600 35

Abstract: 3JH61 3GZ41 3GU41 3GH61 3GH45 6CC13 5KF20 1S2584 3TH62
Text: ms 400 3 30a 80 25 j 1. 5 3 300 400 trr< 100ns , Ioli;' 'JyHS3?SB# 89J 3GZ41 400 3 45a , 600 3 50 25] 2 3 100 600 trr< 100ns , Ioli ;' 'JyHfi3ISB# 89J 3JZ41 ms 600 3 45a 180 25] 1 , < 100ns 253 5JUZ47 ms 600 5 11 Oc 50 25j 1. 5 5 100 600 trr< 100ns 253 5KF10 bw/9- 110 100 5 , -310- 13249 12MAX iE ií i ft El 250 5.31-5. 4.53-4.950 2.54(1 té-i* a b c 1 38.1 min 19.0 min


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PDF 3GH45 200ns. 3GH61 3GU41 100ns, 3GZ41 3gz61 1S2584Ã 3jc12 50X50Xl. MS 600 35 3JH61 3GZ41 6CC13 5KF20 1S2584 3TH62
2006 - "Digital Delay Lines"

Abstract: "digital delay" 14 RCD Components "Delay Lines" delay line 100ns 100NS A01A 03a a03 03s 8pin
Text: SIDE SIDE VIEW STANDARD DELAY TIMES RCD A04AG 100NS 1 A 01S Single 8P B A 01A G Single 14S M A CIRCUIT SCHEMATICS A01SAG Single 8S M B A 02A Dual , ) P/N DESIGNATION: A01A - 100NS - B W Type: A01, A01S, A01AG, etc. Options: T, H, F, C, A, 39 , , 10nS, 15nS, 20nS, 25nS, 50nS, 75nS, 100nS , 250nS, 500nS Intermediate values available on special , 02A G 8 (OUT) 8 (OUT) 8 (VCC) 7 (OUT) 5 (OUT) C A 02S A Circuit B Circuit A 14


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PDF A03SAG 500nS 100NS A01AG, FA077 GF-061. "Digital Delay Lines" "digital delay" 14 RCD Components "Delay Lines" delay line 100ns A01A 03a a03 03s 8pin
2005 - Digital Delay Lines

Abstract: 03a a03 A03AG 03s 8pin SM DELAY LINES
Text: (leave blank if either is acceptable) - 100nS - B W RCD Components Inc., 520 E. Industrial Park Dr , 100NS Economical cost, prompt delivery! Wide range of values, 5nS to 500nS TTL schottky interfaced , . 25nS, 50nS, 75nS, 100nS , 250nS, 500nS Intermediate values available on special order. SIDE , g e Style 14P 8P 14S M 8S M 14P 8P 14S M 8S M 14P 8P 14S M 8S M 14P 14S M Circuit A B A B C D C D E , SCHEMATICS Circuit A 14 (VCC) 8 (OUT) Circuit B 8 (VCC) 5 (OUT) Circuit C 14 (VCC) 12 (OUT) 8 (OUT


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PDF A03AG A04AG 100NS 500nS MIL-D-23859. A01AG, 100nS FA077 GF-061. Digital Delay Lines 03a a03 03s 8pin SM DELAY LINES
2006 - digital delay lines

Abstract: No abstract text available
Text: = Lead-free, Q= Tin/Lead (leave blank if either is acceptable) - 100nS - B W RCD Components Inc, 520 , A04AG 100NS Economical cost, prompt delivery! Wide range of values, 5nS to 500nS TTL schottky , , 20nS. 25nS, 50nS, 75nS, 100nS , 250nS, 500nS Intermediate values available on special order , Circuit A B A B C D C D E F E F G G PACKAGE STYLE 14P (14-Pin DIP) PACKAGE STYLE 14SM (14-Pin SM DIP) CIRCUIT SCHEMATICS Circuit A 14 (VCC) 8 (OUT) Circuit B 8 (VCC) 5 (OUT) Circuit C 14 (VCC) 12


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PDF A03AG A04AG 100NS 500nS MIL-D-23859. A01AG, 100nS FA077 GF-061. digital delay lines
Not Available

Abstract: No abstract text available
Text: ELPAQ EMS256K8C 70 - 100ns A d ivisio n o f E L M O Sem iconductor Corp. 2Mb CMOS STATIC , – Organized as 262,144 x B AI« £ t 91 2 A1S At4 C » *0 3 A17 ■Access time 70 - 100ns a Low power consumption A t* C 4 » 3 W CE CNpEnabte A7 C 1 It , EMS256K8C 70 A d lv ftio n o f E L M O Sem iconductor Gog». - 100ns BLOCK DIAGRAM vcc T , EMS256K8C 70 A d ivisio n o f E L M O Sem iconductor Corp. ABSOLUTE MAXIMUM RATINGS 100ns


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PDF EMS256K8C 100ns 200mW 100ns
Digital Delay Lines

Abstract: No abstract text available
Text: A01 100nS Input test pulse voltage: 3.2V Input pulse width: 3x the total delay Input rise time


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PDF 500nS IL-D-83532 100nS Digital Delay Lines
Digital Delay Lines

Abstract: No abstract text available
Text: , A01 S, A03) Delay Time - : =r A01 100nS Input test pulse voltage


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PDF 500nS IL-D-83532 100nS Digital Delay Lines
1997 - 8051XA

Abstract: PSD3xx PSD311 8051XA-G3 A11-A3 psd4xx DWA 045
Text: Register Mapping CPU Register Offset Actual PSD Address 2 (Port A Pin Register) 3 (Port B Pin Register) 4 (Port A Direction Register) 5 (Port B Direction Register) 6 (Port A Data Register) 7 (Port B Data Register) 0x20 0x30 0x40 0x50 0x60 0x70 Table 3 indicates that to access the Port , alone, the other address lines A14-A12 may be used in the mux control equations. Appendix B is a , 1-338 5V 5V Ch2 100ns 5V M 100ns Ch2 1.9V PSD3XX ­ Application Note 045 RAM


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PDF PSD311 8051XA 8051XA-G3 16-bit 8051XA 8051XA. p14-p17 p35-p30 PSD3xx A11-A3 psd4xx DWA 045
Not Available

Abstract: No abstract text available
Text: -Packaging: B=Bulk- A01 - 100nS - TEST CONDITIONS @25°C 1. 2. 3. 4. 5. 6. ) Input


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PDF 500nS. MIL-D-83532 250nS 100nS
Not Available

Abstract: No abstract text available
Text: BIT 10 22 +12 V /+15V S U PP LY 4 BIT 9 21 + 10 V R E F E R E N C E O U T 5 B IT 8 20 ANALOG IN P U T 6 B IT 7 19 GROUND 7 B IT 6 18 NO CONNECT 8 B IT 5 17 NO CONNECT 9 B IT 4 16 S TA R T C O N V E R T 10 BIT 3 15 EO , SUPPLY NO CONNECT Fig u re 1. A D S -C C D 1201 Fun ctional B lock Diagram 2 b 5 1 S b l , this time. © Effective bits is equal to: (SNH + Distortion) - i. 7 b + -6.02 Contact


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PDF ADS-CCD1201 12-Bit, 4096-to-1 24-pin ADS-CCD1201 u515bl 0DG3513
Not Available

Abstract: No abstract text available
Text: REFERENCE OUT 12 B IT 1 (M S B ) 11 B IT 2 10 B IT 3 9 B IT 4 C O B IT 5 7 B IT 6 AN ALO G , 0 6 B IT 7 IN P U T 5 B IT 8 4 B IT 9 3 B IT 10 2 B IT 11 B IT 12 CONVERT , . 3. A 100ns wide start convert pulse is used for all production testing. TECHNICAL NOTES 3. When , 0000 0000 0000 0001 0000 B IT 1 (MSB) B IT 2 10 UNIPOLAR SCALE +9.9976 +7.5000 +5.0000 +2.5000 +0.0024 0 -1 2 V /-1 5 V Q Coding is straight binary; 1 LSB = 2.44m V B IT


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PDF 12-Bit, 4096-to-1 400pV 24-pin DS-0274B
CTC 1351

Abstract: CTC+1351+transistor+pin+detail
Text: , 0 to +10 ±2.5, ±5, ±10 2.5 5 10 V V k fl -2 0 100ns I 1 1 ka 5.5 +0.8 , POWER SUPPLY SENSITIVITY 11.4V < ± V CC< 16.5V +4.5V £ ±V0D < +5.5V DRIFT Total Accuracy, B ip o , pulse width of greater than 100ns ; however, it must be limited to 20ps (max) to assure the specified , meet its published specifications. B U R R - B R O W N ® 2.20 Burr-Brown IC Data Book—Mixed , . Timing Diagram (nominal values at +25°C with internal clock). B U R R - BROW N® 1 —1 * -* 1â


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PDF ADC80MAH-12 12-Bit 12-BIT ADC80MAH-t 17313L5 CTC 1351 CTC+1351+transistor+pin+detail
D4LA20

Abstract: D8L60 D6K40R D6K40 D6K20RH D6K20R D6K20H D6K20 D5L60 6602m
Text: 25c trr< 100ns 798 D6K20R STSTC 250 200 6 122c 120 25 j 1. 2 6 25c 10 200 25c trr<300ns 798 D6K20RH §rS7C 250 200 6 122c 120 25 j 1. 2 6 25c 10 200 25c trr< 100ns 798 D6K40 STSTC 450 400 6 , 50a 30 1.4 0. 5 10 200 19D DFAOSE B # 400 0. 5 50a 30 1. 4 0. 5 10 400 19D DFA050 =n 600 0. 5 50a 30 1. 4 0. 5 10 600 trr<300ns. loHJUrStSKÄSi 19D DFA08C B & 200 0.8 25 1. 2 0. 8 10 200 485B DFA08E B & 400 0.8 25 1. 2 0. 8 10 400 trr<300ns, loliTKtX® Âïi 485B DFB05B


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PDF D4LA20 D5L60 D6K20 300ns D6K20H 100ns D6K20R 300ns D6K20RH D8L60 D6K40R D6K40 D6K20RH D5L60 6602m
2004 - Not Available

Abstract: No abstract text available
Text: FUNCTIONAL BLOCK DIAGRAM VDD A CS SDI 3-WIRE INTERFACE W CLK WIPER REGISTER B 04749-0-001 , calibration VCXO adjustment PIN CONFIGURATION 8 AD5165 B TOP VIEW GND 3 (Not to Scale) 6 CS 5 , VWZSE RESISTOR TERMINALS Voltage Range5 VA, B ,W Capacitance6 A, B CA, B Capacitance6 W Common-Mode , voltage output D/A converter. VA = VDD and VB = 0 V. 5 Resistor terminals A, B , and W have no , (RWB ≤ 1 kΩ, A open)2 IWA Continuous (RWA ≤ 1 kΩ, B open)2 Digital Inputs and Output Voltage


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PDF 256-Position, AD5165 256-position AD5160 adju22 MO-193BA OT-23] AD5165BUJZ100-R21 AD5165BUJZ100-R71 AD5165EVAL
Supplyframe Tracking Pixel