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Top Results (3)

Part Manufacturer Description Datasheet Download Buy Part
HEX41-AB-00-25-A17-1 (A21310-000) TE Connectivity Ltd HexaShield Adapters and Ferrule Kits; HEX41-AB-00-25-A17-1 ( Raychem )
HEX40L-AC-00-25-A17-3 (379294-000) TE Connectivity Ltd HexaShield Adapters and Ferrule Kits; HEX40L-AC-00-25-A17-3 ( Raychem )
HEX40L-AC-90-25-A17-3 (141988-000) TE Connectivity Ltd HexaShield Adapters and Ferrule Kits; HEX40L-AC-90-25-A17-3 ( Raychem )

A0-A17 Datasheets Context Search

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A0-A17

Abstract: edge connector 64 pin a1657 30 pin simm memory transistor CS4 SL832256K1F-12AG 28-pin SOJ SRAM
Text: Pin Function A0-A17 Address Inputs DQ0-DQ31 Data Inputs/Outputs WE Write Enable , FUNCTIONAL BLOCK DIAGRAM DQ0-3 DQ0 DQ1 CS DQ2 OE WE A0-A17 DQ3 CS1 DQ4-7 DQ0 DQ1 CS DQ2 OE WE A0-A17 DQ3 DQ8-11 DQ0 DQ1 CS DQ2 OE WEA0-A17 DQ3 CS2 DQ12-15 DQ0 DQ1 CS DQ2 OE WE A0-A17 DQ3 DQ16-19 DQ0 DQ1 CS DQ2 OE WE A0-A17 DQ3 CS3 DQ20-23 DQ0 DQ1 CS DQ2 OE WE A0-A17 DQ3 DQ24-27 DQ0 DQ1 CS DQ2 OE WEA0-A17 DQ3 CS4 DQ28-31 DQ0 DQ1 CS DQ2 OE WEA0-A17


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PDF SL832256K1F-xxAG 64-Pin 28-pin 64-pin SL832256K1F-12AG A0-A17 DQ8-11 WEA0-A17 edge connector 64 pin a1657 30 pin simm memory transistor CS4 28-pin SOJ SRAM
SO-DIMM 100-pin

Abstract: A839 NC133 SL936512K2M-09DFVG SO-DIMM 144-pin
Text: 140 DQ31 Pin Functions Pin Name Pin Locations Pin Function A0-A17 Address Inputs , WE A0-A17 CS0 OE BW2 BEL BW3 BEH CLK2 DQ0-7 DQ8-15 DP0-1 ADS C WE A0-A17 CS OE0 DQ0-7 DQ8-15 DP0-1 CS1 OE1 CLK ADS C WE A0-A17 OE BW2 BEL BW3 , -1 DQ16-23 DQ24-31 DP2-3 ADS C WE A0-A17 A0-A17 WE ADS VCC VSS · · · 0.1µF capacitors To


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PDF SL936512K2M-09DFVG 144-Pin 87MHz SL936512K2M-09DFVG 100-pin SO-DIMM 100-pin A839 NC133 SO-DIMM 144-pin
SL832256K1S-15AVG

Abstract: a844
Text: Pin Name Pin Function A3 A0-A17 Address Inputs DQ0-DQ31 Data Inputs/Outputs WE , SL832256K1S-xxAVG 72-PIN SRAM SIMMS FUNCTIONAL BLOCK DIAGRAM DQ0-3 DQ0 DQ1 CS DQ2 OE WE A0-A17 DQ3 CS1 DQ4-7 DQ0 DQ1 CS DQ2 OE WE A0-A17 DQ3 DQ8-11 DQ0 DQ1 CS DQ2 OE WEA0-A17 DQ3 CS2 DQ12-15 DQ0 DQ1 CS DQ2 OE WE A0-A17 DQ3 DQ16-19 DQ0 DQ1 CS DQ2 OE WE A0-A17 DQ3 CS3 DQ20-23 DQ0 DQ1 CS DQ2 OE WE A0-A17 DQ3 DQ24-27 DQ0 DQ1 CS DQ2 OE WEA0-A17 DQ3 CS4


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PDF SL832256K1S-xxAVG 72-Pin 32-pin A0-A17 DQ8-11 WEA0-A17 DQ12-15 SL832256K1S-15AVG a844
edge connector 64 pin

Abstract: SL832256K1F-12AVG SL832256K1F-15AVG A0-A17 10DQ3 A1657
Text: CONFIGURATION Pin Symbols Pin Locations (SIMM) Pin Names Pin Name Pin Function DQ18 A0-A17 , SL832256K1F-xxAVG 64-PIN SRAM SIMMS FUNCTIONAL BLOCK DIAGRAM DQ0-3 DQ0 DQ1 CS DQ2 OE WE A0-A17 DQ3 CS1 DQ4-7 DQ0 DQ1 CS DQ2 OE WE A0-A17 DQ3 DQ8-11 DQ0 DQ1 CS DQ2 OE WEA0-A17 DQ3 CS2 DQ12-15 DQ0 DQ1 CS DQ2 OE WE A0-A17 DQ3 DQ16-19 DQ0 DQ1 CS DQ2 OE WE A0-A17 DQ3 CS3 DQ20-23 DQ0 DQ1 CS DQ2 OE WE A0-A17 DQ3 DQ24-27 DQ0 DQ1 CS DQ2 OE WEA0-A17 DQ3 CS4


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PDF SL832256K1F-xxAVG 64-Pin 32-pin A0-A17 DQ8-11 WEA0-A17 DQ12-15 edge connector 64 pin SL832256K1F-12AVG SL832256K1F-15AVG 10DQ3 A1657
1998 - plcc32 pinout

Abstract: 1N914 PLCC32 TSOP32
Text: . PLCC32 (K) TSOP32 (N) 8 x 20 mm Figure 1. Logic Diagram VCC VPP 18 8 A0-A17 W , 1st Cycle Cycles 2nd Cycle Operation A0-A17 DQ0-DQ7 X 2 Write X 80h or 90h 00000h 20h 00001h F5h X 20h Read X Data Output A0-A17 Data Input 00h Electronic Signature (2) Read Write Write DQ0-DQ7 Write 1 A0-A17 Read , 2 Write A0-A17 A0h Write X 40h Program Program Verify 2 Write X


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PDF M28W201 256Kb 100ns M28W201 plcc32 pinout 1N914 PLCC32 TSOP32
CI 7473

Abstract: A10C SN74ABT7819
Text: FIFOB-A to A0-A17. The A0-A17 outputs are in the high-impedance state when CSA is high. ÜSB I Port-B , . The state of the A0-A17 outputs is controlled by CSA and W/RA. When both CSA and W/RA are low, the outputs are active. The A0-A17 outputs are in the high-impedance state when either CSA or W/RA is high , high, WENA is high, and the IRA flag Is high J3ata is read from Fl FOB-A to the A0-A17 outputs on the , (positive logic) CSA W/RA WENA RENA to WEN FIFOA-B A0-A17 (output enable) REN FIFOB-A WEN FIFOB-A


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PDF SN74ABT7819 SCBS125B 50-pF 80-Pin bl723 CI 7473 A10C SN74ABT7819
1N914

Abstract: M28F201 PLCC32 TSOP32
Text: VCC VPP 18 8 A0-A17 W DQ0-DQ7 M28F201 E Table 1. Signal Names A0 - A17 , A0-A17 DQ0-DQ7 X 2 Write X 80h or 90h 00000h 20h 00001h 0F4h or 0F5h X 20h Read X Data Output A0-A17 Data Input 00h Electronic (2) Signature Read Write Write DQ0-DQ7 Write 1 A0-A17 Read Read Operation Setup Erase/ 2 Write X 20h Erase Erase Verify Setup Program/ 2 2 Write A0-A17 0A0h Write


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PDF M28F201 M28F201 1N914 PLCC32 TSOP32
BO 817

Abstract: 5962-9470401QXA SN54ABT7819 010331A
Text: logic diagram (positive logic) CSA W/RA WENA m RENA :=o WEN FIFOA-B Output Enable ( A0-A17 ) REN FIFOB-A FUNCTION TABLES SELECT INPUTS A0-A17 A-PORT OPERATION CLKA CSA W/RA WENA RENA X H X X X î L H H X t L L X H High Z High Z Active None Write A0-A17tO FIFOA-B Read FIFOB-A to A0-A17 SELECT , are active. The A0-A17 outputs are in the high-impedance state when either CSA or W/RA is high. Data , - REVISED DECEMBER 1995 Terminal Functions TERMINAL NAME I/O DESCRIPTION A0-A17 I/O Port-A data


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PDF SN54ABT7819 512x18x2 SGBS305B 50-pF 5962-9470401QXA 84-Pin 10333fci BO 817 SN54ABT7819 010331A
1997 - M28F151

Abstract: No abstract text available
Text: 18 A0-A17 8 DQ0-DQ7 W Table 1. Signal Names A0 - A17 DQ0 - DQ7 E G W VPP VCC VSS February , Write Write A0-A17 X 0A0h 40h Write Read Write A0-A17 X X Data Input Data Output 0FFh Cycles Operation 1 2 Write Write Write 1st Cycle A0-A17 X X X DQ0-DQ7 00h 80h or 90h 20h Write Read X X 20h Data Output Read Read 2 00000h 00001h 20h 04Fh Operation 2nd Cycle A0-A17 DQ0-DQ7 Note: 1. X = VIL or VIH 2 , M28F151T, M28F151B Figure 5. Read Mode AC Waveforms tAVAV A0-A17 tAVQV E tELQV tELQX G tGLQV tGLQX


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PDF M28F151T M28F151B 00000h 10000h M28F151
SN74ABT7819

Abstract: No abstract text available
Text: /RA. When both CSA and W/RA are low, the outputs are active. The A0-A17 outputs are in the , AO-A17 (output enable) REN FIFOB-A FUNCTION TABLES SELECT INPUTS A0-A17 PORT-A OPERATION CLKA CSA W/RA WENA RENA X H X X X î L H H X î L L X H High Z High Z Active None Write A0-A17toFIFOA-B Read , A0-A17 I/O Port-A data. The 18-bit bidirectional data port for side A. AF/AEA 0 FIFOA- B almost-lull , transition of CLKA to either write data from A0-A17 to FIFOA - B or read data from Fl FOB - A to AO - A17


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PDF SN74ABT7819 512x18x2 SCBS125D 50-pF 80-Pin SN74ABT7819
Not Available

Abstract: No abstract text available
Text: either write data from A0-A17 to FIFOA-B or read data from FIFOB-A to A0-A17. The A0-A17 outputs are in , bidirectional interface between microprocessors and/or buses with synchronous control. The state of the A0-A17 outputs is controlled by CSA and W/RA. When both CSA and W/RA are low, the outputs are active. The A0-A17 , flag is highJData is read from FIFOB-A to the A0-A17 outputs on the low-to-high transition of CLKA , for operation from 0°C to 70°C. Function Tables PORTA SELECT INPUTS A0-A17 PORT-A OPERATION


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PDF SN74ABT7819 512x18x2 SCBS125G 50-pF
1995 - SN74ABT7819A

Abstract: W256
Text: No file text available


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PDF SN74ABT7819A SCBS756 50-pF 80-Pin SN74ABT7819A W256
1997 - 1N914

Abstract: M28F201 PLCC32 TSOP32
Text: . Logic Diagram VCC VPP 18 8 A0-A17 W DQ0-DQ7 M28F201 E Table 1. Signal Names A0-A17 DQ0-DQ7 Data Inputs / Outputs E Chip Enable G Output Enable W Write , M28F201 Table 5. Commands (1) Command 1st Cycle Cycles 2nd Cycle Operation A0-A17 , Data Output A0-A17 Data Input 00h Electronic Signature (2) Read Write Write DQ0-DQ7 Write 1 A0-A17 Read Read Operation Setup Erase/ 2 Write X 20h


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PDF M28F201 M28F201 1N914 PLCC32 TSOP32
1998 - M28F201

Abstract: PLCC32 TSOP32
Text: 8 A0-A17 W DQ0-DQ7 M28F201 E Table 1. Signal Names A0-A17 DQ0-DQ7 Data Inputs , Operation A0-A17 DQ0-DQ7 X 2 Write X 80h or 90h 00000h 20h 00001h F4h X 20h Read X Data Output A0-A17 Data Input 00h Electronic Signature (2) Read Write Write DQ0-DQ7 Write 1 A0-A17 Read Read Operation Setup Erase/ 2 Write X 20h Erase Erase Verify Setup Program/ 2 2 Write A0-A17 A0h Write X


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PDF M28F201 256Kb M28F201 PLCC32 TSOP32
1994 - 5962-9470401QXA

Abstract: 5962-9470401QYA SN54ABT7819 W256
Text: No file text available


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PDF SN54ABT7819 SGBS305D 50-pF 59customer 5962-9470401QXA 5962-9470401QYA SN54ABT7819 W256
1994 - Not Available

Abstract: No abstract text available
Text: No file text available


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PDF SN54ABT7819 SGBS305D 50-pF 5962-9470401QXA 5962-947040i
1997 - plcc32 pinout

Abstract: M28F201 PLCC32 TSOP32
Text: . Logic Diagram VCC VPP 18 8 A0-A17 W DQ0-DQ7 M28F201 E Table 1. Signal Names A0-A17 DQ0-DQ7 Data Inputs / Outputs E Chip Enable G Output Enable W Write , M28F201 Table 5. Commands (1) Command 1st Cycle Cycles 2nd Cycle Operation A0-A17 , Data Output A0-A17 Data Input 00h Electronic (2) Signature Read Write Write DQ0-DQ7 Write 1 A0-A17 Read Read Operation Setup Erase/ 2 Write X 20h


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PDF M28F201 M28F201 plcc32 pinout PLCC32 TSOP32
1998 - M28F201

Abstract: PLCC32 TSOP32
Text: 8 A0-A17 W DQ0-DQ7 M28F201 E Table 1. Signal Names A0-A17 DQ0-DQ7 Data Inputs , Operation A0-A17 DQ0-DQ7 X 2 Write X 80h or 90h 00000h 20h 00001h F4h X 20h Read X Data Output A0-A17 Data Input 00h Electronic Signature (2) Read Write Write DQ0-DQ7 Write 1 A0-A17 Read Read Operation Setup Erase/ 2 Write X 20h Erase Erase Verify Setup Program/ 2 2 Write A0-A17 A0h Write X


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PDF M28F201 256Kb M28F201 PLCC32 TSOP32
1995 - SN74ABT7819A

Abstract: W256
Text: No file text available


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PDF SN74ABT7819A SCBS756 50-pF 80-Pin SN74ABT7819A W256
1996 - plcc32 pinout

Abstract: 1N914 PLCC32 TSOP32
Text: ) 8 x 20 mm Figure 1. Logic Diagram VCC VPP 18 8 A0-A17 W DQ0-DQ7 M28V201 , A0-A17 DQ0-DQ7 X 2 Write X 80h or 90h 00000h 20h 00001h 0F4h or 0F5h X 20h Read X Data Output A0-A17 Data Input 00h Electronic (2) Signature Read Write Write DQ0-DQ7 Write 1 A0-A17 Read Read Operation Setup Erase/ 2 Write X 20h Erase Erase Verify Setup Program/ 2 2 Write A0-A17 0A0h Write


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PDF M28V201 150ns M28V201 plcc32 pinout 1N914 PLCC32 TSOP32
1996 - M28F201

Abstract: No abstract text available
Text: ) TSOP32 (N) 8 x 20 mm Figure 1. Logic Diagram VCC VPP 18 A0-A17 8 DQ0-DQ7 W E G , 0C0h 0FFh 2 2 Write Write A0-A17 X 0A0h 40h Write Read Write A0-A17 X X Data Input Data Output 0FFh Cycles Operation 1 2 Write Write Write 1st Cycle A0-A17 X X X DQ0-DQ7 00h 80h or 90h 20h Write Read X X 20h Data Output Read Read 2 00000h 00001h 20h 0F4h Operation 2nd Cycle A0-A17 DQ0-DQ7 Note: 1. X = , manufacturer or device codes. 6/20 M28F201 Figure 5. Read Mode AC Waveforms tAVAV A0-A17 tAVQV E


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PDF M28F201 M28F201
1992 - SN74ABT7819

Abstract: W256
Text: No file text available


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PDF SN74ABT7819 SCBS125G 50-pF 80-Pin SN74ABT7819 W256
1994 - Not Available

Abstract: No abstract text available
Text: No file text available


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PDF SN54ABT7819 SGBS305D 50-pF 5962-9470401QXA
302AJ

Abstract: 256KX16
Text: DQ1 A0-A17 A1 4 c 3 45 DQ2 A2 5 c 3 44 DQ3 WL 6 c 3 43 E1(0-3) ~Ë(4-7> E2(4-7) 7 c 3 42 , A0-A17 E1 WL WH E2 E3 -DQ0 -DQ1 "I— DQ4 -DQ5 -DQ8 L-DQ9 -DQ12 -DQ13 -DQ2 L-DQ6 -DQ10 -DQ14 L-DQ3 1—DQ7 -DQ11 "C-DQ15 512Kx8 Configuration DQ0 DQ1 A0-A17. -W - vcc - 03b 02b 01b , A18 VSS J - A0-A17 - E1 - WL-WH- -~E2 ■E3 DQ0 DQ1 DQ4 w DQ5 w DQ8 DQ9 DQ12 DQ4 , Configuration A0-A17. W VCC 03b 02b 01b O0b C Alb C A0b n I—CS1b C VCC c 139 DECODER 3 GND 3 03a 3 02a J


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PDF EDI8M16256C 256KX16 EDI8M16256C 4096K-bit 256Kx1 256Kx4 256Kx16, 512Kx8 1024Kx4 302AJ
EM256C08N

Abstract: EM256C08NC EM256C08TC TWC-500
Text: Pin Name A0-A17 D0-D7 CE1 CE2 OE Pin Function Pin Name Address Inputs Data Inputs , 0 25 0 ns ns FIGURE 3: Read Cycle Timing (WE = VIH) tRC A0-A17 tAA tHZ tCE CE1 , Valid 5 NanoAmp Solutions EM256C08 FIGURE 4: Write Cycle Timing (OE clock) tWC A0-A17 , tOHZ tOW High-Z Data Out FIGURE 5: Write Cycle Timing (OE fixed) tWC A0-A17 tWR tAW


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PDF EM256C08 EM256C08 256Kx8 EM10R2XX EM256C08N EM256C08NC EM256C08TC TWC-500
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