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A0-A16 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
ADA16

Abstract: A0-A16
Text: A0-A16 NOE DQO-7 129kx8 NWE/NCS/CE A0-A16 NOE DQO-7 12BXXÍ NWE/NCS/CE A0-A16 NOE NW6/NCS/CE A0-A16 NOE NWE/NCS/CE AD-A16 NOE NWE/NCS/CE A0-A16 NOE C T IS PINOUT CONFIGURATION ch«ck B«*(x16) A0-A16


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PDF HC83241 120x100 ADA16 A0-A16
M12j

Abstract: M10I
Text: – SEL0 ■5EÏ ■CE2 • sen CE0 ÜE ■W ■A0-A16 ■=6 M14 M12j M10I 8 M8 I -1/016-1/023 -1/00-1/07 CE7 • SE10 ■ÜE5 ■CE3 • SEL1 CET ÜE ■W ■A0-A16 ■=0 M15! M13; M1t| M9 ? S -I/024-I/031 -1/08-1/015 CES -SEL1 - en • CEÎ SEL0 ere se ■*E ■A0-A16 â , • WE ■A0-A16 ■=0 M7 I M5 I M3 Ml -1/024-1/031 -1/08-1/015 Commercial only. PIN NAMES A0-A16 Address Inputs I/00-I/031 Data Input/Output CËÔ-CË7 Low Chip Enables ■SEL0, SEL1


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PDF DPS512X32AV3 T-V4-23-/V DPS512X32AV3 30A044-11 T-46-23-14 M12j M10I
Not Available

Abstract: No abstract text available
Text: NWE/NCS/CE NWE.'JiCSiCE AC-A1S NOE A0-A16 DOC-7 123/03 HW E'SCS.'CE AC-A1S NOE AC-A16 NOE A0-A16 NOE A0-A16 NOE A0-A16 NOE _E IE z c NOE 66 Pin Grid Array (PGA


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PDF GGD1D17 HC83241 1x101 -120x100
Not Available

Abstract: No abstract text available
Text: 14 A8 CE A1 IN 11 13 16 GND 17 D3 IN/OUT 22 A0-A16 D0-D7 CE OE PGM 24 , INPUT MBM27C1001-20(2/2) READ MODE(VDD = +5V,VPP = +5V) OE CE PGM A0-A16 D0-D7 0 0 1 A IN D , DISABLE PROGRAM MODE(VDD = +6V,VPP = +12.5V) MODE OE CE PGM A0-A16 1 0 0 A IN 1-BYTE 0 1 A


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PDF MBM27C1001-20 A2-A16
Y240

Abstract: 0A07A
Text: D0-D15 I/O 16 A0-A16 I 17 /CS I 3.3 V /OE I /WE I /UBE , , A0-A16 , /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1, OSC2, /RESET, /DOFF, TEST, MS 5 V STB , management circuit) A0-A16 RAM PD16663 4 480×320 1FFF80H-1FFFEH 49 16 2 (Arbiter) RAM , . CPU 7.1 RDY RAM RAM CPU RDY CPU 7.1.1 A0-A16 ,/UBE /CS /OE,/WE Hi-z Hi-z , PL0, PL1 LSI No. DIR 1 OSC1, OSC2 D0-D15, A0-A16 , /CS, /OE, /WE, /UBE, RDY, /RESET, /DOFF


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PDF PD16663 PD16667 PD16663N-XXX PD16663N-051 S13392JJ1V0DS00 Y240 0A07A
Dense-Pac Microsystems

Abstract: No abstract text available
Text: ) • 66-Pin PGA "VERSA-STACK" Package FUNCTIONAL BLOCK DIAGRAM ÜE2 SEL0 CE0 ÜE WF A0-A16 CE1 1/016-I/023 0E A0-A16 M1 -1/08— 1/015 Commercial only. PIN NAMES A0-A16 Address Inputs I


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PDF DPS128X24AV3 DPS128X24AV3 30A044-31 D00G445 T-46-23-14 Dense-Pac Microsystems
1995 - AD 4153

Abstract: AT17128 ad 8077 AT171 AT6010 AT6005 AT6003 AT6002 AT17XXX Vector Controls
Text: use only one, D0. A0-A16 A0-A16 are address output signals, used by modes 1, 2 and 5, to drive , control signals as well as the A0-A16 output signals, ERR output, and CSOUT signal. Data is loaded into , Configuration Pins Used CON, CS, M0, M1, M2, CCLK Dual-Function Pins Used D0-D7, A0-A16 Optional , Used CON, CS, M0, M1, M2, CCLK Dual-Function Pins Used D0-D7, A0-A16 Mode 2 (Figure 7 , MODE 2 M1 M2 M0 CCLK A0-A16 D0-D7 CS CON Figure 6. Mode 1 Configuration AT60xx MODE 1 M0


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PDF AT6000 A0-A16 AD 4153 AT17128 ad 8077 AT171 AT6010 AT6005 AT6003 AT6002 AT17XXX Vector Controls
DPS512X32BV3

Abstract: No abstract text available
Text: CE4 WE0 OE A0-A16 C M14 5 M6 M12 1 S 1/00-1/07 1/016-1/023 CE5 WEI DE A0-A16 C M15 J M7 J £ M13 i S I/0S-I/015 1/024-1/031 CE0 WE0 OE A0-A16 - 1/016-1/023 - 1/00-1/07 CEI WE1 DE A0-A16 M3


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PDF DPS512X32BV3 DPS512X32BV3 500mV 30A044-12
1998 - TSOP32

Abstract: M68Z128
Text: compatible. Table 1. Signal Names A0-A16 Address Inputs DQ0-DQ7 Data Inputs / Outputs E1 Chip Enable 1 E2 Write Enable VCC A0-A16 DQ0-DQ7 W M68Z128 Supply Voltage VSS , for any given device. Figure 5. Address Controlled, Read Mode AC Waveforms tAVAV A0-A16 , VALID A0-A16 tAVQV tAXQX tE1LQV tE1HQZ E1 tE1LQX tE2HQV tE2LQZ E2 tE2HQX tGLQV , Controlled, Write AC Waveforms tAVAV VALID A0-A16 tAVWH tWHAX tAVE1L E1 tAVE2H E2 tWLWH


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PDF M68Z128 128Kb TSOP32 M68Z128 TSOP32
1998 - M68Z128

Abstract: TSOP32
Text: x 20mm) Figure 1. Logic Diagram VCC 17 8 A0-A16 DQ0-DQ7 W A0-A16 Address , A0-A16 VALID tAVQV DQ0-DQ7 tAXQX DATA VALID AI01078 Note: E1 = Low, E2 = High, G = Low , Waveforms tAVAV A0-A16 VALID tAVQV tAXQX tE1LQV tE1HQZ E1 tE1LQX tE2HQV tE2LQZ , Figure 8. Write Enable Controlled, Write AC Waveforms tAVAV A0-A16 VALID tAVWH tWHAX tAVE1L , A0-A16 VALID tAVE1H tAVE1L tE1HAX tE1LE1H E1 tAVE2L tAVE2H tE2HE2L tE2LAX E2


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PDF M68Z128 128Kb M68Z128 TSOP32
2000 - Not Available

Abstract: No abstract text available
Text: available in the standard 450mil-wide TSOP type 1 package. Figure 1. Logic Diagram VCC 17 A0-A16 8 DQ0-DQ7 Table 1. Signal Names A0-A16 DQ0-DQ7 E1 E2 G W VCC VSS NC Address Inputs Data Input , . Figure 5. Address Controlled, Read Mode AC Waveforms tAVAV A0-A16 tAVQV VALID tAXQX DQ0-DQ7 DATA , Enable or Output Enable Controlled, Read Mode AC Waveforms. tAVAV A0-A16 tAVQV tE1LQV E1 tE1LQX tE2HQV , , Write AC Waveforms tAVAV A0-A16 VALID tAVWH tAVE1L E1 tAVE2H E2 tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA


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PDF M68Z128W 128Kb TSOP32 M68Z128W
2000 - M48Z128

Abstract: M48Z128Y SOH28 TSOP32
Text: A0-A16 Data Inputs / Outputs E Chip Enable G Ground NC A0-A16 DQ0-DQ7 Supply , housing containing the battery. M48Z128, M48Z128Y Figure 3. Block Diagram VCC A0-A16 POWER , DQ0-DQ7 E E1CON E E2CON E3CON E4CON A0-A16 A RST B W BL VSS VSS AI03625 , . CL = 5pF. Figure 7. Address Controlled, Read Mode AC Waveforms tAVAV A0-A16 VALID tAVQV , Mode AC Waveforms tAVAV A0-A16 VALID tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV


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PDF M48Z128 M48Z128Y 128Kb PMDIP32 M48Z128: M48Z128Y: 28-PIN 32-LEAD M48Z128 M48Z128Y SOH28 TSOP32
2000 - M68Z128

Abstract: TSOP32
Text: inputs and outputs are TTL compatible. VCC 17 8 A0-A16 DQ0-DQ7 Table 1. Signal Names A0-A16 Address Inputs W DQ0-DQ7 Data Input/Output E1 E1 Chip Enable 1 E2 E2 , A0-A16 VALID tAVQV DQ0-DQ7 tAXQX DATA VALID AI01078 Note: E1 = Low, E2 = High, G = Low , Waveforms. tAVAV A0-A16 VALID tAVQV tAXQX tE1LQV tE1HQZ E1 tE1LQX tE2HQV tE2LQZ , Controlled, Write AC Waveforms tAVAV A0-A16 VALID tAVWH tAVE1L tWHAX E1 tAVE2H E2 tWLWH


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PDF M68Z128 128Kb TSOP32 M68Z128 TSOP32
2000 - M68Z128

Abstract: TSOP32
Text: inputs and outputs are TTL compatible. VCC 17 8 A0-A16 DQ0-DQ7 Table 1. Signal Names A0-A16 Address Inputs W DQ0-DQ7 Data Input/Output E1 E1 Chip Enable 1 E2 E2 , A0-A16 VALID tAVQV DQ0-DQ7 tAXQX DATA VALID AI01078 Note: E1 = Low, E2 = High, G = Low , Waveforms. tAVAV VALID A0-A16 tAVQV tAXQX tE1LQV tE1HQZ E1 tE1LQX tE2HQV tE2LQZ , Controlled, Write AC Waveforms tAVAV VALID A0-A16 tAVWH tWHAX tAVE1L E1 tAVE2H E2 tWLWH


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PDF M68Z128 128Kb TSOP32 M68Z128 TSOP32
1995 - M28F101

Abstract: PDIP32 PLCC32 TSOP32
Text: A0-A16 W DQ0-DQ7 M28F101 Supply Voltage VSS VPP Output Enable W VCC Chip , . Commands (1) Command 1st Cycle Cycles 2nd Cycle Operation A0-A16 DQ0-DQ7 X 2 Write X 90h 00000h 20h 00001h 07h X 20h Read X Data Output A0-A16 Data Input 00h Electronic Signature Read Write Write DQ0-DQ7 Write 1 A0-A16 , Program/ 2 2 Write A0-A16 0A0h Write X 40h Program Program Verify 2 Write


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PDF M28F101 PLCC32 PDIP32 TSOP32 M28F101 PDIP32 PLCC32 TSOP32
00005H

Abstract: Y240 09fe
Text: D0-D15 I/O 16 A0-A16 I 17 /CS I 3.3 V /OE I /WE I /UBE , , A0-A16 , /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1, OSC2, /RESET, /DOFF, TEST, MS 5 V STB , management circuit) A0-A16 RAM PD16663 4 480×320 1FFF80H-1FFFEH 49 16 2 (Arbiter) RAM , . CPU 7.1 RDY RAM RAM CPU RDY CPU 7.1.1 A0-A16 ,/UBE /CS /OE,/WE Hi-z Hi-z , PL0, PL1 LSI No. DIR 1 OSC1, OSC2 D0-D15, A0-A16 , /CS, /OE, /WE, /UBE, RDY, /RESET, /DOFF


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PDF PD16663 PD16667 PD16663N-XXX PD16663N-051 S13392JJ1V0DS00 00005H Y240 09fe
1998 - M28F101

Abstract: PDIP32 PLCC32 TSOP32
Text: Diagram VCC VPP 17 8 A0-A16 Table 1. Signal Names A0-A16 Data Inputs / Outputs E , 07h Table 5. Commands (1) Command 1st Cycle Cycles 2nd Cycle Operation A0-A16 , Output A0-A16 Data Input 00h Electronic Signature (2) Read Write Write DQ0-DQ7 Write 1 A0-A16 Read Read Operation Setup Erase/ 2 Write X 20h Erase Erase Verify Setup Program/ 2 2 Write A0-A16 A0h Write X 40h Program Program


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PDF M28F101 128Kb M28F101 PDIP32 PLCC32 TSOP32
Not Available

Abstract: No abstract text available
Text: M7 M5 M3 I/024-I/031 -1/08-1/015 CE4 CF2 SEL0 Ct5 · C T3 SEL0 CET CF0 CE · W A0-A16 · ÜE W A0-A16 · PIN-OUT DIAGRAM (T O P V IE W ) PIN NAMES A0-A16 1/00-1/031 CÊÜ-CË7 SEL0


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PDF DPS256X32AV3 I/024-I/031 A0-A16 A0-A16 30A04401
Not Available

Abstract: No abstract text available
Text: W A0-A16 · A0 -A1 6 · C Ë5 · SEL 1 · M6 ' M4 M2 0F7 · SEL1 · M7 ÜF4 . ÜF5 , O FT " H m i 0F W < -1/024-1/031 1/08-1/015 A0-A16 · A0-A16 - PIN-OUT DIAGRAM (TOP


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PDF DPS512X32V3 I/012 30A044-10
1998 - M68Z128

Abstract: TSOP32
Text: deselected. The M68Z128 is available in TSOP32 (8 x 20mm) package. Table 1. Signal Names A0-A16 , 17 8 A0-A16 DQ0-DQ7 W M68Z128 Supply Voltage VSS VCC Output Enable W , A0-A16 VALID tAVQV DQ0-DQ7 tAXQX DATA VALID AI01078 Note: E1 = Low, E2 = High, G = Low , Waveforms tAVAV VALID A0-A16 tAVQV tAXQX tE1LQV tE1HQZ E1 tE1LQX tE2HQV tE2LQZ , 8. Write Enable Controlled, Write AC Waveforms tAVAV VALID A0-A16 tAVWH tWHAX tAVE1L


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PDF M68Z128 128Kb M68Z128 TSOP32
A141

Abstract: A151 A161 M68Z128W TSOP32
Text: . Logic Diagram Vcc Table 1. Signal Names A0-A16 Address Inputs DQ0-DQ7 Data Input/Output ET Chip , Connected Internally A0-A16 W El E2 G 17 DQ0-DQ7 M68Z128W Vss November 1999 1/12 M68Z128W Table , Mode AC Waveforms A0-A16 DQ0-DQ7 =f tAVAV VALID Ì ■tAVQV ■->- tAXQX X DATA VALID I , Enable Controlled, Read Mode AC Waveforms. A0-A16 E1 dt tAVAV VALID E2 DQ0-DQ7 tAVQV ■tE1 LQV , M68Z128W Figure 8. Write Enable Controlled, Write AC Waveforms A0-A16 E1 E2 W DQ0-DQ7 M- ■tAVE1


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PDF M68Z128W 128Kb M68Z128W TSOP32 A141 A151 A161
Not Available

Abstract: No abstract text available
Text: A0-A16 A17 ROMCS OEB ROM Pin Name A0 - A17 Pin Function Address Inputs Write Enable , Z A0-A17 _ L H X L Dout A0-A16 X H L H H Z A0-A16 L H L H L Dout A0-A16 L H L L X Din A0-A16 H H L H L Dout A0-A16 H H L L X Din Note: (1) It is forbidden that ROMCSB pin and


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PDF LX50CM2256 LX50CM2256 A0-A17 A0-A16
2000 - M68Z128W

Abstract: TSOP32
Text: . TSOP32 (N) 8 x 20mm Figure 1. Logic Diagram VCC 17 8 A0-A16 DQ0-DQ7 Table 1. Signal Names A0-A16 Address Inputs W DQ0-DQ7 Data Input/Output E1 E1 Chip Enable 1 E2 , A0-A16 VALID tAVQV DQ0-DQ7 tAXQX DATA VALID AI01078 Note: E1 = Low, E2 = High, G = Low , Waveforms. tAVAV VALID A0-A16 tAVQV tAXQX tE1LQV tE1HQZ E1 tE1LQX tE2HQV tE2LQZ , Controlled, Write AC Waveforms tAVAV VALID A0-A16 tAVWH tWHAX tAVE1L E1 tAVE2H E2 tWLWH


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PDF M68Z128W 128Kb M68Z128W TSOP32
2001 - Not Available

Abstract: No abstract text available
Text: ) 8 x 20mm Figure 1. Logic Diagram VCC 17 8 A0-A16 DQ0-DQ7 Table 1. Signal Names A0-A16 Address Inputs W DQ0-DQ7 Data Input/Output E1 E1 Chip Enable 1 E2 E2 , . Address Controlled, Read Mode AC Waveforms tAVAV A0-A16 VALID tAVQV DQ0-DQ7 tAXQX DATA , Enable or Output Enable Controlled, Read Mode AC Waveforms. tAVAV VALID A0-A16 tAVQV tAXQX , tAVAV VALID A0-A16 tAVWH tWHAX tAVE1L E1 tAVE2H E2 tWLWH tAVWL W tWHQX tWLQZ


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PDF M68Z128W 128Kb M68Z128W
2000 - M68Z128

Abstract: TSOP32
Text: inputs and outputs are TTL compatible. VCC 17 8 A0-A16 DQ0-DQ7 Table 1. Signal Names A0-A16 Address Inputs W DQ0-DQ7 Data Input/Output E1 E1 Chip Enable 1 E2 E2 , A0-A16 VALID tAVQV DQ0-DQ7 tAXQX DATA VALID AI01078 Note: E1 = Low, E2 = High, G = Low , Waveforms. tAVAV VALID A0-A16 tAVQV tAXQX tE1LQV tE1HQZ E1 tE1LQX tE2HQV tE2LQZ , Controlled, Write AC Waveforms tAVAV VALID A0-A16 tAVWH tWHAX tAVE1L E1 tAVE2H E2 tWLWH


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PDF M68Z128 128Kb TSOP32 M68Z128 TSOP32
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