The Datasheet Archive

Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
AM5716AABCXEA Texas Instruments Sitara Processor: Arm Cortex-A15 & DSP 760-FCBGA -40 to 105
AM5718AABCX Texas Instruments Sitara Processor: Arm Cortex-A15 & DSP, Multimedia 760-FCBGA 0 to 90
TPS6590378ZWST Texas Instruments Power Management IC (PMIC) for ARM Cortex A15 Processors 169-NFBGA -40 to 85
AM5718AABCXQ1 Texas Instruments Sitara Processor: Arm Cortex-A15 & DSP, Multimedia 760-FCBGA -40 to 125
TPS6590379ZWSR Texas Instruments Power Management IC (PMIC) for ARM Cortex A15 Processors 169-NFBGA -40 to 85
AM5726BABCXAR Texas Instruments Sitara Processor: Dual Arm Cortex-A15 & Dual DSP 760-FCBGA -40 to 105

A0-A15 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2000 - DSP56F803

Abstract: DSP56F80X 64Kx16-bit
Text: spaces. IP Phone DSP56F803 Modems GS71116 A0-A15 Security A0-A15 D0-D15 Magnetic , DSP56F803 A0-A15 A0-A15 D0-D15 DQ1-DQ16 RD OE WR WE UB PS CE LB DS DSP56F80X CUSTOMER SUPPORT: GS71116 Technical Support: A0-A15 DQ1-DQ16 OE WE UB CE , authorized distributor Disclaimer: DSP56F803 A0-A15 PS D0-D15 GS71116 A0-A15 A16 DQ1-DQ16 RD


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PDF BR1537/D DSP56F80X 80MHz, DSP56F803 A0-A15 D0-D15 GS71116 DQ1-DQ16 DSP56F803 64Kx16-bit
CMS210 memory

Abstract: card 60-pin
Text: A0-A15 O E / Vpp E DO-D7 A0-A15 O E /V p p E D8-D15 M2t 64K x 8 M1 64K x 8 VC C VCC VSS 59 , Address Decoder 16 A0-A15 16 A16 10 CE 41 HCT139 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 1G 2Y2 2Y3 2G GND VC C 1A 2A 1B 2B O E /V p p DO- D7 E Ml 64K x 8 A0-A15 O E /V p p D8-D15 E M2t 64K x 8 Vcc VS S vcc v Ss 16 A0-A15 16 A0-A15 D0-D7 M3 64K x 8 O E /V p p E O E /V p p , 45 16 A0-A15 A0-A15 58 16 Addreaa Decoder A16 A17 10 12 CE 41 HCT139 1Y0 1A


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PDF CMS209, CMS210, CMS212, CMS213, CMS214, CMS216 SMN8209A-JUNE 1991-REVISED 16-Bit 60-Pin CMS210 memory card 60-pin
2012 - Not Available

Abstract: No abstract text available
Text: A0-A15 "A" data input bus. The 16-bit "A" input data bus to the ALU. B0-B15 "B" data input bus , ,OSA,OSB to C16 A0-A15 , B0-B15 to P,G ¯ ¯ A0-A15 , B0-B15 to OVF, ZERO A0-A15 , B0-B15 to C16 , QPL4C381-35 S0-S2,OSA,OSB to P,G ¯ ¯ S0-S2,OSA,OSB to OVF, ZERO S0-S2,OSA,OSB to C16 A0-A15 , B0-B15 to F0-F15 A0-A15 , B0-B15 to P,G ¯ ¯ A0-A15 , B0-B15 to OVF, ZERO 27 FTAB=1, FTF , ns ns ns ns ns ns ns ns ns ns ns ns Unless Otherwise Specified A0-A15 , B0-B15 to


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PDF QPL4C381 QPL4C381 16-bit L4C381 16bit L4C381.
2008 - CMGA3-P68

Abstract: L4C381 5962-8995901YA
Text: A0-A15 "A" data input bus. The 16-bit "A" input data bus to the ALU. B0-B15 "B" data input bus , ,OSB to P,G ¯ ¯ S0-S2,OSA,OSB to OVF, ZERO S0-S2,OSA,OSB to C16 A0-A15 , B0-B15 to P,G ¯ ¯ A0-A15 , B0-B15 to OVF, ZERO A0-A15 , B0-B15 to C16 Clock to F0-F15 16 FTAB=0, FTF=1, CL , ,OSA,OSB to OVF, ZERO S0-S2,OSA,OSB to C16 A0-A15 , B0-B15 to F0-F15 A0-A15 , B0-B15 to P,G ¯ ¯ A0-A15 , B0-B15 to OVF, ZERO 27 FTAB=1, FTF=0, QPL4C381-45 QPL4C381-35 FTAB=1, FTF


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PDF QPL4C381 QPL4C381 16-bit L4C381 16bit L4C381. CMGA3-P68 5962-8995901YA
DSP56156

Abstract: PB10 PB12 SC10 MC68000 PIO
Text: ) A0-A15 (Address Bus) - three state, active high outputs. A0-A15 change in t0 and specify the address for external program and data memory accesses. If there is no external bus activity, A0-A15 remain at their previous values. A0-A15 are three-stated during hardware reset or when the DSP is not bus master , is referenced. PS/DS timing is the same for the A0-A15 address lines. PS/DS is high for program , . A0-A15 PS/DS R/W WR RD Data In D0-D15 Data Out Bus Operation (Read-Write- 0WT) T0


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PDF DSP56156 PB10 PB12 SC10 MC68000 PIO
1995 - DSP56100

Abstract: DSP56166 PB10 PB12 FUNCTION BG IN MC68000 os1p
Text: X:$FF7F). PEREN timing is the same as the A0-A15 address lines; it is asserted and deasserted , qualifies the A0-A15 and PS/DS pins. WR can be connected directly to the WE pin of a static RAM. WR is , DSP. When RD is asserted, it qualifies the A0-A15 and PS/DS pins. RD can be connected directly to , Total 112 ADDRESS AND DATA BUS (32 PINS A0-A15 (Address Bus) - three state, active high outputs , no external bus activity, A0-A15 remain at their previous values. A0A15 are three-stated during


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PDF DSP56100 DSP56166 DSP56100 DSP5616 DSP56166. PB10 PB12 FUNCTION BG IN MC68000 os1p
8X305

Abstract: 8X360 146g specifications of ic 1408 1S08 N8X360I N8X360N
Text: GND1, GND2 Ground 2 TSCL Address 3-State Control Pin TSCL Action 1 Enable A0-A15 0 Disable (3-State) 3-18 A0-A15 16 3-State Address Output Plris: AO is LSB. 19, 21 -23 RS3 - RSO Register Select Input , Low-level input current Vcc = Max, V|L - 0.5V -500 M Vol Low-level output voltage iv TC A0-A15 Vcc = Min Iol - 16mA Iol - 8mA Iol *= 8mA 0.55 0.55 0.55 V V V Voh High-level output voltage 17 TC A0-A15 Vcc , IV TC A0-A15 Vcc-Max Only 1 output at a time -20 -20 -20 mA mA mA ice Vcc-Max 70 100 mA 'BB


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PDF 8X360 8X305 8X305. 6X305 a0-a15 146g specifications of ic 1408 1S08 N8X360I N8X360N
1995 - PB12

Abstract: PC10 DSP56166 PB10
Text: DATA BUS (32 PINS) A0-A15 (Address Bus) - three state, active high outputs. A0-A15 change in t0 , activity, A0-A15 remain at their previous values. A0-A15 are three-stated during hardware reset. D0-D15 , referenced. PS/DS timing is the same as the A0-A15 address lines. PS/DS is high for program memory access , PB12 PB13 PB14 EXTAL CLKO SXFC VddS GNDS A0-A15 D0-D15 Vdd Add/Data Vss Add/Data BS , external data has been latched inside the DSP. When RD is asserted, it qualifies the A0-A15 and PS/DS


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PDF DSP56166 16-BIT PB12 PC10 PB10
1996 - G30-88

Abstract: G38-87
Text: the pins A0-A15 , D0-D15, PS, DS, RD, and WR derates linearly at 1.7 ns per 20 pF of additional , , the PS, DS, RD, and WR strobes remain deasserted and A0-A15 do not change from their previous state , Min Max 4 16.6 ns 20 21 CLKO High to A0-A15 Valid 5.2 12.4 ns 22 , D0-D15 Out Tri-state - 15 ns 35 CLKO High to A0-A15 Invalid 2.5 3.5 ns 36 , ) 21 35 A0-A15 (See Note) 36 22 PS, DS 23 WR (Output) 29 24 31 RD (Output) 30


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PDF DSP56L811 AA0207 AA0208 AA0209 AA0210 G30-88 G38-87
Not Available

Abstract: No abstract text available
Text: Pulse Width High Fall Time, Rise Time A0-A15 Hold Time A0-A15 Setup Time BA0-BA7 Hold Time BA0-BA7 Setup , Time Clock Pulse Width Low Clock Pulse Width High Fall Time, Rise Time A0-A15 Hold Time A0-A15 Setup , THE WESTERN DESIGN CENTER, INC. W65C816S PHI2(IN| R/WB, MLB, VPB, A0-A15 , VDA, VPA Read


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PDF W65C816S A0-A15,
Not Available

Abstract: No abstract text available
Text: of Pins 32 9 4 3 15 2 10 7 4 9 15 1 1 112 ADDRESS AND DATA BUS (32 PINS) A0-A15 (Address Bus) - three state, active high outputs. A0-A15 change in t0 and specify the address for external program and data memory accesses. If there is no external bus activity, A0-A15 remain at their previous values. A0-A15 are three-stated during hardware reset or when the DSP is not bus master. D0-D15 , /DS timing is the same for the A0-A15 address lines. PS/DS is high for program memory access and is


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PDF DSP56156 16-BIT
50p06

Abstract: LQFP100 TMP91CY22IFG ad015
Text: fFPH ( = x) tFPH 37.0 ns 2 A0-A15 ALE tAL 0.5x - 14 4 ns 3 ALE A0-A15 tLA 0.5x - 16 2 ns 4 ALE High tLL x - 20 17 ns 5 ALE RD , tCLW x - 10 27 ns 8 A0-A15 RD / WR tACL x - 23 14 ns 9 A0-A23 RD , WR A0-A23 tCAW x - 13 24 ns 12 A0-A15 D0-D15 tADL 3.0x - 38 73 ns , A0-A23 WAIT 22 A0-A15 WAIT 1+n WAIT 1+n WAIT 1+n WAIT tAWH 3.5x - 60 69


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PDF TLCS-900/L1 TMP91CY22IFG TMP91CY22I TMP91CY22I 900/L1 TLCS-90/900 50p06 LQFP100 TMP91CY22IFG ad015
1998 - M28F102

Abstract: PLCC44
Text: Address Inputs DQ0 - DQ15 A0-A15 Output Enable W Supply Voltage VSS E Program , Cycles Operation A0-A15 2nd Cycle DQ0-DQ15 (2) X 2 Write X xx90h 0020h 0001h 0050h X xx20h Read X Data Output A0-A15 Data Input xx00h Electronic Signature 0000h Write Write Read Write 1 A0-A15 Read Read DQ0-DQ15 (2 , Write A0-A15 xxA0h Write X xx40h Program Program Verify 2 Write X xxC0h


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PDF M28F102 0020h 0050h M28F102 PLCC44
1995 - M28F102

Abstract: PLCC44
Text: 16 A0-A15 W DQ0-DQ15 M28F102 E Table 1. Signal Names A0 - A15 DQ0 - DQ15 Data , 0050h Table 5. Commands (1) Command 1st Cycle Cycles 2nd Cycle Operation A0-A15 , X Data Output A0-A15 Data Input xx00h Electronic Signature Read Write Write DQ0-DQ15 (2) Write 1 A0-A15 Read Read Operation Setup Erase/ 2 Write X xx20h Erase Erase Verify Setup Program/ 2 2 Write A0-A15 xxA0h Write X xx40h


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PDF M28F102 PLCC44 TSOP40 PLCC44 M28F102
M28F102

Abstract: PLCC44
Text: (K) TSOP40 (N) 10 x 14mm Figure 1. Logic Diagram VCC VPP 16 16 A0-A15 W , A0-A15 Data Input xx00h Electronic Signature DQ0-DQ15 (2) Write DQ0-DQ15 A0-A15 Write A0-A15 Operation Read Operation Setup Erase/ 2 Write X xx20h Erase Erase Verify Setup Program/ 2 2 Write A0-A15 xxA0h Write X xx40h Program , Figure 5. Read Mode AC Waveforms tAVAV A0-A15 tAVQV tAXQX E tELQV tEHQZ tELQX G tGLQV


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PDF M28F102 PLCC44 TSOP40 M28F102
1995 - M28F102

Abstract: PLCC44
Text: (K) TSOP40 (N) 10 x 14mm Figure 1. Logic Diagram VCC VPP 16 16 A0-A15 W , A0-A15 Data Input xx00h Electronic Signature DQ0-DQ15 (2) Write DQ0-DQ15 A0-A15 Write A0-A15 Operation Read Operation Setup Erase/ 2 Write X xx20h Erase Erase Verify Setup Program/ 2 2 Write A0-A15 xxA0h Write X xx40h Program , Figure 5. Read Mode AC Waveforms tAVAV A0-A15 tAVQV tAXQX E tELQV tEHQZ tELQX G tGLQV


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PDF M28F102 PLCC44 TSOP40 M28F102
1995 - DSP56156

Abstract: MC68000 PB12 SC10-11
Text: goes high in t0. R/W is three-stated during hardware reset. Address and Data Bus A0-A15 (Address Bus) - three-state, active high outputs. A0-A15 change in t0 and specify the address for external program and data memory accesses. If there is no external bus activity, A0-A15 remain at their previous values. A0-A15 are three-stated during hardware reset. D0-D15 (Data Bus) - three-state , A0-A15 address lines. PS/DS is high for program memory access and is low for data memory access. If the


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PDF A0-A15 A0-A15 D0-D15 DSP56156 MC68000 PB12 SC10-11
DSP56166

Abstract: PB10 PB12 PC10
Text: AND DATA BUS (32 PINS) A0-A15 (Address Bus) - three state, active high outputs. A0-A15 change , external bus activity, A0-A15 remain at their previous values. A0-A15 are three-stated during hardware , memory is referenced. PS/DS timing is the same as the A0-A15 address lines. PS/DS is high for program , Vdd Vss HA0 HA1 HA2 PB11 PB12 PB13 PB14 EXTAL CLKO SXFC VddS GNDS A0-A15 D0-D15 , latched inside the DSP. When RD is asserted, it qualifies the A0-A15 and PS/DS pins. RD is three-stated


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PDF DSP56166 PB10 PB12 PC10
2000 - M59BW102

Abstract: No abstract text available
Text: . The device is offered in TSOP40 (10 x 14mm) package. VCC 16 16 A0-A15 DQ0-DQ15 W E , Table 1. Signal Names Figure 2. TSOP Connections A0-A15 A9 A10 A11 A12 A13 A14 A15 ALE , address inputs A0-A15 and the Data Inputs/Outputs DQ0-DQ15. Memory control is provided by Chip Enable E , Inputs ( A0-A15 ). The address inputs for the memory array are latched during a write operation on the , 1 0 Toggle Toggle Cntr odd Cntr even DQ0-DQ15 A0-A15 G E ALE


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PDF M59BW102 TSOP40 M59BW102
Not Available

Abstract: No abstract text available
Text: PIN N A M ES A0-A15 Address Inputs I/00-I/015 Data Input/Output Œ Ü -C Ë 3 Chip , ET — ŒÔ — A0-A15 — 30A00&O4 REV. A I/ 0 6 - M 13 I/0 1 3 - 1/09- M 14 M 10 M 7 1010/ M il W EB— W E T -~ CË2 — CET— . A0-A15 — A0-A15 , . A0-A15 - Twilight Technology _ DPS1024 Dense-Pac Microsystems, Inc. CAPACITAN CE 4


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PDF DPS1024 DPS1024 S1024 1/01YSTEM S1024
Not Available

Abstract: No abstract text available
Text: TTL-Compatible • 900 mil, 42-pin D IP pinout • Commercial Only P IN N A M ES A0-A15 Address , Š2 A0-A15 — A0-A15 — . _ A0-A15 — ~ 4-9 1/012- M9 I/09- M2 I/03 â , €¢ A0-A15 ■Twilight Technology DPS1037 Dense-Pac Microsystems, Inc. R EC O M M EN D E D O PER


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PDF DPS1037 DPS1037 64Kx1 ectinologyA04
Not Available

Abstract: No abstract text available
Text: £ 5 A4 £ 6 A5 £7 A6 £ 8 A7C 9 A8 £ 10 A9 ËC 13 GC GND £ 14 12 A0-A15 DQ1-DQ4 E G GND NC , ( A0-A15 ) The 16 addresses select one of the 65,536 4-bit words in the RAM. The address inputs must be , ) [* A0-A15_ ^ *c(rd) ` ~)K - *a(A)- *] _L PREVIOUS , STATIC RANDOM-ACCESS MEMORY write cycle timing (G = V|H, W controlled) *c(W) A0-A15 = J C , -BIT HIGH-SPEED STATIC RANDOM-ACCESS MEMORY write cycle timing (G = Vm, E controlled) h - A0-A15 I I


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PDF TMS6709 144-BIT 28-Pin TMS6709-20 TMS6709-25 SMSS709
2000 - M59BW102

Abstract: No abstract text available
Text: . The device is offered in TSOP40 (10 x 14mm) package. VCC 16 16 A0-A15 DQ0-DQ15 W E , Table 1. Signal Names Figure 2. TSOP Connections A0-A15 DQ0-DQ7 A9 A10 A11 A12 A13 A14 , address inputs A0-A15 and the Data Inputs/Outputs DQ0-DQ15. Memory control is provided by Chip Enable E , . Address Inputs ( A0-A15 ). The address inputs for the memory array are latched during a write operation on , 1 0 Toggle Toggle Cntr odd Cntr even DQ0-DQ15 A0-A15 G E ALE


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PDF M59BW102 TSOP40 M59BW102
idq10

Abstract: EDH816H64C 5S70
Text: Noise Immunity Single +5V (±10%) Supply Operation Pin Names A0-A15 E0-E3 W DQ0-DQ15 VCC VSS , Configuration T— E0 ■A0-A15 ■"ËT. "W ■£2 E3 -DQ0 "I—DQ1 "I—DQ2 m -DQ4 -DQ5 , "I—DQ15 128Kx8 Configuration DQ0 DQ1 A0-A15_ W VCC - 03b 02b Olb C O0b C - A1b 0 - A0b C -CS1b C VCC C 139 DECODER 3 GND 3 03a 3 02a 3 Ola 3 O0a 3 A1a 3 A0a 3 CS1a E A16 VSS J -E0 - A0-A15 â , DQ15 DQ7 256Kx4 Configuration OQ0 A0-A15.-W -VCC -, 03b C 02b C 01 b c O0b C A1b C A0b C Iâ


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PDF EDH816H64C35/45/55/70 64Kx16 EDH816H64C 1024K-b 64Kx1 64Kx4 128Kx8 256Kx4 idq10 5S70
1995 - TH sck 083

Abstract: sck 083 DSP56156 E400 WS-063 WT137
Text: Mode 2 and Mode 3. VIHR RESET 11 D0-D15 A0-A15 PS/DS R/W BS 12 10 First Fetch Figure 7 Asynchronous Reset Timing CLKO 13 RESET A0-A15 PS/DS BS R/W 14 Figure 8 , External Interrupt Timing (Negative Edge-Triggered) A0-A15 PS/DS BS R/W IRQA IRQB First , 22 IRQA IRQB 23 A0-A15 PD/DS BS R/W First Interrupt Instruction Fetch Figure 12 Synchronous Interrupt from Wait State Timing 24 IRQA 25 A0-A15 PD/DS BS R/W First Instruction


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PDF DSP56156 TH sck 083 sck 083 E400 WS-063 WT137
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