YM 1021 Search Results

Contextual Info: HB56A48A/AT/B-8/10/12 8-Bit DRAM 4,194,304-Word x 8-Bit High Density Dynamic RAM Module PIN OUT • DESCRIPTION The HB56A48 is a 4M x 8 dynamic RAM module, mounted eight 4Mbit DRAM HM514100JP sealed in SOJ package. An outline of the HB56A48 is 30-pin single in-line package having Lead types

CAT24C44

Abstract: CAT24C44I D1-D15 0DG2024
Contextual Info: bflE » • n b 2 b 15 0 D G 2 0 24 CATALYST SEMICONDUCTOR «CST IIIH C R T R L Y S T m a i i i S E M I C O N D U C T O R CAT24C44/CAT24C44I 256-Bit SERIAL NONVOLATILE CMOS STATIC RAM FEATURES ■ L o w P ow er CMOS T e ch n o lo g y ■ P ow er U p/D ow n P ro te ctio n

Contextual Info: p e b m 7 j" L Q Revised M ay 1999 74LCX245 Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs General Description Features The LCX245 contains eight non-inverting bidirectional buff­ ers w ith 3-STATE outputs and is intended fo r bus oriented

Contextual Info: IBM11S4360BN IBM11S4360BL Preliminary 4M x 36 SODIMM Module Features • 72 -P in S m all O utline D ual-ln -Lin e M e m o ry M odule • Perform ance: -6 0 -7 0 1rac R A S A c ce s s T im e 6 0n s 70ns ICAC C A S A c ce s s T im e 15ns 20ns • All inputs & outputs are T T L & C M O S

DC chopper

Contextual Info: MITSUBISHI MOSFET MODULES FM75E2Y-9,-10 DC CHOPPER USE INSULATED TYPE OUTLINE DRAWING FM75E2Y-9, -10 D im ensions in mm 94 CIRCUIT DIAGRAM e 2y . 75A . 450/500V • 1-Element in a package

Contextual Info: S E M I C O N D U C T O R tm General Description Features The VHC/VHCT244 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissi­

Contextual Info: IDT7164S IDT7164L CMOS STATIC RAM 64K 8K x 8-BIT Integrated D evice Technology, Inc. FEATURES: DESCRIPTION: • High-speed address/chip select access time — Military: 20/25/30/35/45/55/70/85ns (max.) — Commercial: 15/20/25/35/70ns (max.) • Low power consumption

Contextual Info: “ “ R e v is e d M a rc h 1999 SEMICONDUCTOR!!^ General Description LV T574 and L V T H 5 7 4 a re Features h ig h -s p e e d , lo w -p o w e r o c ta l D -ty p e flip -flo p fe a tu rin g s e p a ra te D -ty p e in p u ts fo r e a c h flip -flo p a n d 3 -S T A T E o u tp u ts fo r b u s -o rie n te d a p p lic a tio n s . A b u ffe re d C lo c k C P a n d O u tp u t E n a b le (O E ) a re

TDA 9370

Abstract: tda 7830 TDA 9370 with pin voltages tda 9370 ic tda 4558 ic tda 9370 ic tda 4558 TDA 4844 L 9790 0/TDA 9370 with pin voltages
Contextual Info: a AM ENDM ENT need AdvaM n“ Ü Mero Am85C30 Enhanced Serial Communications Controller Devices SUMMARY This amendm ent adds information to the Final Data Sheet on the Com mercial and Industrial 20 MHz speed grades. This latest offering complem ents the 8 ,1 0 , and

Contextual Info: ca W PS1M32-XXC M/HITE /M IC R O E L E C T R O N IC S 1Mx32 SRAM MODULE ADVANCED ' FEATURES • A cce ss Tim es o f 17, 20, 25, 35ns ■ C om m ercial T e m p era ture Range ■ Packaging ■ TTL C om p a tib le Inputs and O utputs ■ 5 V o lt Po w e r Supply

IS916

Abstract: EP610 PALCE610 EP610 ORDERING le3k
Contextual Info: USE GAL DEVICES FOR NEW DESIGNS FIN A L COM’ L: H-15/25 Lattice Semiconductor PALCE610 Family EE CMOS High Perform ance Program m able A rray Logic D IS TIN C TIV E C H A R A C TER ISTIC S • Lattice/V antis P rogram m able A rray Logic PAL a rchitecture

Contextual Info: S E M IC O N D U C T O R Revised April 1999 TM • 2 .3 V -3 .6 V V qq specifications provided General Description The LC X240 is an inverting octal buffer and line driver designed to be em ployed as a m em ory address driver, clock d river and bus oriented tra n sm itte r or receiver. The

transistors BC 557C

Abstract: BF366 SMD code 307C F199 transistor 2N5793 BC413 motorola ZENER diode marking code z7 equivalent of transistor bc212 bc 214 bc107c motorola 2n555
Contextual Info: S e le c to r G u id e s 1 M e ta l-C a n T ra n s is to rs 3 F ie ld -E ffe c t T ra n s is to rs 4 S m a ll-S ig n a l T u n in g , S w itc h in g and Z e n e r D io d e s 5 T a p e a n d R eel S p e c ific a tio n s P a ck ag e O u tlin e D im e n s io n s and

Contextual Info: r r u v m . TECHNOLOGY _ RH1021-5 Precision 5V R eference DCSCRIPTIOn n f t s o i u T t m n x im u m The RH1021-5 is a precision 5V reference with ultralow drift and noise, extremely good long term stability and almost total immunity to input voltage variations. The

ups circuit schematic diagram

Abstract: led driver circuit diagram ups schematic diagram MSC1212-01 MSC1212-01GS-BK P048 QFP64-P-1414-0
Contextual Info: E2C0021-27-Y3 O K I Semiconductor P rev iou s version: Jul. 1996 M SC 1212-01 48-Bit Grid/Anode Driver GENERAL DESCRIPTION The MSC1212-01 is a driver IC for VFD implemented in BiCM OS technology. The circuit consists of a 48-bit shift register and a 48-bit latch; they control display data, which

Motorola transistors MRF 947

Abstract: motorola hep cross reference 2N5070 2N5591 MOTOROLA Semicon volume 1 mrf532 transistor equivalents for 2n3866 siemens semiconductor manual Microlab Splitter Specification sheet pt9797
Contextual Info: MOTOROLA RF DATA MANUAL Prepared by Technical Information Center M otorola’s leadership position of RF power, small-signal transistors and hybrid amplifiers is by research and new product development coupled with a com plete in-house m anufacturing ca pa b ility in clu d in g silico n g row ing,

2025h

Abstract: stair case taking off sheet I 3009H DATA SHEET 2025h CXA3562AR CXA7000R CXD3526GG 300eh 200D 2028H
Contextual Info: CXD3526GG Digital Signal Driver/Timing Generator Description The CXD3526GG incorporates digital signal processor type RGB driver, color shading correction and timing generator functions onto a single IC. Operation is possible with a system clock up to 85 [MHz] max. . This

MSM514201

Contextual Info: O K I semiconductor MSM514201_ 1,048,576-Word x 1-Bit Serial GEN ERA L DESCRIPTION MSM514201 is a serial register in 1,048,576-word x 1-bit configuration featuring medium speed

AT41511

Contextual Info: HEWLETT- PAC KARD/ CMPNTS blE T> • 4447584 QOCHaiS 77b H H P A W hp% H EW LETT mL'KM PACKARD Low Cost General Purpose Transistors Technical Data AT-41511 AT-41586 Features D escription • L ow N oise F ig u re 1.4 dB Typical a t 1 GHz 1.7 dB Typical a t 2 GHz

2028H

Abstract: 302-2H
Contextual Info: CXD3526GG Digital Signal Driver/Timing Generator Description The CXD3526GG incorporates digital signal processor type RGB driver, color shading correction and timing generator functions onto a single IC. Operation is possible with a system clock up to 85 [MHz] max. . This

smd code book 13t

Abstract: CL-MD4450 varistor xf 030 Metal-Oxide Varistor S14 sds relay 5v s4 smd code Yj 33 HA 1115 VIA VT 2021 44t smd transistor 3453T
Contextual Info: CL-MD34XX Data Book CIRRUS LOGIC FEATURES • Complete PC telephony solution — — — — — — Up to 33.6-kbps data rates Highly integrated three- or four-chip set Controller-based robust platform Exceeds Microsoft PC 95 requirements Full-duplex, echo-cancelled digital speakerphone

diode marking L5 sot363

Abstract: VISHAY diode MARKING er VISHAY SOT LOT CODE marking L5 sot363 sot363 ON Marking DS vishay siliconix code marking
Contextual Info: _ SM906DL Vishay Siliconix New Product N-Channel 20-V D-S MOSFET PRODUCT SUMMARY r DS<on) (Œ ) lD (mA) 2.0 9 V q s = 4.5 V 250 2.5 V GS = 2.5 V 150 V DS(V) 20 SOT-363 S C-70 (6*Leads) Marking Code XX £ Lot Traceability

MPY16HJ

Abstract: 64 PIN CERDIP 643S 29517 trw mpy 16hj l683 AM29520 vts 132/14 29l517 AM29516DC
Contextual Info: Family A m 29516/17 Family Am29516/17 1 6 x 1 6-Bit Parallel Multipliers DISTINCTIVE CHARACTERISTICS • • • • High speed 1 6 x 1 6 multiplier T w o 's com plem ent, unsigned o r mixed operands Full product multiplexed a t output Improved speed: 38ns clocked m ultiply A devices

74F10

Abstract: F384 AM25LS14
Contextual Info: July 1989 54F/74F384 8-Bit Serial/Parallel Twos Complement Multiplier General Description The ’F384 is an 8 -bit by 1-bit sequential logic element that multiplies two numbers represented in twos complement notation. The device implements Booth's algorithm internal­