YEC 103 C Search Results

Contextual Info: microelectronics Preliminary Data Sheet November 1998 group Lucent Technologies Bell Labs Innovations TFRA08C13 Octal T1/E1 Framer Features Facility Data Link Features • Eight independent T1/E1 transmit and receive framers. m Internal DS1 transmit clock synthesis—no external

AXP 188 ba

Abstract: 21071-DA 2mb1100 AXP 188 IC 5188b RSAD 5111 1M 21071-BA 82378IB 21071AA d327c
Contextual Info: m DECchip 21071-AA, 21072-AA Core Logic Data Sheet m A p ril 1994 21071-AA, 21072-A A Features: • Supports the entire fam ily of the DECchip 21064 Alpha AXP m icroprocessors • DECchip 21071-AA: 128-bit cache/64-bit memory • DECchip 21072-AA: 128-bit cache/128-bit

RBS 2202

Abstract: Lucent SLC 2000 4558 X data sheet SA4-13 data sheet ic 7495 B20-B2E HDB3 CODING DECODING FPGA SA5-27 5N26 FRM8 relay datasheet
Contextual Info: Preliminary Data Sheet October 2000 TFRA08C13 OCTAL T1/E1 Framer Features • Eight independent T1/E1 transmit and receive framers. ■ Internal DS1 transmit clock synthesis—no external oscillator necessary. ■ Comprehensive alarm reporting and performance

SA4-13

Abstract: SA5-27 RHS25
Contextual Info: Device Advisory October 1999 TFRA08C13 Device Advisory for Version 2.0 of the Device Introduction This advisory refers to version 2.0 of the TFRA08C13 Octal T1/E1 Framer. This advisory addresses the timing issue of the microprocessor interface when FDL registers are accessed. This advisory also introduces guidelines for interfacing TFRA08C13 with processors of the Motorola* M68000 family.